Abstract: It is an object to provide a high-precision method for forming deep holes of elliptic pattern, which can improve hole directionality on the short diameter side, the hole directionality being possibly deteriorated as a result of excessive polymer deposition in the initial etching stage. The insulating film dry etching method is for treating a work on which a mask of elliptic pattern is formed with a fluorocarbon gas, wherein the etching process is divided into a first and second steps after the etching is started, the first step operating to deposit a polymer at a rate set lower than that in the second step, and controlling step time in accordance with ellipticity (long diameter/short diameter ratio) of the elliptic pattern.

Abstract: A combination of a dry oxidizing, wet etching, and wet cleaning processes are used to remove particle defects from a wafer after ion implantation, as part of a wafer bonding process to fabricate a SOI wafer. The particle defects on the topside and the backside of the wafer are oxidized, in a dry strip chamber, with an energized gas. In a wet clean chamber, the backside of the wafer is treated with an etchant solution to remove completely or partially a thermal silicon oxide layer, followed by exposure of the topside and the backside to a cleaning solution. The cleaning solution contains ammonium hydroxide, hydrogen peroxide, DI water, and optionally a chelating agent, and a surfactant. The wet clean chamber is integrated with the dry strip chamber and contained in a single wafer processing system.

Abstract: One example of a separation-material composition for a photo-resist according to the present invention comprises 5.0 weight % of sulfamic acid, 34.7 weight % of H2O, 0.3 weight % of ammonium 1-hydrogen difluoride, 30 weight % of N,N-dimethylacetamide and 30 weight % of diethylene glycol mono-n-buthyl ether. Another example of a separation-material composition for a photo-resist according to the present invention comprises 1-hydroxyethylidene-1, 3.0 weight % of 1-diphosphonic acid, 0.12 weight % of ammonium fluoride, 48.38 weight % of H2O and 48.5 weight % of diethylene glycol mono-n-buthyl ether. The separation-material composition for the photo-resist is mainly used for a medicinal liquid washing liquid/scientific liquid in order to remove the photo-resist residuals and the by-product polymer after an ashing process of a photo-resist mask.

Abstract: In the polishing head of a CMP device, the diaphragm which includes an elastic body film is fixed to a carrier plate with the diaphragm stop ring which includes a metallic material. The screw stop of the retaining ring which includes a resin material is done to this diaphragm stop ring with a screw from a lower part. A groove is formed in the under surface of a retaining ring, and the screw hole for doing the screw stop of the retaining ring is formed in the groove. By pressurizing the space sealed by a diaphragm, membrane, etc., a semiconductor wafer is pushed against a polishing pad via membrane, and CMP treatment of the semiconductor wafer is done.

Abstract: To provide a resist composition capable of prevention of the formation of abnormal resist pattern shapes for efficient, high-precision formation of fine, high-resolution resist patterns, a resist pattern forming process capable of efficient, high-precision formation of finer, high-resolution resist patterns by using the resist composition, and a method for manufacturing a semiconductor device. The resist composition of the present invention includes a base resin, a photoacid generator, a first additive, and a second additive, wherein the pKa of the second additive is higher than the pKa of the first additive, and at a resist formation temperature, the vapor pressure of the second additive is lower than the vapor pressure of the first additive.

Abstract: A phase shift mask includes a quartz substrate having a main surface partially dug, and a Cr film deposited on the main surface. The dug portion includes an undercut provided such that the Cr film partially serves as an eaves, and the Cr film has a ? opening exposing a portion of the dug portion, and a first subopening exposing an end of the dug portion.

Abstract: An apparatus and a method for fabricating a semiconductor device are provided. The method can efficiently remove by-products from a foreline connected to a process chamber. The apparatus includes a remote plasma source, which generates a plasma gas. The plasma gas is guided to the foreline, so as to remove impurities formed on an inner wall of the foreline.

Abstract: Disclosed herein a method of manufacturing a semiconductor device, the method including: forming a plurality of layers over a semiconductor substrate having a lower structure including a transistor; forming a photoresist layer over the plurality of layers and patterning the photoresist layer in a contact hole shape; and etching the plurality of layers through a predetermined etching method using the patterned photoresist layer as an etching mask to form a contact hole.

Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a recess, the substrate being formed on a backside of a semiconductor wafer, forming pores in the substrate in an area of the recess, and forming in the recess a material having a thermal conductivity which is greater than a thermal conductivity of the substrate. In another aspect, a method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.

Abstract: There is provided a method for producing a semiconductor device which forms a deep hole contact ultra-finely without generating distortion of an opening and Twisting in a contact hole. The method for producing a semiconductor device has the steps of: (a) forming a contact hole 6 in an upper part of an insulation layer 3 containing silicon oxide by dry etching using a first etching gas which contains Xe gas, and (b) deepening the contact hole 7 in the insulation layer 3 by dry etching using a second etching gas which does not contain Xe gas. It is preferable that the first etching gas contains a gas obtained by diluting an etching gas with Xe gas or with a mixed gas of Xe gas and Ar gas. It is preferable that the second etching gas contains a gas obtained by diluting an etching gas with Ar gas. It is preferable that the etching gas contains a mixed gas of a fluorocarbon gas and O2 gas.

Abstract: A method for manufacturing a semiconductor device includes forming a photo-resist pattern above a first film, implanting a predetermined dopant that increases an etching rate of the first film into the first film using the photo-resist pattern as a mask, thereby forming an implantation layer in the first film, and etching a first portion of the first film, which is at least a part of the implantation layer, using the photo-resist pattern as a mask.

Abstract: Compositions and methods for removal of barrier layer materials by a chemical mechanical polishing technique are provided. In one aspect, the invention provides a composition adapted for removing a barrier layer material in a chemical mechanical polishing technique including at least one reducing agent selected from the group of bicarboxylic acids, tricarboxylic acids, and combinations thereof, at least one reducing agent selected from the group of glucose, hydroxylamine, and combinations thereof, and deionized water, wherein the composition has a pH of about 7 or less. The composition may be used in a method for removing the barrier layer material including applying the composition to a polishing pad and polishing the substrate in the presence of the composition to remove the barrier layer.

Abstract: A display panel includes a substrate having a display area and a blank area. The blank area includes at least one of a non-metal line region and a metal-line region. The non-metal line region includes a plurality of insulating patterns and a first conductive pattern layer formed on the substrate. The insulating patterns are isolated from each other by the first conductive pattern layer. The metal-line region includes an insulating multilayer formed on the substrate and a conductive pattern layer formed on the insulating multilayer. Several isolated zones are formed by the conductive pattern layer on the surface of the insulating multilayer.

Abstract: [Subject In a plasma process using an ammonia gas after conducting a plasma process by using a process gas containing fluorine and carbon to a silicone-containing substrate, an ammonium silicofluoride having toxicity and water absorbancy is formed on the substrate. [Means for Solution]After conducting the plasma process using an ammonia gas, the substrate is heated to a temperature not lower than the decomposition temperature of the ammonium silicofluoride to decompose the ammonium silicofluoride in a process container in which the plasma process was conducted, or in a process container connected with the processing vessel which the plasma process was conducted therein and is isolated from a clean room atmosphere.

Abstract: According to one aspect of the invention, a semiconductor substrate processing apparatus and a method for processing semiconductor substrates are provided. The semiconductor substrate processing apparatus may include a semiconductor substrate support, a dispense head positioned over the semiconductor substrate support, a liquid container, and a transport subsystem. A semiconductor substrate may be placed on the semiconductor substrate support while a first semiconductor processing liquid is dispensed thereon. The wafer may also be spun by the semiconductor substrate support to remove the first semiconductor processing liquid. The transport subsystem may transport the semiconductor substrate to the liquid container where the semiconductor substrate may be immersed in a second semiconductor processing liquid.

Abstract: A method of chemical-mechanical polishing (CMP) and a method of forming an isolation layer using the same are provided. The method of chemical-mechanical polishing includes performing a first chemical-mechanical polishing operation on an insulating layer having a zeta potential with a first polarity by supplying a first slurry on the insulating layer, wherein the first slurry includes a first abrasive and ionic surfactants having a zeta potential with a second polarity opposite to the first polarity. The method of forming an isolation layer includes forming a mask layer on a substrate, etching the substrate to a desired depth using the mask layer such that a trench is formed in the substrate, forming the insulating layer on the substrate and performing the first chemical-mechanical polishing operation described above.

Abstract: A planarization process for a pre-damascene structure is described, wherein the pre-damascene structure includes a metal hard mask that is disposed on a first material layer with a damascene opening therein and a second material layer that fills the damascene opening and covers the metal hard mask. A first CMP step is conducted using a first slurry to remove the second material layer outside the damascene opening. A second CMP step is conducted using a second slurry to remove the metal hard mask.

Abstract: Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device can include at least two gate structures spaced apart from each other on a semiconductor substrate, a silicon nitride layer covering the semiconductor substrate and the gate structures, an interlayer dielectric layer on the silicon nitride layer, and a buffer layer interposed between the silicon nitride layer and the interlayer dielectric layer to buffer stress between the silicon nitride layer and the interlayer dielectric layer. The buffer layer has a tensile stress characteristic, while the silicon nitride layer and the interlayer dielectric layer have a compressive stress characteristic. Therefore, the buffer layer buffers the compressive stress of both the silicon nitride layer and the interlayer dielectric layer. Accordingly, the delamination or the damage of the silicon nitride layer and the interlayer dielectric layer is inhibited.

Abstract: A method of etching a silicon substrate is described. The method includes bonding a first silicon substrate to a sacrificial silicon substrate. The first silicon substrate is etched. A pressure is applied at an interface of the first silicon substrate and the sacrificial silicon substrate to cause the first silicon substrate to separate from the sacrificial silicon substrate. An apparatus having metal blades can be used to separate the substrates.

Abstract: A processing method which, when an organic film layer such as a PR film layer 202 formed on the surface of a wafer W is to be removed from an SiO2 film layer 204 below it by generating plasma of a process gas in a chamber 1 comprises the step of using O2 gas as the process gas to remove the organic film layer at a first pressure, e.g., 20 mTorr, lower than in a conventional case, and the step of using the same O2 gas to remove the organic film layer at a second pressure, e.g., 200 mTorr, higher than the first pressure.

Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.

Abstract: A transition metal substituted, amorphous mesoporous silica framework with a high degree of structural order and a narrow pore diameter distribution (±0.15 nm FWHM) was synthesized and used for the templated growth of GaN nanostructures, such as single wall nanotubes, nanopipes and nanowires. The physical properties of the GaN nanostructures (diameter, diameter distribution, electronic characteristic) can be controlled by the template pore diameter and the pore wall chemistry. GaN nanostructures can find applications, for example, in nanoscale electronic devices, such as field-emitters, and in chemical sensors.

Abstract: A complementary metal-oxide-semiconductor (CMOS) device comprising a substrate, a first type of metal-oxide-semiconductor (MOS) transistor, a second type of MOS transistor, an etching stop layer, a first stress layer and a second stress layer is provided. The substrate has a first and a second active region. The first active region is isolated from the second active region through an isolation structure. The first type of MOS transistor is disposed in the first active region of the substrate and the second type of MOS transistor is disposed in the second active region of the substrate. The etching stop layer covers conformably the first type of MOS transistor, the second type of MOS transistor and the isolation structure. The first stress layer is disposed on the etching stop layer in the first active region and the second stress layer is disposed on the etching stop layer in the second active region.

Abstract: A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate.

Abstract: The present disclosure provides a method for removing photoresist residue from a low k dielectric above a semiconductor substrate. The method includes creating a first opening in the low k dielectric extending a first depth towards an underlying conductor, and applying and patterning a material above the low k dielectric. In-situ first and second plasma environments are provided, with a bias power being applied to the substrate to attract ion bombardment during the second plasma environment. Trenches can be etched in the low k dielectric, the trenches extending a second depth less than the first depth. Material for the first and second plasmas and the ion bombardment are selected for removing residue of the material from the low k dielectric.

Abstract: The invention relates to a device for introducing light into a waveguide, which device comprises: a light source, preferably an electro-optical converter, more preferably a VCSEL, for generating a light beam; a reflector for receiving at least a part of the light beam and for reflecting at least a part of the received part, wherein the waveguide and the material layer lie substantially mutually in line and both rest at least partially on a substantially flat substrate, wherein the light source and the reflector are positioned relative to the waveguide such that at least a part of the reflected part is introduced into the waveguide. The invention also relates to a device for emitting light from a waveguide. The invention further relates to a method for manufacturing such devices.

Abstract: A wafer planarization process with a conditioning tool having an electrical insulator that electrically insulates the abrasive surface of the conditioning tool. The electrical insulator extends the useful life of the abrasive surface of the conditioning tool by reducing the level of electrochemically driven corrosion.