Abstract: According to an embodiment, a semiconductor structure includes a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion; and a metal layer formed on and in contact with the second monocrystalline semiconductor portion.

Abstract: A semiconductor structure includes a substrate, a first well having a first conductive type, a second well having a second conductive type, a body region, a first doped region, a second doped region, a third doped region and a field plate. The first and second wells are formed in the substrate. The body region is formed in the second well. The first and second doped regions are formed in the first well and the body region, respectively. The second and first doped regions have the same polarities, and the dopant concentration of the second doped region is higher than that of the first doped region. The third doped region is formed in the second well and located between the first and second doped regions. The third and first doped regions have reverse polarities. The field plate is formed on the surface region between the first and second doped regions.

Abstract: A bipolar junction transistor (BJT), which includes a collector layer, a base layer on the collector layer, an emitter layer on the base layer, and a recess region embedded in the collector layer, is disclosed. A base-collector plane is between the base layer and the collector layer. The recess region is may be below the base-collector plane. Further, the recess region and the base layer are a first type of semiconductor material. By embedding the recess region in the collector layer, the recess region and the collector layer form a first P-N junction, which may provide a point of avalanche for the BJT. Further, the collector layer and the base layer form a second P-N junction. By separating the point of avalanche from the second P-N junction, the BJT may avalanche robustly, thereby reducing the likelihood of avalanche induced failures, particularly in silicon carbide (SiC) BJTs.

Abstract: In the case of adjacent high voltage nodes in which one node is protected by a lateral BJT clamp, the irreversible burnout due to transient latch-up between the two adjacent high voltage pins of the structure is avoided by increasing the base contact region by including a sinker connected to the base.

Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.

Abstract: The present disclosure provides an ESD protection device. The device contains a bipolar junction transistor device that includes a collector, a base, and an emitter. The collector includes a first doped element and a more heavily doped second doped element disposed over the first doped element. The first and second doped elements each have a first doping polarity. The base is located adjacent to the collector and includes a third doped element having a second doping polarity different from the first doping polarity. A p-n junction is formed between the third doped element and one of the first and second doped elements. The emitter is formed over the base. The emitter includes a fourth doped element having the first doping polarity and forming a p-n junction with the third doped element. The fourth doped element is more heavily doped than the third doped element.

Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first conductivity type cathode layer, a first conductivity type base layer, a second conductivity type anode layer, a second conductivity type semiconductor layer, a first conductivity type semiconductor layer, an buried body, and a second electrode. The first conductivity type semiconductor layer is contiguous to the second conductivity type semiconductor layer in a first direction, and extends on a surface of the anode layer in a second direction that intersects perpendicularly to the first direction. The buried body includes a bottom portion and a sidewall portion. The bottom portion is in contact with the base layer. The sidewall portion is in contact with the base layer, the anode layer, the second conductivity type semiconductor layer and the first conductivity type semiconductor layer. The buried body extends in the first direction.

Abstract: Aspects of the invention provide a method of forming a bipolar junction transistor. The method includes: providing a semiconductor substrate including a uniform silicon nitride layer over an emitter pedestal, and a base layer below the emitter pedestal; applying a photomask at a first end and a second end of a base region; and performing a silicon nitride etch with the photomask to simultaneously form silicon nitride spacers adjacent to the emitter pedestal and exposing the base region of the bipolar junction transistor. The silicon nitride etch may be an end-pointed etch.

Abstract: A semiconductor device includes an n-type first guard ring layer provided between an emitter layer and a collector layer on a surface side of a base layer, and having a higher n-type impurity concentration than the base layer, and an n-type second guard ring layer provided between the first guard ring layer and a buried layer, connected to the first guard ring layer and the buried layer, and having a higher n-type impurity concentration than the base layer. The first guard ring layer has an n-type impurity concentration profile decreasing toward the second guard ring layer side, and the second guard ring layer has an impurity concentration profile decreasing toward the first guard ring layer side.

Abstract: An electrostatic discharge protection device comprises a substrate with a first conductivity, a gate, a drain structure and a source structure. The gate is disposed on a surface of the substrate. The drain structure with a second conductivity type comprises a first doping region with a first doping concentration disposed adjacent to the gate and extending into the substrate from the surface of the substrate, a second doping region extending into and stooped at the first doping region from the surface of the substrate and having a second doping concentration substantially greater than the first doping concentration, and a third doping region disposed in the substrate beneath the second doping region and having a third doping concentration substantially greater than the first doping concentration. The source structure with the second conductivity is disposed in the substrate and adjacent to the gate electrode.

Abstract: A semiconductor device in which only the trigger voltage can be controlled without change in the hold voltage. In the semiconductor device, a protection device includes a lower doped collector layer, a sinker layer, a highly-doped collector layer, an emitter layer, a highly-doped base layer, a base layer, a first conductivity type layer, and a second conductivity type layer. The second conductivity type layer is formed in the lower doped collector layer and located between the base layer and first conductivity type layer. The second conductivity type layer has a higher impurity concentration than the lower doped collector layer.

Abstract: A power SiGe heterojunction bipolor transistor (HBT) with improved drive current by strain compensation and methods of manufacture are provided. A method includes adding carbon in a continuous steady concentration in layers of a device including a subcollector layer, a collector layer, a base buffer layer, a base layer, and an emitter buffer layer.

Abstract: An electrostatic discharge (ESD) protection device includes a well region formed from semiconductor material with a first doping type and a floating base formed from semiconductor material with a second doping type. The floating base is disposed vertically above the well region. The ESD also includes a first terminal receiving region formed from semiconductor material with a third doping type. The first terminal receiving region is disposed vertically above the floating base. The ESD further includes a second terminal receiving region. The second terminal receiving region is laterally spaced apart from the first terminal receiving region by silicon trench isolation (STI) region. In some embodiments, the second terminal receiving region is formed from semiconductor material with the third doping type to form a bipolar junction transmitter (BJT) or with a fourth doping type to form a silicon controlled rectifier (SCR).

Abstract: A bipolar semiconductor component, in particular a diode, comprising an anode structure which controls its emitter efficiency in a manner dependent on the current density in such a way that the emitter efficiency is low at small current densities and sufficiently high at large current densities, and an optional cathode structure, which can inject additional holes during commutation, and production methods therefor.

Abstract: The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region.

Abstract: Disclosed are a transistor and a method of forming the transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal.

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. The bipolar junction transistor may include a plurality of emitters that are arranged in distinct emitter fingers. A silicide layer is formed that covers an extrinsic base layer of the bipolar junction transistor and that fills the gaps between adjacent emitters. Non-conductive spacers on the emitter sidewalls electrically insulate the emitters from the silicide layer. The emitters extend through the extrinsic base layer and the silicide layer to contact the intrinsic base layer. The emitters may be formed using sacrificial emitter pedestals in a replacement-type process.

Abstract: Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent to a trench isolation region within a substrate. Mask layer(s) cover the trench isolation region and further extend laterally onto the edge portion of the collector region. A first section of an intrinsic base layer is positioned above a center portion of the collector region and a second section of the intrinsic base layer is positioned above the mask layer(s). During processing these mask layer(s) prevent divot formation in the upper corner of the trench isolation region at the isolation region-collector region interface and further limit dopant diffusion from a subsequently formed raised extrinsic base layer into the collector region.

Abstract: A bipolar transistor is disclosed, which includes a collector region, a base region, an emitter region and field plates. Each field plate is present in a structure of a flat sidewall covering one side face of the active region so that it also covers the collector region from one side. The field plate has its surface parallel to the side face of the active region and is isolated from the side face of the active region by a pad oxide layer. The field plate has its top lower than the surface of the active region. The bipolar transistor is capable of improving the breakdown voltage of the device without increasing the collector resistance or deteriorating the frequency characteristic. A method of manufacturing bipolar transistor is also disclosed.

Abstract: A power semiconductor diode is provided. The power semiconductor diode includes a semiconductor substrate having a first emitter region of a first conductivity type, a second emitter region of a second conductivity type, and a drift region of the first conductivity type arranged between the first emitter region and the second emitter region. The drift region forms a pn-junction with the second emitter region. A first emitter metallization is in contact with the first emitter region. The first emitter region includes a first doping region of the first conductivity type and a second doping region of the first conductivity type. The first doping region forms an ohmic contact with the first emitter metallization, and the second doping region forms a non-ohmic contact with the first emitter metallization. A second emitter metallization is in contact with the second emitter region.

Abstract: A semiconductor device includes a first conductive type semiconductor layer formed on a substrate; a first conductive type embedded layer formed between the substrate and the semiconductor layer; a second conductive type well formed on the semiconductor layer; a first conductive type first contact layer that is positioned on the semiconductor layer, separate from the well; a second conductive type second contact layer formed on the well; a first conductive type third contact layer formed on the well between the first and second contact layers; and a first conductive type deep layer formed between the embedded layer and the first contact layer and in contact with the first contact layer. A minimum point in the effective impurity concentration profile along a straight line that extends in a vertical direction and passes through the embedded layer and the second part exists between the embedded layer and the first part.

Abstract: Disclosed are example bipolar transistors capable of reducing the area of a collector, reducing the distance between a base and a collector, and/or reducing the number of ion implantation processes. A bipolar transistor may includes a trench formed by etching a portion of a semiconductor substrate. A first collector may be formed on the inner wall of the trench. A second collector may be formed inside the semiconductor substrate in the inner wall of the trench. A first isolation film may be formed on the sidewall of the first collector. An intrinsic base may be connected to the third collector. An extrinsic base may be formed on the intrinsic base and inside the first isolation film. A second isolation film may be formed on the inner wall of the extrinsic base. An emitter may be formed by burying a conductive material inside the second isolation film.

Abstract: The present disclosure provides an ESD protection device. The device contains a bipolar junction transistor device that includes a collector, a base, and an emitter. The collector includes a first doped element and a more heavily doped second doped element disposed over the first doped element. The first and second doped elements each have a first doping polarity. The base is located adjacent to the collector and includes a third doped element having a second doping polarity different from the first doping polarity. A p-n junction is formed between the third doped element and one of the first and second doped elements. The emitter is formed over the base. The emitter includes a fourth doped element having the first doping polarity and forming a p-n junction with the third doped element. The fourth doped element is more heavily doped than the third doped element.

Abstract: An ESD protection apparatus comprises a substrate, a low voltage p-type well and a low voltage n-type well formed on the substrate. The ESD protection device further comprises a first P+ region formed on the low voltage p-type well and a second P+ region formed on the low voltage n-type well. The first P+ region and the second P+ region are separated by a first isolation region. The breakdown voltage of the ESD protection apparatus is tunable by adjusting the length of the first isolation region.

Abstract: According to one exemplary embodiment, a fin-based bipolar junction transistor (BJT) includes a wide collector situated in a semiconductor substrate. A fin base is disposed over the wide collector. Further, a fin emitter and an epi emitter are disposed over the fin base. A narrow base-emitter junction of the fin-based BJT is formed by the fin base and the fin emitter and the epi emitter provides increased current conduction and reduced resistance for the fin-based BJT. The epi emitter can be epitaxially formed on the fin emitter and can comprise polysilicon. Furthermore, the fin base and the fin emitter can each comprise single crystal silicon.

Abstract: Disclosed are embodiments of an improved transistor structure (e.g., a bipolar transistor (BT) structure or heterojunction bipolar transistor (HBT) structure) and a method of forming the transistor structure. The structure embodiments can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method embodiments allow for self-aligning of the emitter to base regions and further allow the geometries of different features (e.g., the thickness of the dielectric layer, the width of the conductive strap, the width of the dielectric spacer and the width of the emitter layer) to be selectively adjusted in order to optimize transistor performance.

Abstract: Disclosed is an integrated circuit and a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate comprising a pair of isolation regions separated by an active region comprising a collector; forming a base layer stack over said substrate; forming a migration layer having a first migration temperature and an etch stop layer; forming a base contact layer having a second migration temperature; etching an emitter window in the base contact layer, thereby forming cavities extending from the emitter window; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material.

Abstract: A bipolar junction transistor includes a first trench element isolation film, a second trench element isolation film, a first base region, a second base region, a collector region, a first well, a second well, an emitter, a collector, and bases. The second well is formed by implanting an n-type impurity into the semiconductor substrate, and the emitter is formed by implanting the n-type impurity into the emitter region between the first trench element isolation film and the second well. The collector is formed by implanting the n-type impurity into the collector region between the first well and the second trench element isolation film, and the bases are formed by implanting the p-type impurity into the first base region and into the second base region between the emitter region and the second well.

Abstract: The present disclosure relates to a silicon carbide (SiC) bipolar junction transistor (BJT), where the surface region between the emitter and base contacts (1, 2) on the transistor is given a negative electric surface potential with respect to the potential in the bulk SiC. The present disclosure also relates to a method for increasing the current gain in a silicon carbide (SiC) bipolar junction transistor (BJT) by the reduction of the surface recombination at the SiC surface between the emitter and base contacts (1, 2) of the transistor.

Abstract: A bipolar junction transistor and a manufacturing method for the same are provided. The bipolar junction transistor includes a well region, an emitter electrode, a base electrode, a collector electrode, and a conductive layer. The emitter electrode, the base electrode and the collector electrode are separated from each other by the well region. The conductive layer is on the well region between the base electrode and the collector electrode.

Abstract: The invention relates to a semiconductor device (10) with a substrate (11) and a semiconductor body (1) comprising a bipolar transistor with in that order a collector region (2), a base region (3), and an emitter region (4), wherein the semiconductor body comprises a projecting mesa (5) comprising at least a portion of the collector region (2) and the base region (3), which mesa is surrounded by an isolation region (6). According to the invention, the semiconductor device (10) also comprises a field effect transistor with a source region, a drain region, an interposed channel region, a superimposed gate dielectric (7), and a gate region (8), which gate region (8) forms a highest part of the field effect transistor, and the height of the mesa (5) is greater than the height of the gate region (8). This device can be manufactured inexpensively and easily by a method according to the invention, and the bipolar transistor can have excellent high-frequency characteristics.

Abstract: Methods for fabricating bipolar junction transistors, bipolar junction transistors made by the methods, and design structures for a bipolar junction transistor. The bipolar junction transistor includes a dielectric layer on an intrinsic base and an extrinsic base at least partially separated from the intrinsic base by the dielectric layer. An emitter opening extends through the extrinsic base and the dielectric layer. The dielectric layer is recessed laterally relative to the emitter opening to define a cavity between the intrinsic base and the extrinsic base. The cavity is filled with a semiconductor layer that physically links the extrinsic base and the intrinsic base together.

Abstract: In accordance with one embodiment, the present invention provides a bipolar junction transistor including an emitter region; a base region; a first isolation between the emitter region and the base region; a gate on the first isolation region and overlapping at least a portion of a periphery of the emitter region; a collector region; and a second isolation between the base region and the collector region.

Abstract: An electrostatic discharge (ESD) protection element includes a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.

Abstract: High performance bipolar transistors with raised extrinsic self-aligned base are integrated into a BiCMOS structure containing CMOS devices. By forming pad layers and raising the height of an intrinsic base layer relative to the source and drain of preexisting CMOS devices and by forming an extrinsic base through selective epitaxy, the effect of topographical variations is minimized during a lithographic patterning of the extrinsic base. Also, by not employing any chemical mechanical planarization process during the fabrication of the bipolar structures, complexity of process integration is reduced. Internal spacers or external spacers may be formed to isolate the base from the emitter. The pad layers, the intrinsic base layer, and the extrinsic base layer form a mesa structure with coincident outer sidewall surfaces.

Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.

Abstract: A bipolar junction transistor (BJT) device including a base region, an emitter region and a collector region comprises a substrate, a deep well region in the substrate, a first well region in the deep well region to serve as the base region, a second well region in the deep well region to serve as the collector region, the second well region and the first well region forming a first junction therebetween, and a first doped region in the first well region to serve as the emitter region, the first doped region and the first well region forming a second junction therebetween, wherein the first doped region includes a first section extending in a first direction and a second section extending in a second direction different from the first direction, the first section and the second section being coupled with each other.

Abstract: A junction transistor, comprising, on a substrate an emitter layer, a collector layer, and a base layer that comprises a graphene layer, wherein an emitter barrier layer is arranged between the base layer and the emitter layer, and a collector barrier layer is arranged between the base and the collector layers and adjacent to the graphene layer, characterized in that the collector barrier layer is a compositionally graded material layer, which has an electron affinity that decreases in a direction pointing from the base layer to the collector layer.

Abstract: An apparatus includes an electrostatic discharge (ESD) protection device. In one embodiment, the protection device electrically coupled between a first node and a second node of an internal circuit to be protected from transient electrical events. The protection device includes a bipolar device or a silicon-controlled rectifier (SCR). The bipolar device or SCR can have a modified structure or additional circuitry to have a selected holding voltage and/or trigger voltage to provide protection over the internal circuit. The additional circuitry can include one or more resistors, one or more diodes, and/or a timer circuit to adjust the trigger and/or holding voltages of the bipolar device or SCR to a desired level. The protection device can provide protection over a transient voltage that ranges, for example, from about 100 V to 330V.

Abstract: Embodiments relate to a bipolar transistor that includes a body region having a fin structure. At least one terminal region may be formed over at least a portion of the body region. The at least one terminal region may be formed as an epitaxially grown region. Embodiments also relate to a vertically integrated electronic device that includes a first terminal region, a second terminal region and a third terminal region. The second terminal region may be arranged over at least a portion of the third terminal region, and at least two of the first, second and third terminal regions may be formed as epitaxially grown regions.

Abstract: The present technology discloses a bipolar junction transistor (BJT) device integrated into a semiconductor substrate. The BJT device comprises a collector, a base and an emitter. The collector is of a first doping type on the substrate; the base is of a second doping type in the collector from the top surface of the semiconductor device and the base has a base depth; and the emitter is of a first doping type in the base from the top surface of the semiconductor device. The base depth is controlled by adjusting a layout width in forming the base.

Abstract: Conduction between source and drain or emitter and collector regions is an important characteristic in transistor operation, particularly for lateral bipolar transistors. Accordingly, techniques that can facilitate control over this characteristic can mitigate yield loss by promoting the production of transistors that have an increased likelihood of exhibiting desired operational performance. As disclosed herein, well regions are established in a semiconductor substrate to facilitate, among other things, control over the conduction between the source and drain regions of a lateral bipolar transistor, thus mitigating yield loss and other associated fabrication deficiencies. Importantly, an additional mask is not required in establishing the well regions, thus further mitigating (increased) costs associated with promoting desired device performance.

Abstract: A hydrogen ion sensing device of the present invention includes: a reference electrode; a sensing portion which senses hydrogen ions by contacting an ion aqueous solution; and a plurality of ring-like lateral bipolar junction transistors, each including a lateral collector, an emitter, a vertical collector and a floating gate connected to the reference electrode, with the emitter surrounded by the floating gate and the lateral collector, wherein the plurality of ring-like lateral bipolar junction transistors are formed on a common substrate and are connected in parallel.

Abstract: The present invention provides a semiconductor with a multilayered contact structure. The multilayered structure includes a metal contact placed on an active region of a semiconductor and a metal contact extension placed on the metal contact.

Abstract: A bipolar transistor at least includes a semiconductor substrate including an N? epitaxial growth layer and a P? silicon substrate, an N+ polysilicon layer, a tungsten layer, two silicide layers, a base electrode, an emitter electrode, and a collector electrode. The N+ polysilicon layer formed on the semiconductor substrate is covered with one of the silicide layers. The tungsten layer that is formed on the silicide layer is covered with the other silicide layer.

Abstract: Methods for fabricating bipolar junction transistors with self-aligned emitter and extrinsic base, bipolar junction transistors made by the methods, and design structures for a BiCMOS integrated circuit. The bipolar junction transistor is fabricated using a sacrificial emitter pedestal that provides a sacrificial mandrel promoting self-alignment between the emitter and the extrinsic base. The sacrificial emitter pedestal is subsequently removed to open an emitter window extending to the intrinsic base. An emitter is formed in the emitter window that lands on the intrinsic base.

Abstract: A buried layer architecture which includes a floating buried layer structure adjacent to a high voltage buried layer connected to a deep well of the same conductivity type for components in an IC is disclosed. The floating buried layer structure surrounds the high voltage buried layer and extends a depletion region of the buried layer to reduce a peak electric field at lateral edges of the buried layer. When the size and spacing of the floating buried layer structure are optimized, the well connected to the buried layer may be biased to 100 volts without breakdown. Adding a second floating buried layer structure surrounding the first floating buried layer structure allows operation of the buried layer up to 140 volts. The buried layer architecture with the floating buried layer structure may be incorporated into a DEPMOS transistor, an LDMOS transistor, a buried collector npn bipolar transistor and an isolated CMOS circuit.

Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

Abstract: Design and methods for fabricating bipolar junction transistors are described. In one embodiment, a semiconductor device includes a first fin comprising a first emitter region, a first base region, and a first collector region. The first emitter region, the first base region, and the first collector region form a bipolar junction transistor. A second fin is disposed adjacent and parallel to the first fin. The second fin includes a first contact to the first base region.

Abstract: In one embodiment, a semiconductor device is formed in a body of semiconductor material. The semiconductor device includes a charge compensating trench formed in proximity to active portions of the device. The charge compensating trench includes a trench filled with various layers of semiconductor material including opposite conductivity type layers.