Abstract: A test device for testing a semiconductor device including a TSV may comprise a ring oscillator including a plurality of inverters, a switch selectively connecting an output node of an inverter of the plurality of inverters and the TSV, and a controller controlling the switch.

Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

Abstract: According to one embodiment, a semiconductor device includes: a first switching element; a first interconnection; a first resistor; and a second interconnection. The first switching element includes a first control terminal, a first electrode terminal, and a first conductor terminal. The second switching element includes a second control terminal, a second electrode terminal, and a second conductor terminal. The first interconnection includes a first through a fourth interterminal interconnections. The first resistor is connected at a first end to the first control terminal. The second resistor is connected at a first end to the second control terminal and is connected at a second end to a second end of the first resistor. The second interconnection is provided between the first electrode terminal and the second electrode terminal and/or between the first control terminal and the second control terminal.

Abstract: A switch circuit including structures to reduce the effects of charge injection. In an embodiment, a first transistor of the switch circuit is to receive a first signal and first and second dummy transistors of the switch circuit are each to receive a second signal, wherein the first transistor is connected between the first and second dummy transistors. The second signal is complementary to the first signal. In another embodiment, the first transistor, the first dummy transistor and the second dummy transistors are each connected via respective body connections to a first low supply voltage.

Abstract: An RF switch includes a switchable RF transistor. The switchable RF transistor includes a stripe of a plurality of adjacent RF transistor fingers and at least one non-switchable dummy transistor that is arranged at an end of the stripe of the switchable RF transistor.

Abstract: A circuit includes first and second semiconductor switches each having a load path and control terminal and their load paths connected in series. At least one of the first and second switches includes a first semiconductor device having a load path and a control terminal, the control terminal coupled to the control terminal of the switch. A plurality of second semiconductor devices each have a load path between a first load terminal and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: A circuit includes an input/output (IO) circuit, a first node configured to have a first voltage level, a second node configured to have a second voltage level, a third node, and a switching circuit. The IO circuit has a set of transistors, and the third node is coupled to bulks of the set of transistors. The switching circuit is configured to couple the first node to the third node when the IO circuit is operated in an active mode; and couple the second node to the third node when the IO circuit is operated in an inactive mode. The first voltage level causes the set of transistors to have a first threshold voltage, the second voltage level causes the set of transistors to have a second threshold voltage, and an absolute value of the second threshold voltage is greater than that of the first threshold voltage.

Abstract: This document discloses, among other things, a switch circuit that includes a depletion-mode field-effect transistor (DMFET) having an ON-state and an OFF-state, wherein the DMFET is configured to couple a first node to a second node in the ON-state, and wherein the DMFET is configured to isolate the first node from the second node in the OFF-state, a negative charge pump that is coupled to a gate terminal of the DMFET, the charge pump configured to supply a negative charge pump voltage to the gate terminal of the DMFET, and a negative discriminator coupled to the charge pump, the discriminator configured to compare a first voltage at the first node and a second voltage at the second node and determine the negative charge pump voltage based on the comparison.

Abstract: An integrated circuit including a state retention node, a conductive clock network shielding and multiple state retention devices for maintaining a state of the integrated circuit during the low power state. The state retention node receives a state retention supply voltage which remains at an operative voltage level during a low power state. The conductive clock network shielding is distributed with clock signal conductors and is coupled to the state retention node. Each state retention device has a supply voltage input coupled to the clock network shielding so that it remains powered during the low power state. The state retention node may be implemented as a minimal set of conductive traces. A state retention buffer may be provided for buffering a power gating signal indicative of the low power state, in which the buffer has a supply voltage input coupled to the clock network shielding.

Abstract: A semiconductor processing device (10) of the present invention includes a processing circuit (1), a digital-analog conversion circuit (2), an output control circuit (3), at least one output port circuit (4), a connection control circuit (5), and an output switch circuit (6). The output port circuit (4) includes an output buffer (41), a first switch element (SW1), and a second switch element (SW2, SW3). When the second switch element is connected to the side of an output amplifier (42), the output port circuit (4) controls the ON resistance of a P channel MOS transistor (41a) and an N channel MOS transistor (41b) based on a signal amplified at the output amplifier (42) to output an analog signal from the output buffer (41).

Abstract: An apparatus for measuring RMS values of burst-fired currents includes a current sensor having a signal output, an analog-to-digital (A/D) converter coupled to the signal output of the current sensor, a digital processor coupled to an output of the A/D converter, and a digital memory coupled to the digital processor. Code segments stored in the digital memory are executable on the digital processor and implement a process of: a) initially sampling the output of the A/D converter; b) determining from the initial sampling a burst-fired current pattern; c) sampling the output of the A/D converter N times within a burst-fired current pattern to provide N samples; and d) calculating an RMS value from the N samples.

Abstract: Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor.

Abstract: According to one aspect of this disclosure, a circuit arrangement is provided, the circuit arrangement including an electronic component coupled to at least one common power supply node and configured to provide a first signal having a variation in time that is based on power supply via the at least one common power supply node; a detecting circuit coupled to the electronic component, the detecting circuit being configured to detect the first signal and to provide a digital switch array control signal based on the variation in time of the first signal; and a switch array coupled between the at least one common power supply node and at least one power supply source, the switch array being configured to control the power supply via the at least one common power supply node based on the digital switch array control signal.

Abstract: A device includes a first transistor coupled between first and second nodes, and including a control gate supplied with a first control signal, a second transistor coupled between the first node and a third node, and including a control gate supplied with the first control signal, a third transistor coupled between the third node and a fourth node, and including a control gate supplied with a second control signal, a fourth transistor coupled between the fourth node and a fifth node, and including a control gate supplied with the second control signal, and a fifth transistor coupled between the fifth node and the second nodes, and including a control gate supplied with the first control signal. Each of the second and fifth transistors is smaller in threshold voltage than the first transistor.

Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.

Abstract: A gate driver turns on/off a switching element Q1 by applying a control signal from a controller to a gate of the switching element. The switching element has the gate, a drain, and a source and contains a wide-bandgap semiconductor. The gate driver includes a parallel circuit that includes a first capacitor C1 and a first resistor R1 and is connected between the controller and the gate of the switching element and a short-circuit unit S4 that is connected between the gate and source of the switching element and short-circuits the gate and source of the switching element after a delay from an OFF pulse of the control signal.

Abstract: A load control device includes a switching unit which is connected to a power source and a load in series and has a switch device having a transistor structure, a control unit configured to control start-up and stop of the load, and a gate driving unit, which is electrically insulated from the control unit and outputs a gate driving signal to the gate electrode of the switch device. The control unit controls the gate driving unit to supply a higher driving power to the gate electrode of the switch device for a predetermined period of time starting at the start-up of the load than that in a steady state.

Abstract: A transistor monolithically integrated in a semiconductor body includes a first sub-transistor and a second sub-transistor that both include a first and second load contacts and a control contact for controlling an electric current through a load path. The first load contact of the first sub-transistor is electrically connected to the first load contact of the second sub-transistor and the second load contact of the first sub-transistor is electrically connected to the second load contact of the second sub-transistor. A control circuit is configured to cause the first sub-transistor to switch from a first state to a second state at a first point of time and to cause the second sub-transistor to switch from the first state to the second state at a second point of time subsequent to the first point of time.

Abstract: A switch circuit and an electronic device using the same include a power switch transistor, a controlling circuit, a regulated capacitor, and a capacitor. The power switch transistor is connected between an input and an output of the switch circuit. An output of the controlling circuit is connected to a controlling electrode of the power switch transistor and outputs pulse width modulation (PWM) signals to turn the power switch transistor on and off. The regulated capacitor is connected between an output of the switch circuit and ground. The capacitor is connected between an output of the controlling circuit and ground for increasing an inclination of a rising edge and a falling edge of PWM signals to slow down the speed of switching the power switch transistor on and off, thereby making the regulated capacitor charge slowly and the output voltage of the switch circuit stable.

Abstract: A switching-element drive circuit that is configured to be applied to a power converter includes: a switching element; and a control unit that controls an operation of the switching element. The control unit includes a drive-voltage control unit that is configured to be capable of changing a switching speed of the switching element based on a power supply current.

Abstract: An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

Abstract: The disclosed invention provides a semiconductor device capable of suitably controlling the level of an enable signal to resolve NBTI in a PMOS transistor. An input node receives an input signal alternating between high and low levels during normal operation and fixed to a high level during standby. A detection unit receives a signal through the input node and outputs an enable signal. The detection unit sets the enable signal to a low level upon detecting that the input node remains at a high level for a predetermined period. A signal transmission unit includes a P-channel MOS transistor and transmits a signal input to the input node according to control by the enable signal.

Abstract: A method of actuating a semiconductor device includes providing a transistor including a substrate and a first electrically conductive material layer stack positioned on the substrate. The first electrically conductive material layer stack includes a reentrant profile. A second electrically conductive material layer includes first and second discrete portions in contact with first and second portions of a semiconductor material layer that conforms to the reentrant profile and is in contact with an electrically insulating material layer that conforms to the reentrant profile. A voltage is applied between the first discrete portion and the second discrete portion of the second electrically conductive material layer. A voltage is applied to the first electrically conductive material layer stack to modulate a resistance between the first discrete portion and the second discrete portion of the second electrically conductive material layer.

Abstract: The present invention provides a switching device capable of further minimizing the ON resistance of a switching element. Switching element has field application electrode that is connected to semiconductor substrate with insulating film interposed therebetween. Field control unit of driving unit is connected to field application electrode and source electrode of switching element, and applies a bias voltage Ve between field application electrode and source electrode. Field control unit applies an electric field from field application electrode to a hetero-junction interface of semiconductor substrate, by applying the bias voltage Ve exceeding a threshold value to switching element. In short, in the ON state of switching element, the electric field that is applied from field application electrode to semiconductor substrate works to increase electron concentration in a channel region by a field effect and decrease the ON resistance of switching element.

Abstract: A driving circuit of a schottky type transistor includes an input terminal supplied with an input signal, and an output terminal connected to a gate of the schottky type transistor. The driving circuit outputs a first voltage lower than a breakdown voltage of the schottky type transistor to the output terminal at the time of rising of the input signal, and thereafter supplies a second voltage higher than the breakdown voltage to a resistance connected to the output terminal.

Abstract: A controller for a switch and a method of operating the same. In one embodiment, the controller is configured to measure a voltage of a control terminal of the switch and select a first mode of operation if the voltage of the control terminal is greater than a threshold voltage, and a second mode of operation if the voltage of the control terminal is less than the threshold voltage.

Abstract: A power switching assembly for switching power in a power distribution bus, and a power distribution system including such a power switching assembly, are disclosed. The power switching assembly includes a first terminal, a second terminal, a first semiconductor element and a second semiconductor element electrically coupled between the first terminal and the second terminal to provide controllability of a current flow from the first terminal to the second terminal and from the second terminal to the first terminal A controller for controlling the semiconductor elements may be configured to implement one or more of various control schemes such as a breaker, a current limiter, a load balancer, and a precharging device.

Abstract: An RFID transponder in one embodiment comprises a radio frequency (RF) transceiver, processing logic coupled to the RF transceiver, a switch coupled to the processing logic, a tunneling device coupled to the switch and a differential sensing circuit having a first input coupled to the tunneling device and a second input coupled to a predetermined reference voltage. In one embodiment, the tunneling device can discharge to a voltage below the predetermined reference voltage.

Abstract: In a driver, a charging module stores negative charge on the gate of a switching element via a normal electrical path to charge the switching element upon a drive signal representing change of an on state to an off state. This shifts the on state of the switching element to the off state. An adjusting module changes a value of a parameter correlating with a charging rate of the switching element through the normal electrical path as a function of an input signal to the driver. The input signal represents a current flowing through the conductive path, a voltage across both ends of the conductive path, or a voltage at the gate. A disabling module disables the adjusting module from changing the value of the parameter if the drive signal represents the on state of the switching element.

Abstract: The invention relates to an electronic relay with an input plug-in contact (30) and at least one output plug-in contact (87, 87a) for a current to be switched, an electronic component (104) for processing data and for actuating a semiconductor switch (116) for switching the current, a wireless communications interface (106, 108) for connection to a wireless communications network (150), wherein the wireless communications interface is embodied for receiving a first switching signal (120), a control plug-in contact (15) for receiving a second switching signal (122), at least one signal input plug-in contact (W, X, Y, Z) for receiving at least a first data signal (152), wherein the electronic component is embodied such that the semiconductor switch is actuated for switching the current based upon the reception of the first or second switching signal, and such that the first data signal received via at least one signal input plug-in contact is processed and, based upon a result of the data processing of the

Abstract: A switch circuit includes: first, second, and third input-output terminals; a first switching element connected between the first and second input-output terminals; a second switching element connected between the third input-output terminal and a grounding point; a third switching element connected between the first and third input-output terminals; a fourth switching element connected between the second input-output terminal and the grounding point; a first control voltage applying terminal connected to control terminals of the first and second switching elements; a second control voltage applying terminal connected to control terminals of the third and fourth switching elements; first and second resistors connected between the control terminals of the first and second switching elements and the first control voltage applying terminal, respectively; and first and second diodes connected in parallel with the first and second resistors, respectively, and having cathodes connected to the first control voltage

Abstract: A switching circuit suitable for a low power oscillator circuit includes control and output circuits, the control circuit arranged to control the output circuit, the control circuit having input and output terminals, the output circuit having input and output terminals and control terminals; wherein the input terminal of the control circuit is connected to the input terminal of the output circuit, and the control terminal of the output circuit is connected to the output terminal of the control circuit, the output circuit first switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time, and the control circuit has second switches connected in series and arranged such that in use at least one of the switches is in a low impedance state at any given time.

Abstract: A switching circuit for connection to a load and to a voltage source is provided. The switching circuit comprises: at least one switching devices for switching on and off power to the load a pulldown device for shorting out the load thereby isolating the load from the voltage source; and a controller operable while the load is shorted to activate at least one of the switching devices at a time, wherein a current passes through the or each activated switching device and is measurable to test whether the or each activated switching device is operating correctly.

Abstract: In a method for operating a plasma installation, an induction heating installation or a laser excitation installation in a pulsed power output operation, includes controlling at least one semiconductor switching element to produce a power loss in the at least one semiconductor switching element during a pulse pause time period in a pulse pause operation during which no power suitable for the ignition or the operation of the plasma process, the induction heating process, or the laser excitation process is produced at a power output of a power generator by the at least one semiconductor switching element of the power generator, and such that a reduction of a temperature of the at least one semiconductor switching element by more than a predetermined value is prevented.

Abstract: A multiplexer circuit includes multiple groups of switches and multiple groups of control lines. Each control line in each one of the groups of control lines is coupled to a control end of at least one switch in corresponding one of the groups of switches, and each group of control lines is configured for synchronously transmitting an identical group of control signals. A display panel and method for transmitting signals in a display panel is also disclosed herein.

Abstract: A semiconductor arrangement includes a circuit carrier, bonding wire and at least N half bridge circuits. The circuit carrier includes a first metallization layer, a second metallization layer, an intermediate metallization layer arranged between the first metallization layer and the second metallization layer, a first insulation layer arranged between the intermediate metallization layer and the second metallization layer, and a second insulation layer arranged between the first metallization layer and the intermediate metallization layer. Each half bridge circuit includes a controllable first semiconductor switch and a controllable second semiconductor switch. The first semiconductor switch and the second semiconductor switch of each half bridge circuit are arranged on that side of the first metallization layer of the circuit carrier facing away from the second insulation layer. The bonding wire is directly bonded to the intermediate metallization layer of the circuit carrier at a first bonding location.

Abstract: A switching element having an electromechanical switch (such as an electrically conductive membrane switch, for example a graphene membrane switch) is disclosed herein. Such a switching element can be made and used in a switching power converter to reduce power loss and to maximize efficiency of the switching power converter.

Abstract: The present disclosure provides a power semiconductor switch series circuit. The power semiconductor switch series circuit includes a plurality of series modules and a system control module. Each series module has a power semiconductor switch; a drive module for driving each power semiconductor switch to be turned on or turned off; a short-circuit detection unit for outputting at least one detection signal; an equalizer circuit; a comparison module for comparing the detection signal with a predetermined threshold, and outputting a short-circuit signal when the detection signal exceeds the predetermined threshold; and a soft turn-off module for receiving the short-circuit signal and outputting a second control signal. The system control module receives the short-circuit signal and outputs a first control signal.

Abstract: Disclosed herein is a device that includes an input receiver circuit activated by a strobe signal to generate an output signal by comparing a potential of an input signal with a reference potential, and a noise canceller cancelling noise superimposed on the reference potential due to a change in the strobe signal.

Abstract: An RF switch circuit for switching RF signals includes a first terminal and a second terminal and a series connection of a plurality of transistors between the first terminal of the RF switch circuit and the second terminal of the RF switch circuit. Furthermore, the RF switch circuit includes a control circuit configured to conductively couple, in a high impedance state of the RF switch circuit, the first terminal of the RF switch circuit to a control terminal of a first transistor in a series of the series connection of the plurality of transistors. The second terminal of the RF switch circuit is conductively coupled to a control terminal of a last transistor in the series of the series connection of the plurality of transistors.

Abstract: A redundancy switch includes at least three data ports and a control input. Each data port includes a data input and a data output. The redundancy switch operates in one of at least three states. In a first state, a first data port is communicatively coupled with a second data port. In a second state, the first data port is communicatively coupled with a third data port. In a third state, the second data port is communicatively coupled with the third data port. The state of the redundancy switch can be controlled based on a signal received at the control input. The redundancy switch can further include transconductance switching elements that convert a voltage input to a current output.

Abstract: A ramp waveform generating apparatus generates a reference waveform by using an input signal and generates a driving control signal for turning on and off a switch having a first terminal connected to a load and a second terminal connected to a power supply by comparing the voltage of the reference waveform with the voltage of the load. While the switch is repetitively turned on and off in accordance with the driving control signal, a ramp waveform may be generated.

Abstract: A high-frequency switch module includes a multi-layer substrate, and a switch circuit mounted on the multi-layer substrate. The multi-layer substrate includes a terminal through which a plurality of high-frequency signals in a plurality of frequency bands are input and output, a plurality of switch terminals, terminals to which control signals to control the switch circuit are supplied, current paths that connect the terminals to the switch circuit, and resistors that are provided on the current paths and have resistance values greater than the resistance values of the current paths. The switch circuit connects the terminal to the switch terminals corresponding to the frequency bands of high-frequency signals input and output through the terminal based on the control signals.

Abstract: Power switching circuits and power management techniques are provided that can reduce static power of ICs, including digital core processors. In one embodiment, the power switching circuit includes a footer (power-gating transistor) between the core and a ground rail and at least two additional power-gating transistors parallel to the footer. The power-gating transistors are controlled by respective control signals to enable selective switching. In a specific embodiment, for each sleep mode, at most, a single one of the transistors is turned on. Multiple sleep modes are accomplished according to the relative sizing of the additional power-gating transistors. A larger of the additional transistors is used to provide a standby mode during short idling times by providing a fast wake-up time and some reduction in static power. For standby modes during longer idling periods, smaller sized transistors are turned on. For longest idling periods, all transistors are turned off.

Abstract: This invention relates to an inductor, more particularly, to an inductor with variable inductances.

Abstract: There are disclosed herein various implementations of nested composite switches. In one implementation, a nested composite switch includes a normally ON primary transistor coupled to a composite switch. The composite switch includes a low voltage (LV) transistor cascoded with an intermediate transistor having a breakdown voltage greater than the LV transistor and less than the normally ON primary transistor. In one implementation, the normally on primary transistor may be a group III-V transistor and the LV transistor may be an LV group IV transistor.

Abstract: An integrated circuit device comprising at least one signal processing module and a power gating control module arranged to control gating of at least one power supply to at least a part of the at least one signal processing module. The power gating control module is arranged to receive at least one operating parameter; configure at least one power gating setting of the power gating control module based at least partly on the at least one received operating parameter; and apply power gating for at least part of the at least one signal processing module in accordance with the at least one configured power gating setting.

Abstract: Disclosed herein is a resistor-sharing switching circuit, including: a first switching element turning on/off between a first input and output terminal and a second input and output terminal; a second switching element turning on/off between the first input and output terminal and a third input and output terminal; a signal transmission unit connected to both a control terminal of the first switching element and a control terminal of the second switching element; and a resistor having one end connected to the signal transmission unit and the other end connected to a control signal input terminal.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor element mounting unit, a first conductor, a semiconductor element, a first connection and a second connection. The first conductor is provided around the semiconductor element mounting unit. The semiconductor element is provided on the semiconductor element mounting unit and includes a first switch element and a second switch element provided parallel to the first switch element. The first connection and the second connection are provided on the first switch element side of an imaginary boundary line obtained by extending a boundary between the first switch element and the second switch element. The first connection and the second connection are electrically connected to the first switch element and the second switch element, respectively, and electrically connected to the first conductor.

Abstract: SOI MOSFETs are used for the transistors for switching of an antenna switch and yet harmonic distortion is significantly reduced. Capacitance elements are respectively added to either the respective drains or gates of the transistors comprising the through MOSFET group of reception branch of the antenna switch. This makes the voltage amplitude between source and gate and that between drain and gate different from each other. As a result, the voltage dependence of source-drain parasitic capacitance becomes asymmetric with respect to the polarity of voltage. This asymmetry property produces signal distortion having similar asymmetry property. Therefore, the following can be implemented by setting it so that it has the same amplitude as that of second-harmonic waves arising from the voltage dependence of substrate capacitance and a phase opposite to that of the same: second-order harmonic distortion can be canceled out and thus second-order harmonic distortion can be reduced.