Abstract: An improved digital phase detector is used in a digital phase lock loop having a digitally controlled oscillator which includes a state controller and a counter. One embodiment of the phase detector includes a digital integrator; a first register and a first absolute value function; a second register and a second absolute value function; and a subtractor. In another embodiment the integrator includes a tapped delay line and a parallel summing network. The summing network includes a flow counter. The invention to provide a mechanism for ensuring the symmetry of the integration intervals of an early/late gate phase detector in the presence of phase error and to achieve relaxed timing for the phase error calculation without shortening the integration intervals to less than half a bit time while providing a valid phase error output once for each bit period.

Abstract: A monolithic frequency converter using a feedback control loop generates a source of synthesized frequency signals over a wide dynamic range based on a timing source such as a crystal oscillator or an external frequency source. The frequency converter includes a controlled oscillator, a frequency counter, a timing signal generator and, connected between the frequency counter and the controlled oscillator, a digital to analog converter and a difference integrator. The controlled oscillator generates a clock signal at a frequency controlled by an electrical signal. The difference integrator is connected to an input signal terminal and connected to the timing signal generator. The difference integrator determines a difference signal between the input signal and a signal operated upon by the digital to analog converter and integrates the difference signal under control of a timing signal generated by the timing signal generator.

Abstract: A phase-locked loop design is provided that can operate at a plurality of dissimilar supply voltages. By adjusting the frequency range of a PLL based on the power supply voltage, the same PLL design can operate at different supply voltages.

Abstract: A digital loop filter includes a first loop filter for generating first phase control information at variable time intervals on the basis of phase error information indicating a phase difference between a first signal and a second signal. A second loop filter detects a frequency deviation between the first and second signals from the phase error information and generates second phase control information with a period inversely proportional to the frequency deviation. An adder generates finalized phase control information obtained by adding the first phase control information and the second phase control information to each other.

Abstract: A phase lock loop (PLL) circuit and method in which a PLL circuit locks on a variable input phase by providing an instantaneous phase value of a signal from an oscillator at periodic intervals, and by providing phase corrective signals to the oscillator at the same periodic intervals by comparing an instantaneous value of the variable phase to the corresponding instantaneous value of the oscillator signal phase, the phase corrective signals adjusting the phase of the oscillator signal to the predetermined phase. The PLL circuit may also lock on a predetermined frequency by providing frequency corrective signals until a difference between the predetermined frequency and the frequency of oscillator signal is smaller than a predetermined threshold.

Abstract: A phase-locked loop circuit, which is used in order to extract a clock signal out of a received signal obtained from a token ring network or various LANs, has a phase comparator, a charge pump, and a voltage controlled oscillator. Said phase comparator has a window signal generating means, an edge extracting means, and a control means. This edge extracting means finds the edge existence in a received signal during the open period of said window signal. Therefore, if the center edge of the signal has a phase jitter within the open period, the extracting means can find the center edge. When the extracting means finds no edge, said control means shifts the window position by a certain bit time, so as to restart the new extracting of center edge. Thus, this circuit can recover to the synchronous state without causing a bit slip even when a center edge is lost.

Abstract: A reference frequency divider divides a clock signal into a reference frequency signal, and outputs it. A comparison frequency divider circuit divides an output signal from a voltage controlled oscillator, and outputs it as a comparison signal. The reference signal and comparison signal are coupled to a phase comparator. The phase comparator detects the phase difference between the reference signal and comparison signal, and outputs a phase difference signal. A charge pump outputs a voltage signal in response to the phase difference signal from the phase comparator. A low pass filter smooths out the voltage signal from the charge pump to remove the high frequency components, and outputs a controlled voltage signal. A voltage controlled oscillator outputs an output signal with the frequency relating to the voltage value of the controlled voltage signal from the low pass filter. A frequency difference determining circuit compares the reference signal with the comparison signal.

Abstract: A method of estimating the quality of a communication channel from a differential phase angle between a received signal and the corresponding transmitted phase angle employs determining a signal to impairment ratio (SIR) as an indicator of channel state information (CSI). A maximum likelihood estimation procedure is employed to calculate this CSI metric as a function of the differential phase angle between the received signal and transmitted signal. An alternate embodiment employs a estimation that incorporates average SIR information for a Rayleigh fading channel. Since CSI is derived from the phase angle of the received signal, and does not require signal amplitude information, it is attractive for use with differential detectors, phase-locked loops (PLLs) and hard-limited signals. The CSI provided can be used for implementing post detection selection diversity, by selecting the signal from a plurality of antennae which has the best SIR.

Abstract: An A/D converter (1) converts analog modulation signals, such as video signals and audio signals, into digital modulation signals. A center frequency data setting circuit (6) outputs center frequency data for setting the center frequency of an FM wave. An operation unit (5) outputs such addition data, on the basis of the center frequency data and average frequency data from a counter circuit (4) as will make the average frequency of the FM wave substantially identical with the center frequency that has been set. An adder (2) adds the digital modulation signals and the addition data, and outputs addition digital signals. A DDS (3) accumulates an addition digital signal in every sampling period supplied from a reference oscillator (7). In the ROM (32) of the DDS (3) are stored sine wave data and the ROM (32), having the accumulated signals as its address input, outputs the sine wave data.

Abstract: The present invention provides a method and an apparatus for controlling initial transients in a frequency synthesizer by controlling the start-up sequence of the device. The start-up sequence comprises several steps. The voltage controlled oscillator(s) (VCO) is reset so that the VCO(s) are in a known state during start-up. The charge pump and phase detector of phase-locked loop (PLL) are disabled. New data values are loaded into counter(s)/register(s) that control the frequency of the VCO(s). Also, a data value is provided to a digital-to-analog converter (DAC) to set the data rate for the PLL. A fixed amount of time is provided as a delay for the DAC to settle (i.e., 1.6 .mu.s). Divide-by-M and divide-by-N counters are then enabled. Also, the phase detector of the phase-locked loop (PLL) is enabled. The VCO is then restarted.

Abstract: A digital frequency synthesizer circuit with spur compensation includes a demodulator circuit (118) for demodulating the output signal (116) of the synthesizer's accumulator (108). Demodulator (118) also inverts the signal, and provides an inverted demodulated output signal (142) which is then coupled to the synthesizer clock (124) after passing through a gain stage (122) in order to modulate the synthesizer clock (124) with a compensation signal (146). The compensated clock signal (140) is then sent to accumulator (108) in order to substantially cancel out any jitter in the accumulator's output signal (116). The modulation signal (MOD IN) which is digitally applied to accumulator (108) is applied in analog fashion to the gain stage (122) in order to prevent the desired modulation signal (MOD IN) from being canceled in the output signal (116).

Abstract: A phase-locked loop according to the present invention includes first and second frequency demultipliers, and a plurality of phase/frequency detectors. The first and second frequency demultipliers divide frequency of first and second signals by a predetermined number. Each of the plurality of phase/frequency detectors compares two signals supplied from the first and second frequency demultipliers. In accordance with a comparison result of the plurality of phase/frequency detectors, phase of the second signal is adjusted to be synchronized with the first signal.

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V.sub.DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

Abstract: An improved asymmetrical data tracking digital phase locked loop including separate baud rate counters for both the positive data pulse edge and the negative data pulse edge. The outputs of the two independent baud rate counters are added together and divided by two in a virtual counter for each local oscillator clock cycle. This provides a data clock pulse located at the midpoint between the corresponding data pulse edges as defined by the two baud rate counters. A digital filter is utilized to dampen the tracking loop correction to reduce maximum phase errors by not allowing continuous phase corrections.

Abstract: In a phase-locked circuit which is operable in response to an input complex signal to produce an output complex signal, a first complex multiplication is carried out between the input and the output complex signals to obtain a phase difference therebetween which appears as a complex phase difference. The complex phase difference is composed of a real part and an imaginary part which are individually allowed to pass through a low pass filter and to be supplied to a numerically controlled oscillator as a control signal. The control signal includes a frequency component even when the phase-locked circuit is put into an asynchronous state. The low pass filter may be replaced by a digital circuit comprising phase dividers.

Abstract: A microwave oscillator is shown to include an oscillator having an output and a control port and a feedback circuit disposed between the output and the control port of the oscillator. The feedback circuit includes a modulated laser, having an input and an output, the input responsive to a portion of a signal from the output of the oscillator and a photo detector having an input and an output, the input of the photo detector responsive to a signal from the output of the modulated laser delayed by a predetermined amount of time. The feedback circuit further includes a detector having a first and a second input and an output, the first input of the detector responsive to a signal from the output of the photo detector, the second input responsive to a portion of the signal from the output of the oscillator shifted in phase to be in phase quadrature with the signal at the first input of the detector and the output of the detector coupled to the control port of the oscillator.

Abstract: A phase-locking device comprises a "fast" loop providing for the correction of the transient disturbances and a "slow" loop providing for correction on a wide range of phase shifts.

Abstract: In a sync detection circuit, an input pulse signal at frequency f.sub.0 is compared with an output pulse signal from a frequency divider to produce a control signal representative of a difference in frequency or phase between the input and output pulse signals. A voltage-controlled oscillator generates pulses at a frequency f.sub.0 .times.N (where N.gtoreq.2) when the control signal indicates that the frequency or phase difference is zero or pulses at a variable frequency when the control signal indicates that the frequency or phase difference is non-zero. The frequency divider divides the frequency of the pulses from the oscillator by a factor N to generate the output pulse signal. A decision circuit is provided for detecting when the pulses generated by the oscillator during an interval between pulses of the input pulse signal are equal to at least N to give an indication that a phase alignment is established between the input and output pulse signals.

Abstract: It is an object of this invention to provide a novel network interface system which is able to connect automatically to the respective network stations having different data transfer speeds, in order to avoid the above problems. According to this invention, there is provided a detector and a selector in the communication interface to automatically select the appropriate data transfer speed. In the above structure, the speed of communication data transferred by a network is one of two detected by the detector which is able to detect a transfer speed and provide outputs at a first level signal when the transfer speed is at one level and outputs a second level signal when it is at a second level. The selecting means selects the frequency to connect a network station in response to the signal output from the detector. As a result, users need not select the module by themselves, the system automatically select the module.

Abstract: A method of adjusting the pulse rate of a local clock (1) by generating a first pulse train at a first predetermined rate, dividing the pulse train by a divisor (3) to produce a second pulse train. The value of the divisor (3) is selected (4,5,6) so that the rate of the second pulse train is adjusted within a predetermined range.

Abstract: A method and the device for voltage frequency transformation produce a fast, highly accurate voltage frequency transformer which has a wide frequency range. This method and device can be implemented with simple means. The discontinuous output signal of an integrating voltage-controlled oscillator (VCO) is transformed back into a constant voltage via a frequency divider. Then the result is compared with the input voltage (U.sub.E), and the result of the comparison is used to regulate the integrating, voltage-controlled oscillator (VCO).

Abstract: A multilayer circuit board is provided having an inner porous fluororesin layer containing electrical circuits, a ground conductor layer located adjacent the fluororesin layer on one side thereof and a power supply conductor layer located adjacent the fluororesin layer on the other side thereof, and a reinforcing, solid plastic dielectric layer adjacent each conductor layer and being external to the inner fluororesin layer. In an alternate embodiment, the multilayer circuit board may have a plurality of inner porous fluororesin layers, at least one fluororesin layer containing electrical circuits, and may have ground conductors and power supply conductors adjacent each fluororesin layer, and reinforcing, solid plastic dielectric layers on the outermost surfaces of the circuit board assembly. The ground and power supply conductor layers extend over the entire surfaces, respectively, of the inner fluororesin layers.

Abstract: An improved digital phase lock loop incorporates several distinctive features that attain better performance at high loop gain and better phase accuracy. These features include: phase feedback to a number-controlled oscillator in addition to phase rate; analytical tracking of phase (both integer and fractional cycles); an amplitude-insensitive phase extractor; a more accurate method for extracting measured phase; a method for changing loop gain during a track without loss of lock; and a method for avoiding loss of sampled data during computation delay, while maintaining excellent tracking performance. The advantages of using phase and phase-rate feedback are demonstrated by comparing performance with that of rate-only feedback. Extraction of phase by the method of modeling provides accurate phase measurements even when the number-controlled oscillator phase is discontinuously updated.

Abstract: A video dot clock generator includes a phase-locked loop (PLL) which includes a voltage controlled oscillator, a frequency divider, a phase comparator and a loop filter. The voltage controlled oscillator (VCO) is programmable to provide multiple frequency ranges for a given range of control voltages applied to the oscillator. The programming affects both the frequency range and the gain of the VCO. The phase comparator includes circuitry which simulates a predetermined minimum phase error which, when compensated for, substantially eliminates jitter in the dot clock signal. The frequency divider used in the PLL and a similar frequency divided used to generate the reference signals for the phase comparator are programmable via an internal memory which also holds programmable control signals for the VCO. The memory, in turn, may be programmed by the user to achieve desired frequency and loop again characteristics for a given application.

Abstract: An oscillator providing predictable oscillator modulation sensitivity includes an amplifier and a feedback circuit disposed about the amplifier. The feedback circuit includes a resonator having a first port and a second port and a voltage-controlled phase shifter having an input port, an output port and a control port, the input port of the voltage-controlled phase shifter connected to the output port of the amplifier and the output port of the voltage-controlled phase shifter coupled to a port of the resonator. The oscillator further includes a circuit, responsive to signals from the output of the voltage-controlled phase shifter and the first port of the resonator, to provide a control signal to the control port of the voltage-controlled phase shifter for degenerating low frequency FM noise arising within the amplifier.

Abstract: A frequency synthesizing device comprises two reference frequency generators RG1 and RG2, an offset stage OS and a phase-locked loop PLL. In the phase-locked loop, which operates as a tracking filter, the output frequency fs.sub.A is generated by the addition of the frequencies f.sub.RG1 and f.sub.OS. The output frequency fs.sub.A has a very high spectral purity, since all interfering spurious signals are blocked by the tracking filter. By a proper selection of the reference frequencies f.sub.RG1, f.sub.RG2 and f.sub.OR, it is ensured that all interfering spurious signals lie outside the bandwidth B.sub.TF of the tracking filter and are accordingly blocked. As a result, it is not necessary to filter the signals S.sub.RG1, S.sub.RG2 and S.sub.OS.

Abstract: A method for converting voltage to frequency and a device for implementing the method where an extremely rapid and highly accurate digitization of an input signal at a great freqency deviation is achieved using simple means. An input voltage which is raised into the positive range, is integrated, and as an integrated voltage is compared with a reference voltage which is variable in constant voltage steps. The resulting differential voltage acts upon a voltage controlled oscillator through a control element. The voltage controlled oscillator emits a pulse repetition frequency which is proportional to the output voltage of the controlling element. The reference voltage is incremented with each pulse so that this voltage follows the integrated voltage in a step-like manner. The pulse repetition frequency of the pulses, which are generated by the voltage controlled oscillator, is therefore proportional to the input voltage.

Abstract: There is disclosed herein a driver system for an ultrasonic probe for allowing a user to have proportional control of the power dissipated in the probe in accordance with the position of power dissipation controls operable by the user and for automatically tuning upon user request such that the driving frequency is equal to the mechanical resonant frequency of said probe and such that the reactive component of the load impedance represented by said probe is tuned out. The system uses a tunable inductor in series with the piezoelectric crystal excitation transducer in the probe which has a flux modulation coil. The bias current through this flux modulation coil is controlled by the system. It is controlled such that the inductance of the tunable inductor cancels out the capacitive reactance of the load impedance presented by the probe when the probe is being driven by a driving signal which matches the mechanical resonance frequency of the probe.

Abstract: A method and device for converting voltage to frequency performs an extremely rapid and highly accurate digitization of an analog input signal at a large frequency deviation. An input voltage, which is increased into the positive range, is integrated and compared with a reference voltage which is variable in constant steps. When the integrated voltage is greater than the reference voltage, a binary signal logic "1" is generated. If the integrated voltage is less than the reference voltage, a binary signal logic "0" is formed. When the integrated voltage is less than the reference voltage, a pulse repetition frequency is formed which is proportional to the input voltage. At each pulse, the reference voltage is incremented so that this reference voltage follows the integrated voltage in a step-like manner.

Abstract: Self-clocking system for demodulating phase encoded data automatically tracks incoming data rate changes by using information from a bit synchronizer to track the incoming base band data signal.

Abstract: A digital phase acquisition circuit includes logic for detecting an edge of incoming data and a plurality of candidate clock phases, the circuitry further including logic for determining when the data undergoes a phase transition and at least one candidate phase which undergoes a digitally equivalent transition close in time to the data transition so as to enable the candidate phase to be used for a clock for recovering information representative of the data. The circuit allows clock to be recovered within 1 bit time of a predetermined data transition occurring, thus allowing preambles of 1 bit to be utilized in data packets.

Abstract: The object of the invention is to provide an instrument for converting a physiological pulse rate into a corresponding linear output voltage.The instrument (1) which accurately measures the rate of an unknown rectangular pulse wave (9) over an extended range of values, comprises a phase-locked loop (8) including a phase comparator (4), a filtering network (6), and a voltage-controlled oscillator (5), arranged in cascade. The phase comparator has a first input (10) responsive to the pulse wave and a second input (11) responsive to the output signal of the voltage-controlled oscillator. The comparator (4) provides a signal dependent on the difference in phase and frequency between the signals appearing on the first and second inputs. A high-input impedance amplifier (16) accepts an output from the filtering network and provides an amplified output DC signal to a utilization device (16) for providing a measurement of the rate of the pulse wave.

Abstract: A recording-reproducing clock generator circuit generates a reproduced clock having a predetermined frequency from a read out signal including such pulses that the interval between two successive pulses thereof at a predetermined length is to be used as a synchronizing signal region. The circuit generates a reference clock of a predetermined frequency, generates a first sync signal detection signal when the distance between two successive pulses in the input signal measured by means of the clock pulses is equal to a predetermined reference value, separates a clock edge pulse from the input signal by using the first sync signal detection signal, and generates the reproduced clock having the predetermined frequency and synchronized with the separated clock edge pulse.

Abstract: A method and a circuit for exciting an ultrasonic generator comprises a control loop which includes the ultrasonic generator itself and a voltage-controlled oscillator. The control loop keeps the active power consumption to a desired value, which is compared in a comparator with the instantaneous active power consumption. One output of a further rectangular oscillator is connected to the control input of the voltage-controlled oscillator. The rectangular oscillator is put into operation if in the control loop there are no control oscillations or only those which are smaller than a predetermined threshold. The output of the rectangular oscillator is connected across one diode to the control input of the voltage-controlled oscillator and across another diode to the controlled input of comparator. The additional signal is applied to the voltage-controlled oscillator, apart from the control signal of the control loop.

Abstract: A constant propagation delay current reference is provided having an external source providing a reference frequency signal. A phase lock loop is provided which is responsive to the reference frequency signal and to an operating frequency signal to provide a current reference signal at the output of the loop. The current reference signal is provided to a current to frequency converter which generates the operating frequency signal. A current mirror, also coupled to the phase lock loop output provides an output current proportional to the current reference signal which is suitable for providing the injector current for I.sup.2 L devices. The output current tracks the process, voltage and temperature variations of the integrated circuit, allowing the injector currents to be optimized for maintaining constant propagation delay in the circuits being powered.

Abstract: The data link includes a phase noise compensator to eliminate phase noise resulting from microwave frequency sources on a communications satellite. In addition, Fourier analyzers are utilized to determine the frequency of received signals having low carrier-to-noise density. The combination of the phase noise compensator and the Fourier analyzers permits data rates on the order of 50 to 400 bits per second to provide economically attractive communication links with aircraft over ocean areas.

Abstract: A synchronizing pulse signal generation device separates horizontal and vertical synchronizing signals from a video signal; generates a clock signal which is phase locked relative to the phase of the horizontal synchronizing signal; and generates, by using the clock signal, a synchronizing pulse signal which is phase locked relative to the vertical and horizontal synchronizing signals.

Abstract: A transistor device for a microwave oscillating element having an FET transistor chip and a package encapsulating the chip therein. In order to avoid any affection of the external circuit to the input impedance of the transistor device and to make the phase rotation low at a frequency band higher than the X band, a conductor element is provided within the package to connect the drain electrode of the chip and a corresponding terminal of the package. The conductor element has an inductance to provide a sufficient high impedance at the intended frequency band. The conductor element is supported on an insulator plate fixedly mounted within the package.

Abstract: A device for synchronizing the output test pattern signals of a test circuit with the clock signal of a device under test (DUT). The invention uses a programmable delay in the feedback loop of a phase locked loop system to adjust the phase of the test pattern signals to be synchronized with the clock of the device under test (DUT).

Abstract: Disclosed is a latching differential phase detector for improving a slew rate and preventing false phase lock due to cycling. The system combines 2.pi. proportional phase detectors to cover a 4.pi. range. The lock monitors of the phase frequency detectors control a differential phase detector to provide positive latching.

Abstract: A magnetically tuned resonant circuit having improved noise performance includes a ferrimagnetic or gyromagnetic body such as a YIG sphere which is disposed within r.f. structure, The r.f. structure is disposed between a pair of pole pieces of a biasing magnet and flux return path. Several techniques are described for reducing fluctuations in magnetic fields through the gyromagnetic body. The gyromagnetic body is isolated from conductive surfaces, or the bulk of conductive surfaces in the region adjacent to the magnetic body are reduced. Further, a technique is also described which provides a break in the electrical continuity around the r.f. structure. Each of these technique reduce the magnitude of thermally induced eddy current flow in conductive regions adjacent to the resonant body. It is believed that such eddy current flow produce random magnetic field variations which produce random variations in the frequency characteristics of conventional magnetically tuned resonant circuits.

Abstract: A multicoin tester has a coin inlet path 1 along which coins under test run edgewise past coils 2, 3 on opposite sides of the path, and through the windings of a coil 4. Electronic circuitry responsive to the inductive coupling of the coin with the coils operates a gate 5 to either reject the coin onto path 1b or to accept the coin into path 1a. As shown in FIG. 2 each of the coils 2, 3 and 4 is arranged in a parallel L-C resonant circuit 10, 11, 12 connected in the feedback path of an amplifier A1, the resonant circuit being energised sequentially by multiplexer M1. Each of the circuits 10, 11 and 12 has its own natural resonant frequency. The resonant circuits 10, 11, 12 are driven by a voltage controlled oscillator VCO. A phase locked loop including a phase comparator PS1 drives the oscillator VCO at a frequency corresponding to the natural resonant frequency of whichever of the circuits 10, 11 and 12 is connected thereto.

Abstract: A system for stabilizing the output of a voltage-to-frequency (V/F) converter having an input terminal and an output terminal. The system comprises a single-shot having an input terminal and an output terminal. The output terminal of the V/F converter is coupled to the input terminal of the single-shot. An integrator comprising an operational amplifier is coupled in integrating amplifier configuration for coupling the output terminal of the single-shot to the input terminal of the V/F converter. The operational amplifier comprises a difference amplifier. The integrator includes a capacitor coupled between one of the input terminals of the difference amplifier and the output terminal of the difference amplifier. The output terminal of the difference amplifier is coupled to the input terminal of the V/F converter.

Abstract: An electronic device for rapidly tuning a voltage controlled oscillator to the radar carrier frequency of each of the individual radar pulses. A frequency discriminator (1) of the quadricorrelator type is supplied with the incoming pulses and with the output of the VCO (5) to provide the control voltage to the VCO (5) via amplifying stages (2), (4) and a sample-and-hold circuit (3) that maintains the tuned frequency for time durations greater than 100 usec. The operating frequency range of the device is between 6GHz-18GHz.

Abstract: A microwave frequency oscillator utilizing a push-push configuration to provide a low noise highly stable output signal at twice the frequency of a single resonator. The single resonator is connected in the feedback loop of two amplifiers. Additional circuit elements insure the proper oscillation conditions and relative phase are maintained. The use of a single resonator makes possible the application of various noise reduction techniques.

Abstract: A circuit in a synchronous detector system is provided to minimize and compensate for the errors induced by phase modulation and additive noise in the system. In one embodiment a first-order correction of such errors is achieved by equipping the synchronous detector system with a constant loop filter noise bandwidth and an RMS detector. A resolution filter passing the detected system signal to the RMS detector for correction is made to have a noise bandwidth identical to the loop filter noise bandwidth.

Abstract: In a circuit arrangement for synchronization of the phase of a frequency-divided signal with an edge of finite slope of an essentially periodic synchronizing signal with an oscillator supplying a clock signal, a frequency divider which generates the frequency-divided signal and a phase detector which comprises a first comparator for coarse phase detection, a second comparator for fine phase detection and a selector circuit which derives a resulting phase signal applied to the oscillator to control the frequency of the clock signal and originating from the first comparator in the case of large phase variations and from the second comparator in the case of small phase variations, precise adjustment to the edge is nevertheless achieved in the case of an amplitude-discrete synchronizing signal with limited time resolution because of the fact that the synchronizing signal is applied to the phase detector as a sequence of amplitude-discrete values which is formed by sampling the synchronizing signal with the clock

Abstract: A frequency modulated transmitter including a reference frequency source providing a reference frequency to a phase locked loop circuit. The phase locked loop circuit provides a frequency output signal stabilized in accordance with this reference frequency and in accordance with a feedback signal. The phase locked loop circuit further includes a data input circuit that adjusts the output frequency in accordance with input data. Also included is the feedback circuit that provides the feedback signal to the phase locked loop circuit. This feedback circuit is derived from the frequency output signal. A synchronization circuit is connected to the feed back circuit and synchronizes the output of the feedback circuit with the reference frequency signal and the input data.

Abstract: An automatic clock recovery circuit is described. The automatic clock recovery circuit samples a received data signal with a recovered clock signal and advances or retards the recovered clock signal based on the comparison between the received data signal and the recovered clock signal. The automatic clock recovery circuit selectively cancels advance or retard corrections in the presence of bias distortion and phase ambiguities to improve the lock acquisition time for recovered clock.

Abstract: The IC chip consists of electronic circuits wherein voltage control oscillator whose oscillation frequency is dependent on the product of the resistance value of a resistor element and the electrostatic capacity of a capacitor element is provided; said capacitor element consists of the first variable capacitor; said voltage control oscillator comprises said capacitor consisting of said first variable capacitor; said first variable capacitor is controlled by the output obtained by detecting the output signal of said voltage control oscillator by its phase, using the predetermined reference signal, whereby the oscillation frequency of said voltage control oscillator can be made to agree with the frequency of said reference signal.