Abstract: A first internal electrode includes a first lead portion and a second lead portion. A second internal electrode includes a third lead portion and a fourth lead portion. A third internal electrode includes a main electrode portion and a fifth lead portion. A fourth internal electrode includes a main electrode portion and a sixth lead portion. A joint portion between the main electrode portion and the fifth lead portion of the third internal electrode is located between an edge on the first side face side and an edge on the second side face side in a capacitance forming region when viewed from an opposing direction of the third and fourth side faces. A joint portion between the main electrode portion and the sixth lead portion of the fourth internal electrode is located between an edge on the first side face side and an edge on the second side face side in a capacitance forming region when viewed from the opposing direction of the third and fourth side faces.

Abstract: A method for manufacturing a multilayer chip capacitor includes: forming screen patterns on mother green sheets such that a widthwise margin is not formed on the mother green sheets, the screen patterns are spaced apart from each other in the width direction and the longitudinal direction, and a width of each screen pattern is greater than a spacing between the adjacent screen patterns; forming internal electrode patterns on the mother green sheets; forming a stack of the mother green sheets; forming a capacitor body having internal electrodes by cutting the stack of the mother green sheets along cutting lines arranged in the width direction and the longitudinal direction; forming chip-protecting side members on both sides of the capacitor body such that the chip-protecting side members contact both sides of the internal electrodes, respectively; and forming a pair of terminal electrodes on the outer surface of the capacitor body.

Abstract: A capacitor insulating film is composed of a ferroelectric film formed on a substrate and containing an element functioning as a crystal nucleus which allows the growth of a crystal in a random crystal orientation.

Abstract: A multi-segment parallel wire capacitor includes substantially identical multiple capacitor segments fabricated on a semiconductor substrate. Each segment comprises at least first and second interleaved metal finger formed in a first metal layer above the substrate and third and fourth interleaved metal fingers formed in a second metal layer. The first and fourth sets are connected together to form one plate of the capacitor and the second and third sets are connected to form a second plate. The multiple capacitor segments are arranged in a matrix having M rows and N columns. The multiple capacitor segments are inter-connected in such a manner that the capacitor segments in each column of the matrix are connected in parallel. First and second metal lines selectively connect the plates of the different capacitor segments in the first and last rows and serve as the two opposite terminals of the multi-segment parallel wire capacitor.

Abstract: A thin film capacitor is disposed over a semiconductor substrate. The thin film capacitor includes a lower electrode at least an upper surface of which is made of amorphous or microcrystalline metal, a dielectric film disposed over the lower electrode, and an upper electrode disposed over the dielectric film.

Abstract: A first electrode film containing TiAlN and a main dielectric film containing tantalum oxide are formed over a semiconductor substrate. Anneal is performed in the state that the first electrode film and the main dielectric film are formed, to react aluminum (Al) in the first electrode film with oxygen (O) in the main dielectric film and form a subsidiary dielectric film containing aluminum oxide at an interface between the first electrode film and the main dielectric film. A second electrode film is formed facing the first electrode film via the main dielectric film and the subsidiary dielectric film.

Abstract: A method for manufacturing a capacitor, includes: accelerating conductor particles by ejecting the conductor particles together with gas, each surface of the conductor particles covered with a dielectric entirely; fixing the conductor particles to a substrate with the surface of the conductor particles still covered with the dielectric entirely by colliding the conductor particles with the substrate; and sandwiching a deposited film formed of the conductor particles fixed to the substrate between electrodes.

Abstract: A thin-film capacitor assembly includes two plates that are accessed through deep and shallow vias. The thin-film capacitor assembly is able to be coupled with a spacer and an interposer. The thin-film capacitor assembly is also able to be stacked with a plurality of thin-film capacitor assemblies. The thin-film capacitor assembly is also part of computing system.

Abstract: A multilayer capacitor array comprises a capacitor body having rectangular first and second main faces opposing each other. In the capacitor body having a dielectric characteristic, a first electrode group including first and second inner electrodes and a second electrode group including third and fourth inner electrodes are arranged in a row. The first and third inner electrodes are arranged in contact with a reference plane parallel to the opposing direction of the first and second main faces between the first electrode group and second electrode group. The second and fourth inner electrodes are arranged such as to be separated from the reference plane by a predetermined distance.

Abstract: Provided is a multilayer chip capacitor including a capacitor body having first and second capacitor units arranged in a lamination direction; and a plurality of external electrodes formed outside the capacitor body. The first capacitor unit includes at least one pair of first and second internal electrodes disposed alternately in an inner part of the capacitor body, the second capacitor unit includes a plurality of third and fourth internal electrodes disposed alternately in an inner part of the capacitor body, and the first to fourth internal electrodes are coupled to the first to fourth external electrodes. The first capacitor unit has a lower equivalent series inductance (ESL) than the second capacitor unit, and the first capacitor unit has a higher equivalent series resistance (ESR) than the second capacitor unit.

Abstract: A capacitor formed in an insulating porous material.

Abstract: A capacitor structure includes: a first metal layer including: a first frame structure including a first main frame and at least a first frame strip coupled to the first main frame for separating the first main frame to a plurality of first frame sections; and a plurality of first strips, each of the plurality of first strips positioned and isolated in one of the plurality of first frame sections; a second metal layer including: a second frame structure including a second main frame and at least a second frame strip coupled to the second main frame for separating the second main frame to a plurality of second frame sections; and a plurality of second strips, each of the plurality of second strips positioned and isolated in one of the plurality of second frame sections; and a dielectric layer, formed between the first metal layer and the second metal layer.

Abstract: A dielectric ceramic is provided having a high relative dielectric constant, and in the case in which it is used for a multilayer ceramic capacitor, high insulating properties and superior reliability can be obtained even when the thickness of a dielectric ceramic layer is decreased. The dielectric ceramic used for forming the dielectric ceramic layer of a multilayer ceramic capacitor has a composition represented by 100 (Ba1?w?x?mCawSrxGdm)k(Ti1?y?z?nZryHfzMgn)O3+a+pMnO2+qSiO2+rCuO, in which 0.995?k?1.010, 0?w<0.04, 0?x?0.04, 0?y?0.10, 0?z?0.05, 0.015?m?0.035, 0.015?n?0.035, 0.01?p?1.0, 0.5?q?2.5, and 0.01?r?5.0. In addition, a is a value selected with respect to the deviation from 3 so that the primary component is electrically neutral.

Abstract: A metal capacitor in which an electric conductivity is significantly improved by applying a metal material for an electrolyte and a manufacturing method thereof is provided.

Abstract: Copper metal powders, methods for producing copper metal powders and products incorporating the powders. The copper metal powders have a small particle size, narrow size distribution and a spherical morphology. The method includes forming the metal particles in a continuous manner.

Abstract: A method of manufacturing a sensor for in vivo applications includes the steps of providing two wafers of an electrically insulating material. A recess is formed in the first wafer, and a capacitor plate is formed in the recess of the first wafer. A second capacitor plate is formed in a corresponding region of the second wafer, and the two wafers are affixed to one another such that the first and second capacitor plates are arranged in parallel, spaced-apart relation.

Abstract: In a device including multiple metal-insulator-metal (MIM) capacitors and a method of fabricating the same, the multiple MIM capacitors comprise a lower interconnect in a substrate; a first dielectric layer on the lower interconnect; a first intermediate electrode pattern on the first dielectric layer overlapping with the lower interconnect; a second intermediate electrode pattern on the first dielectric layer and spaced apart from the first intermediate electrode pattern in a same plane of the device as the first intermediate electrode pattern; a second dielectric pattern on the second intermediate electrode pattern; and an upper electrode pattern on the second dielectric pattern.

Abstract: The present invention relates to methods of forming multilayer structures and the structures themselves. In one embodiment, a method of forming a multilayer structure comprises: providing a dielectric composition comprising paraelectric filler and polymer wherein the paraelectric filler has a dielectric constant between 50 and 150; applying the dielectric composition to a carrier film thus forming a multilayer film comprising a dielectric layer and carrier film layer; laminating the multilayer film to a circuitized core wherein the dielectric layer of the multilayer film is facing the circuitized core; and removing the carrier film layer from the dielectric layer prior to processing; applying a metallic layer to the dielectric layer wherein the circuitized core, dielectric layer and metallic layer form a planar capacitor; and processing the planar capacitor to form a multilayer structure.

Abstract: a composite dielectric thin film capable of high dielectric constant, low leakage current characteristics, and high dielectric breakdown voltage while being deposited at a room temperature, a capacitor and a field effect transistor (FET) using the same, and their fabrication methods. The composite dielectric thin film is deposited at a room temperature or less than 200° C. and comprises crystalline or amorphous insulating filler uniformly distributed within an amorphous dielectric matrix or within an amorphous and partially nanocrystalline dielectric matrix.

Abstract: Embodiments are described in which a stacked arrangement of integrated circuit packages comprises a dummy substrate comprising an embedded discrete or distributed capacitor connected to first and/or second power voltages, or an embedded termination register connected to one or more clock, control, address, and/or data signals(s).

Abstract: A capacitor includes a lower electrode, a dielectric structure over the lower electrode, the dielectric structure including at least one crystallized zirconium oxide (ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer, and an upper electrode formed over the dielectric structure. A method for fabricating a capacitor includes forming a lower electrode over a certain structure, forming a dielectric structure including at least one crystallized zirconium oxide (ZrO2) layer and at least one amorphous aluminum oxide (Al2O3) layer over the lower electrode, and forming an upper electrode over the dielectric structure.

Abstract: Electrical components for microelectronic devices and methods for forming electrical components. One particular embodiment of such a method comprises depositing an underlying layer onto a workpiece, and forming a conductive layer on the underlying layer. The method can continue by disposing a dielectric layer on the conductive layer. The underlying layer is a material that causes the dielectric layer to have a higher dielectric constant than without the underlying layer being present under the conductive layer. For example, the underlying layer can impart a structure or another property to the film stack that causes an otherwise amorphous dielectric layer to crystallize without having to undergo a separate high temperature annealing process after disposing the dielectric layer onto the conductive layer. Several examples of this method are expected to be very useful for forming dielectric layers with high dielectric constants because they avoid using a separate high temperature annealing process.

Abstract: A monolithic ceramic electronic component includes a ceramic laminate provided with ceramic layers and internal electrode layers disposed between the ceramic layers such that a portion of each internal electrode is led to an end surface of the ceramic laminate and the external electrode disposed on the end surface of the ceramic laminate to which the internal electrode layers are led, so as to connect to the internal electrode layers. At least one end portion in a longitudinal direction of an exposed portion of the internal electrode layer led to and exposed at the end surface of the ceramic laminate is covered with a glass film, and the internal electrodes and the external electrode are electrically connected to each other at a portion not covered with the glass film in the exposed portion of the internal electrode layer.

Abstract: An integrated circuit device includes a capacitor array, which includes unit capacitors arranged in rows and columns, wherein each unit capacitor is formed of two electrically insulated capacitor plates. The unit capacitors include at least one first unit capacitor in each row and in each column of the capacitor array; the at least one first unit capacitor being interconnected, wherein each row of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have, and wherein each column of the capacitor array comprises a same number of the at least one first unit capacitors as other rows and columns have. The unit capacitors further include at least one second unit capacitor in each row and in each column of the capacitor array, wherein the at least one second unit is interconnected and evenly distributed throughout the array.

Abstract: A metal-insulator-metal (MIM) capacitor that includes a silicon nitride (SiN) dielectric film is disclosed. The MIM capacitor includes a bottom electrode, a top electrode and a dielectric layer positioned between the bottom electrode and the top electrode. The dielectric layer includes a silicon nitride film that has a plurality of silicon-hydrogen bonds and a plurality of nitride-hydrogen bonds. A ratio of silicon-hydrogen bonds to nitride-hydrogen bonds is equal to or smaller than 0.5. Accordingly, the nitrogen-rich and compressive silicon nitride film can improve the breakdown voltage of the MIM capacitor.

Abstract: Methods for forming ruthenium films and semiconductor devices such as capacitors that include the films are provided.

Abstract: Disclosed are a capacitor of a semiconductor device and a method of fabricating the same. The capacitor includes a capacitor top electrode, a capacitor bottom electrode aligned with a bottom surface and three lateral sides of the capacitor top electrode, and a capacitor insulating layer between the capacitor top electrode and the capacitor bottom electrode.

Abstract: A design structure for a metal-insulator-metal (MIM) capacitor using a via as a top plate and method for forming is described. In one embodiment, the MIM capacitor structure comprises a bottom plate and a capacitor dielectric layer formed on the bottom plate and at least one via formed on the capacitor dielectric layer. The at least one via provides a top plate of the MIM capacitor.

Abstract: Provided are palladium-containing powders and a method and apparatus for manufacturing the palladium-containing particles of high quality, of a small size and narrow size distribution. An aerosol is generated from liquid feed and sent to a furnace, where liquid in droplets in the aerosol is vaporized to permit formation of the desired particles, which are then collected in a particle collector. The aerosol generation involves preparation of a high quality aerosol, with a narrow droplet size distribution, with close control over droplet size and with a high droplet loading suitable for commercial applications. Powders may have high resistance to oxidation of palladium. Multi-phase particles are provided including a palladium-containing metallic phase and a second phase that is dielectric. Electronic components are provided manufacturable using the powders.

Abstract: An object of the present invention is to restrain warpage in a thin-film trench capacitor. A thin-film capacitor includes a substrate, a dielectric film, and a pair of electrodes, and the dielectric film is provided along a concave-convex surface on which are formed a plurality of convex portions extending away from the substrate. The concave-convex surface forms a pattern having one or more divisions arranged in a plane parallel to the main plane of the substrate, and the convex portions are arranged in either parts of the divisions or other parts. At least some of the divisions have parts extending along the x axial direction, and two or more of the extending parts overlap each other and terminate at locations that are different from each other, as viewed from the y axial direction orthogonal to the x axial direction.

Abstract: A dielectric ceramic including a perovskite compound represented by the general formula {(Ba1-x-yCaxSny)m(Ti1-zZrz)O3} as a primary component in which the x, y, z, and m satisfy 0.02?x?0.20, 0.02?y?0.20, 0?z?0.05, and 0.99?m?1.1 and is processed by a thermal treatment at a low oxygen partial pressure of 1.0×10?10 to 1.0×10?12 MPa. Accordingly, there are provided a dielectric ceramic which can be stably used in a high-temperature atmosphere without degrading dielectric properties, properties of which can be easily adjusted, and which generates no electrode breakage even when ceramic layers and conductive films are co-fired, and a ceramic electronic element, such as a multilayer ceramic capacitor, which uses the above dielectric ceramic.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film.

Abstract: A method of producing an array type multi-layer ceramic capacitor is disclosed, comprising: forming dielectric films, forming dielectric sheets on which internal electrodes and interelectrode dielectrics formed on the same plane as the internal electrodes are printed simultaneously by spraying ink intended for internal electrodes and ink intended for dielectrics onto the dielectric film via a plurality of inkjet printer heads, stacking and compressing the dielectric sheets, cutting the stacked dielectric sheet to include a plurality of internal electrodes on the same plane as the dielectric sheet, and sintering the cut dielectric sheets. The array type multi-layer ceramic capacitor according to the invention can solve the problem of interlayer gaps by printing the dielectrics and internal electrodes simultaneously, and can solve the contact problem by printing the internal electrode and the external electrode as a single body.

Abstract: The present invention relates to a multi-layer ceramic capacitor printed simultaneously with internal electrode and external electrode by employing an inkjet printing. A method for manufacturing the multi-layer ceramic capacitor comprising first external electrode, dielectric, internal electrode and second external electrode prints simultaneously the first external electrode; the internal electrode which is connected with the first external electrode and formed at an invaginated portion of the dielectric invaginated to allow one side to be opened at one portion; and the second external electrode which is formed integrally with the internal electrode by employing an inkjet printing. According to the present invention, a method for manufacturing the multi-layer ceramic capacitor resolves contact problems by printing integrally the internal electrode and the external electrode and reduces the manufacturing process.

Abstract: A method of fabricating an electronic device includes selectively forming a glass layer on a ceramic substrate by printing, baking the glass layer, and forming a capacitor on the glass layer, the capacitor including metal electrodes and a dielectric layer interposed between the metal electrodes.

Abstract: A communications device (125) and capacitor assembly (100) having a first capacitor electrode formed by a conductive keypad mount (110) coupled to a conductive part of a housing (120) of the communications device (125). The keypad mount (110) has keypad apertures (210) aligned with keys (140) of a keypad (145) and the conductive part of the housing (120) has an external housing covering insulator in the form of the window sub-housing (121). There is a circuit board (130) providing support for a second capacitor electrode (150). The circuit board (130) has an array of keypad actuators (135) aligned with the keys (140).

Abstract: A charge storage cell is made up of two electrodes spaced apart by a dielectric layer incorporating a molecular switch. A method of operating a bi-stable, molecular switch charge storage cell encompassing two electrodes spaced apart by a dielectric layer incorporating a molecular switch having an electric dipole is also disclosed. The method involves applying a voltage across said dielectric layer to induce opposing charges on said electrodes that create an electric field across said dielectric layer, wherein molecular dipoles within said dielectric layer align or change in response to said electric field, creating an opposing electric field and a change in state of said molecular switch from a first state to a second state; and applying a voltage of reverse polarity across said dielectric aver to change said state of said molecular switch from said second state to said first state.

Abstract: A thin film capacitor element composition having a bismuth layered compound with a c-axis oriented substantially vertical to the substrate surface, wherein the bismuth layered compound is expressed by the formula (Bi2O2)2+(Am?1BmO3m+1)2? or Bi2Am?1BmO3M+3, the symbol m in the formula is an odd number, at least part of the Bi and/or A of the bismuth layered compound is substituted by a rare earth element, and the number of moles substituted by the rare earth element is larger than 1.0 and 2.8 or less with respect to the number of moles (m+1) of the total of Bi and A.

Abstract: A via array capacitor including a capacitor body having a first main surface and a second main surface and having a structure in which dielectric layers and inner electrode layers are alternately laminated; a plurality of via conductors which conduct the inner electrode layers to each other and are, as a whole, arranged in array form; and metal-containing layers which are disposed on at least one of the first main surface and the second main surface, wherein a total volume of the inner electrode layers and the metal-containing layers included in the via array capacitor is from 45 vol.% to 95 vol.% of a volume of the via array capacitor.

Abstract: A method of making capacitor structure includes arranging first-layer conducting strips on a first layer of an integrated circuit chip, and arranging second-layer conducting strips on a second layer of the integrated circuit chip. The first-layer conducting strips and the second-layer conducting strips can be arranged as respective piecewise spirals. The second-layer conducting strips are arranged overlying and electrically separated from the first-layer conducting strips, and the method further includes electrically connecting the first-layer conducting strips with the second-layer conducting strips.

Abstract: The invention aims at providing a dielectric ceramic composition including BamTiO2+m where “m” satisfies 0.99?m?1.01 and BanZrO2+n where “n” satisfies 0.99?n?1.01, an oxide of Mg, an oxide of R where R is at least one selected from Sc, Y, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu, an oxide of at least one element selected from Mn, Cr, Co and Fe, and an oxide of at least one element selected from Si, Li, Al, Ge and B. 35 to 65 moles of BanZrO2+n, 4 to 12 moles of an oxide of Mg, 4 to 15 moles of an oxide of R, 0.5 to 3 moles of an oxide of Mn, Cr, Co and Fe, and 3 to 9 moles of an oxide of Si, Li, Al, Ge and B are included therein per 100 moles of the BamTiO2+m.

Abstract: A method of forming a window via capacitor comprises a first step of providing a plurality of interleaved dielectric layers and paired electrode layers to create a multilayered arrangement characterized by top and bottom surfaces and a plurality pf side surfaces. First and second transition layer electrode portions are provided on a top surface of the multilayered arrangement on top of which a cover layer formed to define openings, or windows, therein is provided. The cover layer may be provided before device firing or may be printed on after firing using polymer or glass. Peripheral terminations are subsequently formed on the device periphery to connect selected electrode layers to respective transition layer electrode portions. Via terminations are formed in the cover layer openings, on top of which solder balls may be applied. Some of the terminations may be formed in accordance with various plating techniques as disclosed.

Abstract: Quantum Batteries (super capacitors) which by a new quantum effect “virtual photon resonance” can store electrical energy as a pure electrical battery in ranges up to 15 MJ/kg and more. The battery is basically a capacitor composed of insulating matrix material with either dispersed nanocrystal particles of Rutile TiO2 or alternating layers of Rutile crystal TiO2 deposited by Vapor Deposition Process. After reaching the resonance conditions (electrostatic field has suitable 1) strength and 2) energy content) the capacitor becomes a constant voltage battery and takes up additional energy by Dirac current pulses at very fast rates. Thereby the Rutile crystal (semiconductor) changes its state from an insulator to becoming conductive. The battery can be built flat or wound. Voltage from a few to kVolts and top capacities are only limited to mechanical constraints. Due to the nearly zero source resistance the battery loads and discharges at constant voltage and at extremely high rates.

Abstract: A dielectric ceramic composition for low-temperature sintering and hot insulation resistance (hot IR) is capable of carrying out low-temperature sintering, improving a hot IR characteristic, and meeting X5R characteristics, and a multilayer ceramic capacitor makes use of the dielectric ceramic composition. The dielectric ceramic composition includes a main component BaTiO3, and sub-components, based on 100 moles of the main component, MgO of 0.5 moles to 2.0 moles, Re2O3 of 0.3 moles to 2.0 moles, MnO of 0.05 moles to 0.5 moles, V2O5 of 0.01 moles to 0.5 moles, BaO of 0.3 moles to 2.0 moles, SiO2 of 0.1 moles to 2.0 moles, and borosilicate glass of 0.5 moles to 3.0 moles, where Re includes at least one selected from the group consisting of Y, Ho and Dy.

Abstract: This electronic component comprises a substrate; and a capacitor part provided on the substrate, the capacitor part includes a first electrode part provided on the substrate; a dielectric film covering the first electrode part; an insulating film that contacts the dielectric film and has an opening part; and a second electrode part that contacts an inner wall surface of the opening part of the insulating film and a surface of the dielectric film, and when the angle between a first interface between the dielectric film and the insulating film, and a second interface between the insulating film and the second electrode part is ?, ? is not more than 22°.

Abstract: A method for forming a variable capacitor including a conductive strip covering the inside of a cavity, and a flexible conductive membrane placed above the cavity, the cavity being formed according to the steps of: forming a recess in the substrate; placing a malleable material in the recess; having a stamp bear against the substrate at the level of the recess to give the upper part of the malleable material a desired shape; hardening the malleable material; and removing the stamp.

Abstract: Disclosed herein is a polymer-ceramic dielectric composition. The dielectric composition comprises a polymer and a ceramic dispersed in the polymer wherein the ceramic is composed of a material having a perovskite structure represented by ABO3 and a metal oxide dopant and has an electrically charged surface. According to the dielectric composition, the surface of the ceramic is electrically charged to induce space-charge polarization (or interfacial polarization) at the polymer/ceramic interface, resulting in an increase in dielectric constant. Since the dielectric composition has a high dielectric constant particularly in a low-frequency range, it can be suitably used to produce decoupling capacitors.

Abstract: A face-centered cubic structure capacitor is provided, which includes a first metal layer, a second metal layer, and a connection layer. The first metal layer comprises a plurality of first metal wires, a plurality of second metal wires, and a plurality of first metal blocks. The first and second metal wires are intercrossed with each other to form a grid structure, and each of the first metal blocks is disposed in each grid of the grid structure. The second metal layer comprises a plurality of third metal wires, a plurality of fourth metal wires, and a plurality of second metal blocks. The third and fourth metal wires are intercrossed with each other to form a grid structure, and each of the second metal blocks is disposed in each grid of the grid structure. The connection layer comprises a plurality of third metal blocks and a plurality of fourth metal blocks.

Abstract: A thin film capacitor with high capacity and low leak current is provided. The thin film capacitor includes a nickel substrate with nickel (Ni) purity of 99.99 weight percent or above, and a dielectric layer and an electrode layer disposed in this order on the nickel substrate. The thin film capacitor is typically manufactured as follows. A precursor dielectric layer is formed on a nickel substrate with nickel purity of 99.99 weight percent or above, and is subjected to annealing to form a dielectric layer. The diffusion of impurities from the nickel substrate to the precursor dielectric layer during annealing is suppressed.

Abstract: The present invention relates to a method for producing a coating of a porous, electrically conductive substrate material with a dielectric by using a solution of precursor compounds of the dielectric with a concentration of less than 10 wt. %, expressed in terms of the contribution of the dielectric to the total weight of the solution, and to the production of capacitors using this method.