Abstract: A method for forming a capacitor includes providing a metal-containing bottom electrode, forming a capacitor insulator over the metal-containing bottom electrode, forming a metal-containing top electrode over the capacitor insulator, and forming a dielectric-containing field modification layer over the capacitor insulator and at least partially surrounding the metal-containing top electrode. Forming the dielectric-containing field modification layer may include oxidizing a sidewall of the metal-containing field modification layer. A barrier layer may be formed over the capacitor insulator prior to forming the metal-containing top electrode.

Abstract: A multilayer ceramic capacitor having external electrodes. Each of the external electrodes has a lower layer resistance electrode and an upper layer conductive electrode. A glass contained in the upper layer conductive electrode has a softening point higher than that of a glass contained in the lower layer resistance electrode by 20° C. or more.

Abstract: A dielectric ceramic is provided which is can be stably used for a multilayer ceramic capacitor even at a high temperature of approximately 175° C. The dielectric ceramic includes a perovskite type compound represented by the composition formula (Ba1-x-yCaxSny)m(Ti1-zZrz)O3 (where x, y, z, and m satisfy 0?x?0.20, 0.02?y?0.20, 0?z?0.05, and 0.990?m?1.015, respectively) as a primary component; and RE as an accessory component (where RE is at least one selected from the group consisting of Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu), wherein 0.5 to 20 molar parts of RE is contained with respect to 100 molar parts of the primary component.

Abstract: A ceramic electronic component includes a ceramic body and an internal electrode layers disposed within the ceramic body. The ceramic body is covered with a diffusion layer, wherein said diffusion layer is an oxide layer into which at least a part of elements contained in the ceramic body are diffused and is located closer to a surface of the ceramic body than an outermost internal electrode layer.

Abstract: Disclosed is a polymeric surfactant for high dielectric polymer composites, a method of preparing the same, and a high dielectric polymer composite including the same. The polymeric surfactant for high dielectric polymer composites, which includes a head portion having high affinity for a conductive material and a tail portion having high affinity for a polymer resin, forms a passivation layer surrounding the conductive material in the high dielectric polymer composite including the polymeric surfactant, thus ensuring and controlling a high dielectric constant.

Abstract: The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via.

Abstract: A dielectric film capacitor includes a lower electrode having an opening and formed of a material including platinum, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film. The planar area of the lower electrode is 50% or more of the area of a formation region of the dielectric film. A dielectric film capacitor includes a lower electrode formed of a material including platinum and having a thickness of 10 to 100 nm, a dielectric film provided over the lower electrode and including an oxide having an ABOx crystal structure, and an upper electrode provided over the dielectric film.

Abstract: There is provided a dielectric ceramic composition that is a dielectric ceramic material used for a laminated ceramic capacitor; that can be co-fired with internal electrodes mainly composed of Ni at a temperature of 1300° C. or less; and that has a high dielectric constant, good temperature characteristics of capacitance in a range of ?55 to 175° C., and a high resistivity ? at 175° C. The dielectric ceramic composition includes a main component represented by a composition formula (1-a) (K1-xNax)(Sr1-y-zBayCaz)2Nb5O15-a(Ba1-bCab)TiO3 (where a, b, x, y, and z are all molar amounts and 0.3?a?0.8, 0?b?0.2, 0?x<0.2, 0.1?y?0.5, 0.1?z?0.5, and 0.2?y+z?0.7); and M, as an additional component, in an amount of 0.1 to 40 parts by mole relative to 100 parts by mole of the main component (where M is at least one element from the group of V, Mn, Cr, Fe, Co, Ni, Zn, Mg, and Si).

Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

Abstract: Provided are a tunable inter-digital capacitor (IDC) and a method of manufacturing the same. The tunable IDC includes: a first dielectric layer formed on a substrate and having electrode pattern grooves of an IDC including a ground line and a signal line formed therein; electrode metal patterns formed in the electrode pattern grooves of the IDC including the ground line and the signal line formed in the first dielectric layer; and a second dielectric layer formed on an upper surface of the first dielectric layer to cover all of the electrode metal patterns except for parts of the ground and signal lines. Therefore, it is possible to increase tunability of the IDC and reduce drive voltage.

Abstract: A method for forming a capacitor dielectric includes depositing a zirconium oxide layer, performing a post-treatment on the zirconium oxide layer such that the zirconium oxide layer has a tetragonal phase, and depositing a tantalum oxide layer over the zirconium oxide layer such that the tantalum oxide layer has a tetragonal phase.

Abstract: A capacitor structure includes: a first electrode configured to include a plurality of openings; a second electrode formed in each center of the openings; and a dielectric layer formed to surround the second electrode and fill the openings of the first electrode.

Abstract: A method including forming a ceramic material directly on a sheet of a first conductive material; forming a second conductive material on the ceramic material; and sintering the ceramic material. A method including forming a ceramic material directly on a sheet of a first conductive material; forming a second conductive material on the ceramic material so that the ceramic material is disposed between the first conductive material and the second conductive material; thermal processing at a temperature sufficient to sinter the ceramic material and form a film of the second conductive material; and coating an exposed surface of at least one of the first conduct material and the second conductive material with a different conductive material. An apparatus including first and second electrodes; and a ceramic material between the first electrode and the second electrode, wherein the ceramic material is sintered directly on one of the first and second electrode.

Abstract: A multilayer chip capacitor including: a capacitor body having a plurality of dielectric layers deposited therein and having a parallelepiped shape; at least three pairs of first and second external electrodes formed on two longer sides, the first and second external electrodes in each of the pairs having different polarities and opposing each other, and the first and second external electrodes on each of the longer sides arranged alternately with each other; and a plurality of first and second internal electrodes arranged alternately to interpose each of the dielectric layers, the first and second internal electrodes connected to the first and second external electrodes by leads, respectively, wherein the capacitor body has a length that is 2.5 times greater than a width thereof.

Abstract: Nanocrystalline forms of metal oxides, including binary metal oxide, perovskite type metal oxides, and complex metal oxides, including doped metal oxides, are provided. Methods of preparation of the nanocrystals are also provided. The nanocrystals, including uncapped and uncoated metal oxide nanocrystals, can be dispersed in a liquid to provide dispersions that are stable and do not precipitate over a period of time ranging from hours to months. Methods of preparation of the dispersions, and methods of use of the dispersions in forming films, are likewise provided. The films can include an organic, inorganic, or mixed organic/inorganic matrix. The films can be substantially free of all organic materials. The films can be used as coatings, or can be used as dielectric layers in a variety of electronics applications, for example as a dielectric material for an ultracapacitor, which can include a mesoporous material. Or the films can be used as a high-K dielectric in organic field-effect transistors.

Abstract: A method of manufacturing a capacitor device of the present invention, includes the steps of, forming an insulating layer on a substrate, forming a recess portion in the insulating layer by an imprinting process, forming a lower electrode by filling a metal layer in the recess portion in the insulating layer, forming a photosensitive dielectric layer on the lower electrode, forming an upper electrode on the dielectric layer, and forming a dielectric layer pattern under the upper electrode by exposing/developing the dielectric layer while using the upper electrode as a mask.

Abstract: A rolled film capacitor is disclosed which includes a first dielectric film and a second dielectric film, which are wound along their length dimension to form alternating turns of the winding. A plurality of first conductive segments are arranged on a first surface of the first dielectric film along the length dimension of the first dielectric film, and a plurality of second conductive segments are arranged on a surface of the second dielectric film along the length dimension of the second dielectric film, or on a second surface of the first dielectric film along the length dimension of the first dielectric film. The first conductive segments can have a progressively increasing length along the length dimension of the first dielectric film, and the second conductive segments have a progressively increasing length along the length dimension of the first or second dielectric film. The number of the first and/or second conductive segments per turn of the winding can be equal to or more than one.

Abstract: A method for manufacturing a laminated electronic component is performed such that a water-repellent agent is applied to end surfaces at which ends of internal electrodes are exposed so as to be filled in spaces along interfaces between insulating layers and the internal electrodes. Subsequently, an abrading step is performed such that the internal electrodes are sufficiently exposed at the end surfaces and an excess water-repellent agent is removed therefrom to enable plating films to be directly formed on the end surfaces.

Abstract: A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.

Abstract: The “squeal” that occurs when an electric field is applied to a multilayer ceramic capacitor mounted on a substrate is suppressed by providing in an active part contributing to formation of capacitances between internal electrodes facing each other in a capacitor body, low-activity regions positioned near respective end edges of respective external electrodes. A facing area of the internal electrodes in the low-activity regions is less than or equal to one fifth that of the internal electrodes in a normal region having the same volume as that of the low-activity regions. This makes it possible to suppress occurrence of electric-field-induced distortion near the external electrodes bonded to a substrate and reduce the force that causes the substrate to bend.

Abstract: A multilayer capacitor includes a capacitor body in which internal electrodes in a first internal electrode group are overlapped with internal electrodes in a second internal electrode group with dielectric layers sandwiched therebetween. A first external electrode has a first wraparound portion and a second wraparound portion, and a second external electrode has a third wraparound portion and a fourth wraparound portion. The volume proportions of the effective layers in a first area sandwiched between the first wraparound portion and the second wraparound portion and in a third area sandwiched between the third wraparound portion and the fourth wraparound portion are set to at least about 10%. The volume proportions of the effective layers in a second area toward a lower surface in the first area and in a fourth area toward the lower surface in the third area are set to about 15% or less. The external dimensions of the multilayer capacitor 1 are about 1.6±0.1 mm in length by about 0.8±0.

Abstract: A capacitor includes a ceramic capacitor body having opposite ends and comprised of a plurality of electrode layers and dielectric layers and first and second external terminals attached to the ceramic capacitor body. The internal active electrodes within the ceramic capacitor body are configured in an alternating manner. Internal electrode shields within the ceramic capacitor body are used to assist in providing resistance to arc-over. The shields can include a top internal electrode shield and an opposite bottom internal electrode shield wherein the top internal electrode shield and the opposite bottom internal electrode shield are on opposite sides of the plurality of internal active electrodes and each internal electrode shield extends inwardly to or beyond a corresponding external terminal to thereby provide shielding. Side shields are used. The capacitor provides improved resistance to arc-over, high voltage breakdown in air, and allows for small case size.

Abstract: A fabrication method which forms vertical capacitors in a substrate. The method is preferably an all-dry process, comprising forming a through-substrate via hole in the substrate, depositing a first conductive material layer into the via hole using atomic layer deposition (ALD) such that it is electrically continuous across the length of the via hole, depositing an electrically insulating, continuous and substantially conformal isolation material layer over the first conductive layer using ALD, and depositing a second conductive material layer over the isolation material layer using ALD such that it is electrically continuous across the length of the via hole. The layers are arranged such that they form a vertical capacitor. The present method may be successfully practiced at temperatures of less than 200° C., thereby avoiding damage to circuitry residing on the substrate that might otherwise occur.

Abstract: A disclosed capacitor sheet attached to an electronic apparatus comprises: a laminated body; a first penetration electrode penetrating the laminated body, the first penetration electrode being electrically connected to a terminal electrode of the electronic apparatus; a second penetration electrode disposed at an arrangement position different from that of the first penetration electrode on the laminated body, the second penetration electrode being electrically insulated from the first penetration electrode and penetrating the laminated body; at least one first conductor thin film electrically connected to the first penetration electrode and insulated from the second penetration electrode; and at least one second conductor thin film disposed so as to face the first conductor thin film via a dielectric layer, the second conductor thin film being electrically connected to the second penetration electrode and insulated from the first penetration electrode.

Abstract: Devices and methods for their formation, including electronic devices containing capacitors, are described. In one embodiment, a device includes a substrate and a capacitor is formed on the substrate. The capacitor includes first and second electrodes and a capacitor dielectric between the first and second electrodes. At least one of the first and second electrodes includes a metal layer having carbon nanotubes coupled thereto. In one aspect of certain embodiments, the carbon nanotubes are at least partially coated with an electrically conductive material. In another aspect of certain embodiments, the substrate comprises an organic substrate and the capacitor dielectric comprises a polymer material. Other embodiments are described and claimed.

Abstract: An electrical component includes ceramic layers that are stacked to form a base body, electrode layers among the ceramic layers to form at least one capacitor, at least one phase gate on a ceramic layer that corresponds to a surface of the base body, contact surfaces on a top surface of the base body, and through contacts that electrically connect the electrode layers to the contact surfaces. The through contacts are inside the base body at least in part. Side surfaces of the base body are substantially free of surface metallic contacts and of metal plating.

Abstract: The invention provides a multilayer ceramic capacitor comprising a capacitor body composed by alternately layering dielectric layers and inner electrode layers. Accordingly, the multilayer ceramic capacitor has high relative permittivity and is high the temperature property and highly accelerated life test property.

Abstract: A method of manufacturing a capacitor-embedded low temperature co-fired ceramic substrate. A capacitor part is manufactured by firing a deposition including at least one high dielectric ceramic sheet to form a capacitor part. A plurality of low temperature co-fired green sheets are provided. Each of the low temperature co-fired green sheet has at least one of a conductive pattern and a conductive via hole thereon. A low temperature co-fired ceramic deposition is formed by depositing the low temperature co-fired green sheets to embed the capacitor part in the low temperature co-fired ceramic deposition. The embedded capacitor part is connected either to the conductive pattern or the conductive via hole of an adjacent green sheet. Then the low temperature co-fired ceramic deposition having the capacitor part embedded therein is fired.

Abstract: A multilayer capacitor having a capacitor body, first and second inner electrodes, and first and second terminal electrodes. A first terminal electrode is arranged on a first surface of the capacitor body which is parallel to a first direction, and connected to the first inner electrode. A second terminal electrode is connected to the second inner electrode. The first inner electrode has a first main electrode portion including a first no-capacity generating region and a first capacity generating region, and a first lead electrode portion. In a second direction, the first terminal electrode is set smaller than the first surface, while the first lead electrode portion is set smaller than the first main electrode portion. The first no-capacity generating region and the first lead electrode portion overlap each other in the second direction when seen in the first direction.

Abstract: A capacitor element includes a lower conductive portion, an underlying film which covers the lower conductive portion, a lower electrode formed on the underling film, a capacitor insulating film including (i) a dielectric film formed on the lower electrode and (ii) a protective film formed on the dielectric film and having a lower etching rate than that of the dielectric film, and an upper electrode formed on the capacitor insulating film. The upper electrode and the lower conductive portion are electrically connected to each other through a connection portion exposed from the underlying film by partially removing the underlying film and the capacitor insulating film.

Abstract: A first terminal electrode has a first electrode portion disposed on a first face and connected to a first internal electrode, and a second electrode portion disposed on a third face and connected to the first electrode portion. A second terminal electrode has a first electrode portion disposed on a second face and connected to a second internal electrode, and a second electrode portion disposed on the third face and connected to the first electrode portion. Each of the second electrode portions of the first and second terminal electrodes, when viewed along a third direction perpendicular to the third face, is arranged with a gap in the second direction so as to sandwich at least a portion of an end in the first direction of an element body region sandwiched between the first internal electrode and the second internal electrode, at an end in the first direction of the second electrode portion.

Abstract: A capacitor comprises m electrode plates that are arranged spaced apart and in parallel, where m is an integer greater than one. Even ones of the m electrode plates comprise x extensions that extend from the first side and that have a first width. Odd ones of the m electrode plates comprise y extensions that extend from the first side and that have a second width that is less than the first width. The x extensions are located between the y extensions when the m electrode plates are arranged in parallel. n first external terminals that are arranged on a first exterior surface of the capacitor. The x extensions are coupled to x of the n first external terminals and wherein the y extensions of the odd ones of the m electrode plates are coupled to y of the n first external terminals.

Abstract: Low inductance capacitors include electrodes that are arranged among dielectric layers and oriented such that the electrodes are substantially perpendicular to a mounting surface. Vertical electrodes are exposed along a device periphery to determine where termination lands are formed, defining a narrow and controlled spacing between the lands that is intended to reduce the current loop area, thus reducing the component inductance. Further reduction in current loop area and thus component equivalent series inductance (ESL) may be provided by interdigitated terminations. Terminations may be formed by various electroless plating techniques, and may be directly soldered to circuit board pads. Terminations may also be located on “ends” of the capacitors to enable electrical testing or to control solder fillet size and shape. Two-terminal devices may be formed as well as devices with multiple terminations on a given bottom (mounting) surface of the device.

Abstract: A ceramic dielectric composition suitable for preparing capacitors for use in high-temperature service conditions is disclosed. The ceramic material and capacitors made from it exhibit unique and heretofore unrealizable properties including low variation in capacitance with voltage up to high fields, low variation in capacitance with temperature over a broad temperature range, retained high permittivity at temperatures up to 200° C. and beyond, low loss, low field-induced strain and adequate capacitance to retain performance at very low service temperatures. The material is based on sodium bismuth titanate (NBT) with selected additions of substituents and dopants to broaden and flatten its dielectric response, lower loss, lower strain, lower voltage coefficient and increase resistivity.

Abstract: A capacitor comprises a substrate layer, a first electrode layer disposed on the substrate layer, and a first dielectric layer disposed on the electrode layer. The dielectric layer comprises inorganic ferroelectric or antiferroelectric particles, and a polymeric material having an elongation less than or equal to about 5 percent.

Abstract: A method of manufacturing a multilayer capacitor comprises a first layer forming step, a first electrode forming step, a second layer forming step, a second electrode forming step, a separation step, an element forming step and a terminal forming step. In the first layer forming step, a first ceramic green layer is formed on a supporting body. In the first electrode forming step, a first electrode pattern is formed on the first ceramic green layer. In the second layer forming step, a second ceramic green layer is formed laminated on the first ceramic green layer. In the second electrode forming step, a second electrode pattern is formed at the second ceramic green layer. In the separation step, the support body is separated from the laminated body. In the element forming step, elements are formed by laminating a plurality of the laminated bodies.

Abstract: Dielectric powder and thick-film paste compositions are formed having high dielectric constants, low loss tangents, and other desirable electrical and physical properties. Conductive powder and paste compositions are formed having desirable electrical and physical properties. The dielectric powder and thick-film paste compositions can be used in combination with the conductive powder and paste compositions to form capacitors and other fired-on-foil passive circuit components.

Abstract: A monolithic or essentially monolithic single layer capacitor with high structural strength and capacitance, a printed circuit board having the capacitor mounted thereon, and a method of making. Sheets of green-state ceramic dielectric material and glass/metal composite material are laminated together, diced into individual chips, and fired to sinter the glass and the ceramic together. The composite material contains an amount of metal sufficient to render the composite conductive whereby the composite may be used for one or both electrodes and for mounting the capacitor to the printed circuit board. Vertically-oriented surface mountable capacitors and hybrid capacitors are provided.

Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.

Abstract: A fabrication method for parallel-plate structures and a parallel-plate structure arrangement, wherein the structures have a middle layer, grown on a substrate and disposed between top and bottom electrode layers, wherein the middle layer and the top and bottom electrode layers are deposited on a bottom substrate, and wherein the middle layer is grown first and the top and bottom electrodes are essentially deposited afterwards.

Abstract: There is provided a multilayer capacitor including an inner connecting conductor of at least one polarity; a plurality of first and second outer electrodes formed on a surface of the body, wherein the inner connecting conductor is connected to a corresponding one of the outer electrodes having identical polarity, a corresponding one of the inner electrodes having identical polarity to the inner connecting conductor includes a plurality of groups each including at least one of the inner electrodes, wherein the inner electrodes of the respective groups are connected to the outer electrodes having identical polarity that are different from one another for each of the groups and electrically connected to the inner connecting conductor through the connected outer electrode.

Abstract: Polymer-ceramic composite materials for use in the formation of capacitors, which materials exhibit very low changes in temperature coefficient of capacitance (TCC) in response to changes in temperature within the range of from about ?55° C. to about 125° C. Specifically, these capacitor materials have a change in TCC ranging from about ?5% to about +5%, in response to changes in temperature within the desired temperature range. The inventive composite materials comprise a blend of a polymer component and ferroelectric ceramic particles, wherein the polymer component includes at least one epoxy-containing polymer, and at least one polymer having epoxy-reactive groups. The inventive polymer-ceramic composite materials have excellent mechanical properties such as improved peel strength and lack of brittleness, electrical properties such as high dielectric constant, and improved processing characteristics.

Abstract: The invention relates to an electronic component including a capacitor and provides an electronic component in which electromigration can be prevented and whose capacitor element has an accurate capacity value. The electronic component includes a bottom conductor formed on a substrate, a dielectric film formed to cover the bottom conductor, an organic insulation film formed on the dielectric film, and a top conductor formed in an opening provided in the organic insulation film over the bottom conductor, the top conductor forming a capacitor element in combination with the bottom conductor and the dielectric film.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A method including depositing a suspension of a colloid having an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device having a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate having at least one capacitor structure formed on a surface, the capacitor structure having a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material has columnar grains.

Abstract: A production method of a multilayer electronic device, comprising the steps of forming an electrode layer 12a on a first support sheet 20; forming a green sheet 10a on a surface of the electrode layer 12a to obtain a green sheet 10a having an electrode layer 12a; stacking the green sheets 10a, each having the electrode layer 12a, to form a green chip; and firing the green chip: wherein before stacking the green sheet 10a having the electrode layer 12a, an adhesive layer 28 is formed on a surface on the opposite side of the electrode layer side of the green sheet 10a having the electrode layer 12a; and the green sheet 10a having the electrode layer 12a formed thereon is stacked via the adhesive layer 28.

Abstract: An exemplary embodiment providing one or more improvements includes a capacitor with a segmented end electrode and methods for segmenting an end electrode of a capacitor for reducing or eliminating instances of thermally induced damage of the capacitor.

Abstract: A capacitor comprises a substrate layer, a first electrode layer disposed on the substrate layer, and a first dielectric layer disposed on the electrode layer. The dielectric layer comprises a polymeric material having an elongation less than or equal to about 5 percent.

Abstract: A multilayer ceramic capacitor includes a plurality of ceramic dielectric layers, a plurality of inner electrode layers and and external electrodes. The ceramic dielectric layers includes barium titanate crystal grains having pores inside. The inner electrode layers are between the ceramic dielectric layers. The external electrodes are electrically connected to the inner electrode layers. The barium titanate crystal grains each have a core-shell structure which include a core and a shell around the core. The the pores are mainly formed in the cores.

Abstract: A capacitor body of a multilayer feedthrough capacitor is arranged with grounding inner electrodes and signal inner electrodes. The grounding inner electrodes include first and second grounding main electrode portions, grounding connection electrode portions having no areas opposing the signal inner electrodes, and first and second grounding lead electrode portions. The signal inner electrodes include first and second signal main electrode portions, signal connection electrode portions having no areas opposing the grounding inner electrodes, and first and second signal lead electrode portions.