Abstract: An integrated circuit capacitor structure includes a first wall that serves as a first terminal for each capacitor of a plurality of capacitors. The capacitor structure also includes a plurality of second walls, with each second wall serving as a second terminal for a different capacitor of the plurality of capacitors. The first wall and the second walls stand parallel to each other. In embodiments, the capacitor structure includes a substrate on which the first and the second walls stand perpendicularly. In embodiments, the first wall includes a plurality of first finger regions extending from a first common region of the first wall, and one or more of the first finger regions is at least partially positioned between different second walls.

Abstract: A method for manufacturing a capacitor includes the steps of: forming a conductive layer above a base substrate; forming a dielectric layer above the conductive layer; forming a lanthanum nickelate layer above the dielectric layer; and patterning at least the dielectric layer by using at least the lanthanum nickelate layer as a mask.

Abstract: A method of forming a conductor on a substrate including steps of depositing tantalum on a glass layer of the substrate; oxidizing the tantalum; and depositing a noble metal on the oxidized tantalum to form the conductor. The method can be used to form a ferroelectric capacitor or other thin film ferroelectric device. The device can include a substrate comprising a glass layer; and an electrode connected to the glass layer. The electrode comprising can include a noble metal connected to the glass layer by an adhesion layer comprising Ta2O5.

Abstract: A multi-layer ceramic capacitor including: a ceramic sintered body having cover layers provided on upper and lower surfaces thereof as outermost layers and a plurality of ceramic layers disposed between the cover layers; first and second internal electrodes formed on the ceramic layers, the first and second internal electrodes stacked to interpose one of the ceramic layers; first and second external electrodes formed on opposing sides of the ceramic sintered body to connect to the first and second internal electrodes, respectively; and anti-oxidant electrode layers formed between the cover layers and adjacent ones of the ceramic layers, respectively, the anti-oxidant electrode layers arranged not to affect capacitance.

Abstract: A multilayer chip capacitor including: a capacitor body where a plurality of dielectric layers are deposited, the capacitor body having opposing first and second sides and opposing third and fourth sides; a plurality of layers of internal electrodes deposited alternately with the dielectric layers in the capacitor body; at least one first external electrode formed on the first side; and at least one second external electrode formed on the second side, wherein the first and second external electrodes are staggered with respect to each other and spaced apart from each other at a certain distance in a length direction of the first side.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

Abstract: The invention relates to a method for a complex oxide film having a high relative dielectric constant and a thickness which can be arbitrarily controlled, which is obtained, without using any large-scale equipment, by forming a metal oxide layer containing a first metal element on substrate surface and then allowing the layer to react with a solution containing a second metal ion to thereby form a complex oxide film containing the first and second metal elements, and a production method thereof. Further, the invention relates to a dielectric material and a piezoelectric material containing the complex oxide film, a capacitor and a piezoelectric element including the material, and an electronic device comprising the element.

Abstract: A multilayer zinc oxide varistor without bismuth oxide system ingredients, and having variable breakdown voltages by controlling the thickness of the ceramic material; the varistor is bismuth-free and composed of zinc oxide as the primary constituent with alkaline earth element (Ba) as first additive, at least one of transition elements of Mn, Co, Cr, or Ni as second additives, at least one of rare earth elements of Pr, La, Ce, Nd or Tb as third additives and at least one of B, Si, Se, Al, Ti, W, Sn, Sb, Na, or K as rest additives, and the bismuth-free and zinc oxide based varistor exhibits an excellent ESD (Electro-Static Discharge) withstanding characteristic.

Abstract: A capacitor is provided. The capacitor includes a dielectric polymer film comprising a cyanoresin and at least one electrode coupled to the dielectric polymer film. The capacitor has an energy density of at least about 5 J/cc. A method of making a capacitor is provided. The method includes dissolving a cyanoresin in a solvent to form a solution and coating the solution on a substrate to form a dielectric polymer film. The dielectric polymer film has a breakdown strength of at least about 300 kV/mm.

Abstract: The invention relates to a capacitor having a porous electrically conductive substrate on whose inner and outer surfaces a first layer of a dielectric and an electrically conductive second layer are applied. The invention also relates to a method for the production of such capacitors and to their use in electrical and electronic circuits.

Abstract: A capacitor provided with a dielectric film, and a first electrode and second electrode formed sandwiching it and facing each other, wherein the dielectric film has a density exceeding 72% of the theoretical density calculated based on the lattice constant, and either or both of said first electrode and said second electrode contain at least one metal selected from the group consisting of Cu, Ni, Al, stainless steel and a nickel-based alloy.

Abstract: The invention includes capacitor constructions which have a layer of aluminum oxide between a high-k dielectric material and a layer containing titanium and nitrogen. The layer containing titanium and nitrogen can be, for example, titanium nitride and/or boron-doped titanium nitride. The capacitor constructions can be incorporated into DRAM cells, which in turn can be incorporated into electronic systems. The invention also includes methods of forming capacitor constructions.

Abstract: In order to provide a built-in capacitor type wiring board capable of preventing misalignment of the capacitor, a capacitor built-in type wiring board is provided which includes a core board; a multilayer portion disposed on at least one side of the core board and formed by a plurality of interlayer insulating layers; and a plurality of conductor layers alternately laminated on the core board. The capacitor is of a chip-like shape with first and second main surfaces and includes a dielectric layer; electrode layers laminated on the dielectric layer; and a hole portion opening at least at the second main surface. The capacitor is embedded in the interlayer insulating layers so that the second main surface faces the core board.

Abstract: Disclosed is a composition for forming a dielectric, which is applied to an embedded capacitor with a high dielectric constant, a capacitor produced using the composition, and a PCB provided with the capacitor. The composition includes 40 to 99 vol % of thermoplastic or thermosetting resin, and 1 to 60 vol % of semiconductive filler. Alternatively, the composition includes 40 to 95 vol % of thermoplastic or thermosetting resin, and 5 to 60 vol % of semiconductive ferroelectric substance. Furthermore, the present invention provides the capacitor, produced using the composition, and the PCB provided with the capacitor. Therefore, the dielectric, which is produced using the composition including the semiconductive filler or semiconductive ferroelectric substance, is advantageous in that the dielectric constant is high and a dielectric loss is low. The dielectric is usefully applied to produce an embedded capacitor with the high dielectric constant and the PCB provided with the embedded capacitor.

Abstract: A method for forming an alpha-tantalum layer comprising disposing a nitrogen containing base layer on a semiconductor substrate, bombarding the nitrogen containing base layer with a bombarding element, thereby forming an alpha-tantalum seed layer, and sputtering a layer of tantalum on the alpha-tantalum seed layer, thereby forming a surface layer of substantially alpha-tantalum.

Abstract: A multi-layered printed circuit board embedded with a filter, the multi-layered printed circuit board using a composite multi-layered printed circuit board formed of at least a high dielectric material stacked with at least a low dielectric material. A plurality of serial or parallel capacitors are disposed in the composite multi-layered printed circuit board so as to form a filter. At least one capacitor is an interdigital capacitor disposed on a low dielectric material. Metal electrodes of the interdigital capacitor are located on the same plane such that the area of the metal electrodes or the spacing between the metal electrodes can be adjusted in advance to precisely control the electrical properties such as the center frequency and the transmission loss of the filter. Problems resulting from alignment errors caused in manufacturing the composite multi-layered printed circuit board can also be prevented.

Abstract: Disclosed herein are new MIM structures having increased capacitance with little or no tunneling current, and related methods of manufacturing the same. In one embodiment, the new MIM structure comprises a first electrode comprising a magnetic metal and having a magnetic moment aligned in a first direction, and a second electrode comprising a magnetic metal and having a magnetic moment aligned in a second direction antiparallel to the first direction. In addition, such an MIM structure comprises a dielectric layer formed between the first and second electrodes and contacting the first and second magnetic metals.

Abstract: An electronic device having an element body comprising an internal electrode layer, wherein the internal electrode layer includes an alloy, the alloy contains a nickel (Ni) element and at least one kind of element selected from ruthenium (Ru), rhodium (Rh), rhenium (Re) and platinum (Pt), and a content of each component is Ni: 80 to 100 mol % (note that 100 mol % is excluded) and a total of Ru, Rh, Re and Pt: 0 to 20 mol % (note that 0 mol % is excluded).

Abstract: A production method of a multilayer electronic device having an element body configured by alternately stacked dielectric layers formed by using dielectric paste and internal electrode layers formed by using conductive paste: wherein an adding quantity of a co-material included in conductive paste for forming internal electrode layers at the outermost positions in the stacking direction is larger than an adding quantity of a co-material included in conductive paste for forming internal electrode layers at the center position in the stacking direction when adding conductive particles and co-material particles to the conductive paste.

Abstract: A semiconductor device has a semiconductor substrate, and a capacitor which is provided on the upper side of the semiconductor substrate and composed of a lower electrode, an upper electrode and a dielectric film, the dielectric film being placed in between the lower electrode and the upper electrode, the lower electrode including a noble metal film, and a plurality of conductive oxide films formed in an islands arrangement on the noble metal film.

Abstract: A layered capacitor structure comprises two or more semiconductor/dielectric plates formed above an insulating surface which provides mechanical support, with the plates arranged in a vertical stack on the insulating surface. An insulating layer is on each plate, patterned and etched to provide an opening which allows the top of one plate to be in physical and electrical contact with the bottom of the subsequent plate. Contact openings are provided through the insulating layers, each of which provides access to a respective semiconductor layer and is insulated from any other semiconductor/dielectric plate. Electrical contacts through the contact openings provide electrical connections to respective semiconductor layers. The present structure can include as many stacked layers as needed to provide a desired total capacitance or range of capacitances.

Abstract: The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO2) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure.

Abstract: Multi-layered dielectric films which can improve the performance characteristics of a microelectronic device are provided as well as methods of manufacturing the same. The multi-layered dielectric film includes a single component oxide layer made of a single component oxide, and composite components oxide layers made of a composite components oxide including two or more different components formed along either side of the single component oxide layer without a layered structure.

Abstract: An example of a multi-layer ceramic capacitor may include multiple dielectric sheets. In a cross section of each dielectric sheet, there may be printed a first external electrode, a first internal electrode which includes one or more protrusions and which is joined to the first external electrode by way of an interposed dielectric portion, a second external electrode joined as a single body to the first internal electrode, and a second internal electrode joined to the first internal electrode with a dielectric portion positioned in a space defined by the protrusions. The dielectric sheets may be stacked alternately to be symmetrical, such that the first external electrodes and the second external electrodes are electrically connected and the protrusions of the first internal electrodes and the second internal electrodes are electrically connected. In this way, the areas of the internal electrodes can be maximized.

Abstract: The present invention aims to provide an electronic component capable of reducing the occurrence of cracks at the joining portion to a board etc. A capacitor 1 (laminated ceramic capacitor) being one example of the electronic component is provided with an element assembly 10 (ceramic) and a pair of external electrodes 20 formed on both side surfaces of the element assembly 10. In the element assembly 10, a dielectric layer 12 and an internal electrode 14 are laminated alternately. The external electrode 20 has such constitution that a first electrode layer connected with the internal electrode, a second electrode layer (electroconductive resin layer) including a hardened product of thermohardening resin containing a polyphenol compound having a side chain composed of an aliphatic group, a third electrode layer composed of Ni and a fourth electrode layer composed of Sn are formed in this order from the element assembly side.

Abstract: An amorphous dielectric film for use in a semiconductor device, such as a DRAM, and a method of manufacturing the amorphous dielectric film, includes bismuth (Bi), titanium (Ti), silicon (Si), and oxide (O). The amorphous dielectric film may have a dielectric constant of approximately 60 or higher. The amorphous dielectric film may be expressed by the chemical formula Bi1-x-yTixSiyOz, where 0.2<x<0.5, 0<y<0.5, and 1.5 <z<2.

Abstract: A wound capacitor has a lead configuration that enables enhanced control over equivalent series resistance (ESR) and equivalent series inductance (ESL). The capacitor has a case and a wound foil disposed within the case. A ball-and-lead configuration is coupled to the foil and extends from the case.

Abstract: The invention provides an embedded multilayer chip capacitor, and a printed circuit board having the same. The embedded multilayer chip capacitor has a capacitor body having a plurality of dielectric layers stacked one on another; a plurality of first and second internal electrodes formed inside the capacitor body, separated by the dielectric layers; and first and second vias extended vertically inside the capacitor body. The first via is connected to the first internal electrodes and the second via is connected to the second internal electrodes. The first via is led to a bottom of the capacitor body and the second via is led to a top of the capacitor body.

Abstract: Disclosed is a capacitor with a dielectric layer having a low equivalent oxide thickness compared to a HfO2 layer and capable of decreasing a level of a leakage current incidence and a method for fabricating the same. Particularly, the capacitor includes: a bottom electrode; a Hf1-xLaxO layer on the bottom electrode; and a top electrode on the Hf1-xLaxO layer, wherein x is an integer. The method includes the steps of: forming at least one bottom electrode being made of polysilicon doped with impurities; nitriding a surface of the bottom electrode; depositing the amorphous Hf1-xLaxO layer on the nitrided surface of the bottom electrode; performing a thermal process for crystallizing the amorphous Hf1-xLaxO layer and removing impurities existed within the Hf1-xLaxO layer; nitriding a surface of the crystallized Hf1-xLaxO layer; and forming the top electrode being made of polysilicon doped with impurities on the nitrided surface of the crystallized Hf1-xLaxO layer.

Abstract: A polymeric dielectric composition is disclosed, having a paraelectric filler with a dielectric constant between 50 and 150. Such compositions are well suited for electronic circuitry, such as, multilayer printed circuits, flexible circuits, semiconductor packaging and buried film capacitors.

Abstract: A multilayer ceramic capacitor and a method of manufacturing the same is provided. The capacitor comprises dielectric layers and internal electrode layers alternately stacked. Two of the internal electrode layers that are located outermost and/or at least one of the internal electrode layers that is located inside each outermost internal electrode layer are substantially oxidized and do not function as electrodes. The capacitance of the multilayer ceramic capacitor depends on the unoxidized internal electrode layers other tan the oxidized ones. The method of manufacturing a multilayer ceramic capacitor comprises forming green dielectric layers, forming green internal electrode layers, preparing a green ceramic chip, forming green external electrodes, and firing the green ceramic chip.

Abstract: A capacitor for use with RF signals of an operating frequency has a parallel plate configuration including a bottom electrode, a top electrode, and a dielectric layer disposed between the bottom and top electrodes, and an additional mass layer disposed on top of the top electrode. The parallel plate configuration is capable of receiving a DC voltage bias that affects the capacitance value of the parallel plate configuration, and exhibits a standing wave resonance frequency at the operating frequency. The mass layer has a density and a thickness selected to dampen the magnitude of the resonance of the parallel plate configuration at the standing wave resonance frequency and shift the standing wave resonance frequency away from the operating frequency.

Abstract: A multilayer capacitor has a capacitor element, inner electrodes arranged within the capacitor element, and first to fourth terminal electrodes. Electrode parts of the first to fourth terminal electrodes cover ridges formed between first and third side faces, first and fourth side faces, second and third side faces, and second and fourth side faces. The capacitor element has an element part. The element part is formed such as to overlap the electrode parts when seen in a second and a third directions and keep away from respective areas about the electrode parts when seen in a first direction.

Abstract: One embodiment includes a method that includes positioning a first substantially planar electrode including material defining a first aperture into a capacitor stack in alignment with a second substantially planar electrode such that a first non-aperture portion of the second substantially planar electrode at least partially overlays the first aperture and joining the first substantially planar electrode to the second substantially planar electrode proximal the material defining the first aperture and the first non-aperture portion of the second substantially planar electrode.

Abstract: Systems and methods for reducing switching noise in an integrated circuit. In one embodiment, decoupling capacitors are connected to the integrated circuit from the underside of the substrate on which the integrated circuit die is manufactured. The decoupling capacitors are positioned with a higher concentration in the “hot spot” areas of the integrated circuit instead of being evenly distributed. In one embodiment, the decoupling capacitors and the corresponding hole(s) in a circuit board on which the integrated circuit is mounted are positioned so that the circuit board provides support for the central portion of the integrated circuit and thereby prevents the integrated circuit from flexing away from the heat sink/spreader. In one embodiment, the concentration of vias connecting the different ground planes and/or power planes within the integrated circuit is higher in hot spots than in other areas.

Abstract: Composite materials for the formation of printed circuit boards and electronic devices. A composite structure of the invention includes an electrically conductive layer and a dielectric layer. The dielectric layer includes a plurality of adjacent dielectric material patches arranged in a patchwork configuration, which patches are made up of different dielectric materials to thereby result in areas of differential capacitance.

Abstract: A metal-insulator-metal capacitor formed in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels.

Abstract: Capacitors including a first conductive material having a first upper finger located on an upper plane and a first lower finger located on a lower plane. The capacitor also includes a second conductive material having a second upper finger and a second lower finger, the second upper finger located on the upper plane such that the second upper finger is next to the first upper finger forming a first interface and on top of the first lower finger forming a second interface, the second lower finger located on the lower plane such that the second lower finger is next to the first lower finger forming a third interface and below the first upper finger forming a fourth interface. Finally, the capacitor includes a dielectric material located in the first interface, the second interface, the third interface, and the fourth interface.

Abstract: A multilayer capacitor includes a capacitor body in which internal electrodes in a first internal electrode group are overlapped with internal electrodes in a second internal electrode group with dielectric layers sandwiched therebetween. A first external electrode has a first wraparound portion and a second wraparound portion, and a second external electrode has a third wraparound portion and a fourth wraparound portion. The volume proportions of the effective layers in a first area sandwiched between the first wraparound portion and the second wraparound portion and in a third area sandwiched between the third wraparound portion and the fourth wraparound portion are set to at least about 10%. The volume proportions of the effective layers in a second area toward a lower surface in the first area and in a fourth area toward the lower surface in the third area are set to about 15% or less. The external dimensions of the multilayer capacitor 1 are about 1.6±0.1 mm in length by about 0.8±0.

Abstract: An organic dielectric material comprises a branched and/or hyperbranched macromolecule having delocalized electrons. Such macro-molecular organic material systems have desirable delocalized charge and optionally one or more micro-crystalline regions. Organic dielectric materials include, for example, branched polyanilines and phthalocyanines. Delocalized excitations within the macromolecular framework of the organic dielectric material may be used in various applications, such as light harvesting, nonlinear optical, quantum optical, and electronic applications, e.g., capacitors. Electrical devices may comprise such dielectric materials, including capacitors that have very high energy density, storage, and transfer. Also provided are methods of preparing such materials.

Abstract: A multi-segment parallel wire capacitor includes substantially identical multiple capacitor segments fabricated on a semiconductor substrate. Each segment comprises at least first and second interleaved metal finger formed in a first metal layer above the substrate and third and fourth interleaved metal fingers formed in a second metal layer. The first and fourth sets are connected together to form one plate of the capacitor and the second and third sets are connected to form a second plate. The multiple capacitor segments are arranged in a matrix having M rows and N columns. The multiple capacitor segments are inter-connected in such a manner that the capacitor segments in each column of the matrix are connected in parallel. First and second metal lines selectively connect the plates of the different capacitor segments in the first and last rows and serve as the two opposite terminals of the multi-segment parallel wire capacitor.

Abstract: Disclosed is an ultracapacitor having electrodes containing mineral microtubules, an electrolyte between the electrodes, and a separator in the electrolyte to provide electrical insulation between the electrodes, while allowing ion flow within the electrolyte. The electrodes may be formed from a paste containing microtubules, a conductive polymer containing mineral microtubules, or an aerogel containing the mineral microtubules. The mineral microtubules may be filled with carbon, a pseudocapacitance material, or a magnetoresistive material. The mineral microtubules may also be coated with a photoconductive material.

Abstract: Capacitors and methods for fabricating the same are provided. An exemplary embodiment of a capacitor comprises a dielectric layer and a first conductive layer thereover. A supporting rib is embedded in the first conductive layer and extends along a first direction. A second conductive layer is embedded in the first conductive layer and extends along a second direction perpendicular with the first direction, wherein a portion of the second conductive layer forms across the supporting rib and is structurally supported by the supporting rib. A capacitor layer is formed between the first and second conductive layers to electrically insulate the first and second conductive layers.

Abstract: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Abstract: A multilayer electronic component has: a first capacitive electrode layer of a rectangular shape on which four capacitive electrode portions are formed at four comers; and a ground electrode layer which is laid on the first capacitive electrode layer and on which a ground electrode is formed so as to be arranged as superposed over the four capacitive electrode portions. The four capacitive electrode portions are equidistant from a first facing edge pair of the first capacitive electrode layer and equidistant from a second facing edge pair different from the first edge pair. This configuration equalizes distributions of electric fields established between the respective capacitive electrode portions and the ground electrode, which realizes uniformization of the capacitances in the four respective capacitive electrode portions.

Abstract: A highly reliable multilayer ceramic electronic device is obtained while preventing crack defects generated in a ceramic laminate by application of a heat shock in a mounting step or the like. The multilayer ceramic electronic device is constructed such that the average value of continuities of internal electrodes located in two regions (f) is lower by 5% to 20% inclusive than the average value of continuities of internal electrodes located in the central portion in a lamination direction. The two regions (f) are the regions from the topmost internal electrode and the bottommost internal electrode located in the lamination direction to the inside, respectively, within 10% of the distance (d) therebetween. Continuity is defined by (X?Y)/X in which X is the length of a cross section of an internal electrode in one direction and Y indicates the sum of gaps (g) formed by pores in the cross section of the internal electrode.

Abstract: An electrical-energy-storage unit (EESU) has as a basis material a high-permittivity composition-modified barium titanate ceramic powder. This powder is single coated with aluminum oxide and then immersed in a matrix of poly(ethylene terephthalate) (PET) plastic for use in screen-printing systems. The ink that is used to process the powders via screen-printing is based on a nitrocellulose resin that provide a binder burnout, sintering, and hot isostatic pressing temperatures that are allowed by the PET plastic. These lower temperatures that are in the range of 40° C. to 150° C. also allows aluminum powder to be used for the electrode material. The components of the EESU are manufactured with the use of conventional ceramic and plastic fabrication techniques which include screen printing alternating multilayers of aluminum electrodes and high-permittivity composition-modified barium titanate powder, sintering to a closed-pore porous body, followed by hot-isostatic pressing to a void-free body.

Abstract: This invention provides novel capacitors comprising nanofiber enhanced surface area substrates and structures comprising such capacitors, as well as methods and uses for such capacitors.

Abstract: A method for manufacturing a capacitor includes the steps of: forming a lanthanum nickelate layer above a base substrate; forming a dielectric layer above the lanthanum nickelate layer; forming a conductive layer above the dielectric layer; and patterning at least the dielectric layer until the lanthanum nickelate layer is exposed.

Abstract: A multilayer electronic component having a ceramic substrate and a resin layer mounted on a mounting substrate. Recess portions are formed at an outside-facing major surface side of the resin layer. In the resin layer, columnar conductors are disposed so that axis line directions thereof are aligned in a thickness direction of the resin layer. End portions of the columnar conductors are located inside the recess portions further from opening faces thereof and have end surfaces exposed in the recess portions. When a multilayer electronic component is mounted on a mounting substrate, solder is provided on the end surfaces of the columnar conductors in the recess portions. The thickness of solder used in the above mounting does not interfere with a reduction in size and height of an electronic device that includes the above multilayer electronic component.