Abstract: Various capacitors for use with integrated circuits and other devices and fabrication methods are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first capacitor plate that has at least two non-linear strips and forming a second capacitor plate that has a non-linear strip positioned between the at least two non-linear strips of the first capacitor plate. A dielectric is provided between the non-linear strip of the second capacitor plate and the at least two non-linear strips of the first capacitor plate.

Abstract: An MOM capacitor includes a first metal plate; a second metal plate in close proximity to the first metal plate; a third metal plate in close proximity to the first metal plate, and at least one oxide layer interposed between the first, second and three vertical metal plates. The first, second and third metal plate are connected to three different terminals of an integrated circuit.

Abstract: Better high-temperature load characteristics are obtained in a laminated ceramic capacitor including a dielectric ceramic layer with a thickness of 1 ?m or less. The laminated ceramic capacitor includes a plurality of stacked dielectric ceramic layers, a plurality of internal electrode layers, each disposed between dielectric ceramic layers, and external electrodes that are electrically connected to internal electrode layers. In this laminated ceramic capacitor, when the thickness of each dielectric ceramic layer is denoted by tc and the thickness of each internal electrode layer is denoted by te, tc is 1 ?m or less, and tc/te is equal to or less than 1.

Abstract: A capacitor includes a multi layer structure on a ceramic or crystalline substrate. The multilayer structure includes a lower electrode, an upper electrode, and a dielectric that is tunable by a voltage applied to the electrodes. The multilayer structure is configured such that resonant oscillation modes of bulk acoustic waves can be propagated in the multilayer structure and such that the resonant frequencies of the oscillation modes are outside a first band range of between 810 and 1000 MHz, second band range of between 1700 and 2205 MHz and third band range of between 2400 and 2483.5 MHz.

Abstract: A capacitor includes an object or a substrate including an insulation layer having an opening, an electrode structure having conductive patterns, a dielectric layer and an upper electrode. The electrode structure may have a first conductive pattern including metal and a second conductive pattern including metal oxide generated from the first conductive pattern. The first conductive pattern may fill the opening and may protrude over the insulation layer. The second conductive pattern may extend from the first conductive pattern. The electrode structure may additionally include a third conductive pattern disposed on the second conductive pattern. The capacitor including the electrode structure may ensure improved structural stability and electrical characteristics.

Abstract: A composite dielectric material having a plurality of particle cores, each surrounded by polymer strands that are chemically bonded to the surface of the particle core. Each polymer strand includes a linker, through which the polymer strand is attached to the surface, an interfacial core-shielding (ICS) group bound to the linker, and a polymer molecule bound to the ICS group. The ICS groups are designed to inhibit electrical breakdown of the composite dielectric material by (i) deflecting or scattering free electrons away from the particle cores and/or (ii) capturing free electrons by being transformed into relatively stable radical anions. Representative examples of the particle core material, linker, ICS group, and polymer molecule are titanium dioxide, a phosphonate group, a halogenated aromatic ring, and a polystyrene molecule, respectively.

Abstract: A metal capacitor in which an electric conductivity is significantly improved by applying a metal material, instead of a solid electrolyte and electrolyte of an aluminum electrolytic capacitor, and a manufacturing method thereof is provided. A metal capacitor 10 includes a metal member 11 including a plurality of grooves 11a on both surfaces of the metal member 11, a metal oxide film 12 being formed on the metal member 11, a seed electrode layer 13 being formed on the metal oxide film 12, a main electrode layer 14 being formed on the metal oxide film 12 to fill the plurality of grooves 11a, a plurality of lead terminals 15 being installed in the main electrode layer 14, and a molding member 16 being disposed so that the plurality of lead terminals may be externally protruded from the molding member 16, and the metal member 11, the metal oxide film 12, the seed electrode layer 13, and the main electrode layer 14 may be sealed.

Abstract: The present invention relates to a multi-layer ceramic capacitor printed simultaneously with internal electrode and external electrode by employing an inkjet printing. A method for manufacturing the multi-layer ceramic capacitor comprising first external electrode, dielectric, internal electrode and second external electrode prints simultaneously the first external electrode; the internal electrode which is connected with the first external electrode and formed at an invaginated portion of the dielectric invaginated to allow one side to be opened at one portion; and the second external electrode which is formed integrally with the internal electrode by employing an inkjet printing. According to the present invention, a method for manufacturing the multi-layer ceramic capacitor resolves contact problems by printing integrally the internal electrode and the external electrode and reduces the manufacturing process.

Abstract: A collective component has a first region that intersects a conductive paste film for external terminal electrodes in a break line in which break leading holes are arranged and a second region that does not intersect a conductive paste film for external terminal electrodes in the break line. The first break leading holes are formed in the first region so as not to reach the second region. The second break leading holes are formed only in the second region or from the second region to a portion of the first region. The pitch of the first break leading holes is wider than the pitch of the second break leading holes.

Abstract: A capacitor array includes mutually opposed first and second internal electrodes having a first capacitance portion and a second capacitance portion, respectively, a first lead portion and a second lead portion, respectively, which are electrically connected to a first outer terminal electrode and a second outer terminal electrode, and a first protrusion portion and a second protrusion portion, respectively, which partially protrude toward the second outer terminal electrode and the first outer terminal electrode. The outer terminal electrodes have plating films directly connected to the internal electrodes. The plating film is formed by electrolytic plating. In the electrolytic plating, deposition of plating proceeds while being prevented from spreading in width directions of the individual side surfaces by electric fields generated from the protrusion portions toward the vicinities of exposure portions of the respective lead portions on the side surfaces.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to form the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A chip-type electronic component has: a ceramic element body; a plurality of first and second internal electrodes arranged in the ceramic element body so as to be opposed at least in part to each other; a first external connection conductor to which the plurality of first internal electrodes are connected; a second external connection conductor to which the plurality of second internal electrodes are connected; first and second terminal electrodes; a first internal connection conductor arranged in the ceramic element body and connecting the first external connection conductor and the first terminal electrode; and a second internal connection conductor arranged in the ceramic element body and connecting the second external connection conductor and the second terminal electrode.

Abstract: The use of atomic layer deposition (ALD) to form a dielectric layer of hafnium oxide (HfO2) doped with dysprosium (Dy) and a method of fabricating such a combination gate and dielectric layer produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure includes depositing hafnium oxide using atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form the thin laminate structure.

Abstract: The capacitor forming method utilizes a plurality of metal sheet manipulating rollers and a glass supply, which, in combination, make a metal-glass laminate and glass or devitrifying glass dielectric to form a capacitor. Several embodiments of the method manufacture ferroelectric crystal dielectrics by utilizing heat-treatment and annealing to form and devitrify glass while the glass is in a metal-glass spool or flat form.

Abstract: A method of producing capacitor structure includes, in at least one aspect, arranging first layer, adjacent first and second polarity conducting strips, the first layer conducting strips arranged as respective piecewise “S” shaped paths; arranging second layer, adjacent first and second polarity conducting strips, the second layer conducting strips arranged as respective piecewise “S” shaped paths, the second layer second polarity conducting strip is arranged overlying and electrically separated from the first layer first polarity conducting strip, and the second layer first polarity conducting strip is arranged overlying and electrically separated from the first layer second polarity conducting strip; electrically connecting the first layer first polarity conducting strip with the second layer first polarity conducting strip; and electrically connecting the first layer second polarity conducting strip with the second layer second polarity conducting strip.

Abstract: Particular aspects provide capacitors, and particularly ultracapacitors, including molecules suitable to substantially increase the capacitance of the capacitor, and methods for making same, Particular aspects provide ultracapacitors that include nanoparticles optionally coated with molecules, such as polymer electrolytes. Certain aspects provide an energy storage device or capacitor, including at least three layers sealed in a fluid-tight covering, wherein a first layer includes at least one electrolytic polymer molecule of positive charge and at least one nanoparticle; a second dielectric layer including at least one insulative polymer; a third layer including at least one electrolytic polymer molecule of negative charge and at least one nanoparticle.

Abstract: Density-conforming vertical plate capacitors exhibiting enhanced capacitance and methods for fabricating density-conforming vertical plate capacitors exhibiting enhanced capacitance are provided. An embodiment of the density-conforming vertical plate capacitor comprises a first conductive interconnect and a second conductive interconnect. The second conductive interconnect overlies the first conductive interconnect and is substantially aligned with the first conductive interconnect. A via bar electrically couples the first conductive interconnect and the second conductive interconnect. The via bar has a width and a length that is larger than the width and contributes to the capacitance of the vertical plate capacitor.

Abstract: The present invention carries out the vacuum deposition by setting a deposition angle between a single mask set including a shadow mask having a plurality of slits and a deposition source to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once, or adjusts slit patterns by relatively moving upper and lower mask sets that respectively include shadow masks having a plurality of slits and face each other to form a lower terminal layer, a dielectric layer, an inner electrode layer, and an upper terminal layer at once under a vacuum state generated once.

Abstract: Disclosed are dendritic macromolecule-based dielectric compositions (e.g., formulations) and materials (e.g. films) and associated devices. The dendritic macromolecules have branched ends that are functionalized with an organic group that includes at least one 3-40 membered cyclic group.

Abstract: Devices and methods for their formation, including electronic devices containing capacitors, are described. In one embodiment, a device includes a substrate and a capacitor is formed on the substrate. The capacitor includes first and second electrodes and a capacitor dielectric between the first and second electrodes. At least one of the first and second electrodes includes a metal layer having carbon nanotubes coupled thereto. In one aspect of certain embodiments, the carbon nanotubes are at least partially coated with an electrically conductive material. In another aspect of certain embodiments, the substrate comprises an organic substrate and the capacitor dielectric comprises a polymer material. Other embodiments are described and claimed.

Abstract: One embodiment includes an apparatus that includes an implantable device housing, a capacitor disposed in the implantable device housing, the capacitor including a dielectric comprising CaCu3Ti4O12 and BaTiO3, the dielectric insulating an anode from a cathode and pulse control electronics disposed in the implantable device housing and connected to the capacitor.

Abstract: The present invention provides several scalable integrated circuit high density capacitors and their layout techniques. The capacitors are scaled, for example, by varying the number of metal layers and/or the area of the metal layers used to from the capacitors. The capacitors use different metallization patterns to form the metal layers, and different via patterns to couple adjacent metal layers. In embodiments, optional shields are included as the top-most and/or bottom-most layers of the capacitors, and/or as side shields, to reduce unwanted parasitic capacitance.

Abstract: A stable power, low electromagnetic interference (EMI) apparatus and method for connecting electronic devices and circuit boards is disclosed. The apparatus involves a capacitor which includes a body member, a set of power terminals and a set of ground terminals connected to the top of the body member. The set of power terminals and the set of ground terminals alternate one with another. As a result of this configuration, a high inductance on the PCB side is achieved. The capacitor further includes a set of terminals connected to the bottom of the body member and includes metal planes within the body member. The metal planes are positioned to electrically connect either the set of power terminals or the set of ground terminals to the set of terminals.

Abstract: A multilayer capacitor array having a plurality of multilayer capacitor devices formed in a single multilayer structure, the multilayer capacitor array including: a capacitor body formed by depositing a plurality of dielectric layers and having first and second side surfaces opposite to each other; a plurality of first polarity internal electrodes and second polarity internal electrodes, disposed oppositely to each other in the capacitor body, interposing the dielectric layer there between, and formed of a single electrode plate comprising a single lead, respectively; and a plurality of first polarity external electrodes and second polarity external electrodes, formed on the first side surface and second side surface, respectively, and connected to a correspondent polarity internal electrode via the lead, the first polarity external electrode formed on the first side surface and the second polarity external electrode formed on the second side surface, wherein the numbers of the first polarity external electro

Abstract: An NTC capacitor comprises a capacitor body having a plurality of insulator layers laminated therein, first to third inner electrodes arranged within the capacitor body, and first to third terminal electrodes arranged on outer surfaces of the capacitor body. The first inner electrode is connected to only the first terminal electrode. The second inner electrode is connected to only the second terminal electrode. The third inner electrode is connected to only the third terminal electrode. The third inner electrode opposes none of the first and second inner electrodes in the laminating direction of the insulator layers.

Abstract: A method for forming an alpha-tantalum layer comprising disposing a nitrogen containing base layer on a semiconductor substrate, bombarding the nitrogen containing base layer with a bombarding element, thereby forming an alpha-tantalum seed layer, and sputtering a layer of tantalum on the alpha-tantalum seed layer, thereby forming a surface layer of substantially alpha-tantalum.

Abstract: A laminated ceramic electronic component includes a ceramic element and two external electrodes on both end surfaces of the ceramic element. The ceramic element includes a function part and lead parts thinner than the function part. Internal electrode layers are provided facing each other via a ceramic layer therebetween in the function part. The internal electrode layers are drawn out of the function part in the lead part. The external electrode includes an extended part and a curled part. The extended part is formed from the lead part through the function part on the main face. On the main face, the part of the extended part in the lead part is lower than the part of the function part. The curled part is formed from the end face of the ceramic element through the surface of the part of the extended part in the lead part on the main face.

Abstract: A metal capacitor with improved electric conductivity includes a metal member having a through-hole forming portion where a plurality of through-holes are formed, an electrode withdrawing portion formed on the through-hole forming portion, and a sealing portion. The metal capacitor includes a metal oxide layer being formed on the metal member and a main electrode layer formed on the metal oxide layer that is formed on the through-hole forming portion of the metal member, to fill the plurality of through-holes. The metal capacitor further includes an insulating layer formed on the main electrode layer and the metal member to externally expose the electrode withdrawing portion of the metal member.

Abstract: Capacitor plates, capacitors, semiconductor devices, and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes at least one via and at least one conductive member coupled to the at least one via. The at least one conductive member comprises an enlarged region proximate the at least one via.

Abstract: A multilayer capacitor array includes a capacitor body, two first signal terminal electrodes, two second signal terminal electrodes, two grounding terminal electrodes, one first outer connecting conductor, and one second outer connecting conductor, where the capacitor body includes first and second signal inner electrodes, and first to third grounding inner electrodes. The first signal inner electrode is arranged to oppose the first or third grounding inner electrode with at least one insulator layer therebetween, while the second signal inner electrode is arranged to oppose the second or third grounding inner electrode with at least one insulator layer therebetween. The third grounding inner electrode is directly connected to the grounding terminal electrodes, while the first and second grounding inner electrodes are not directly connected to the grounding terminal electrodes, but are connected to the third grounding inner electrode through respective outer connecting conductors.

Abstract: A multilayer film useful for capacitive applications comprises a high energy density layer and a dielectric blocking layer. In some embodiments, a conducting film is located between the high energy density layer and the blocking layer. The high energy density layer may be a fluoropolymer, such as a polymer or copolymer of poly-1,1-difluoroethene or a derivative thereof. The multilayer film may have high energy density (for example,. >8 J/cm3) and low dielectric loss, for example less than 2%, and preferably less than 1%.

Abstract: A thin-film capacitor and a method for making the thin-film capacitor having a structure that can prevent vertical stress acting on outer connecting terminals, such as bumps, from concentrating on electrode layers, and capable of easily increasing the equivalent series resistance to a desired value. The thin-film capacitor includes a substrate, a capacitor unit disposed above the substrate and composed of at least one dielectric thin film and two electrode layers, a protective layer covering at least part of the capacitor unit, a lead conductor electrically connected to one of the electrode layers of the capacitor unit, and a bump disposed above the lead conductor. The lead conductor includes a connecting part disposed in an opening in the protective layer and electrically connected to one of the electrode layers of the capacitor unit, and a wiring part extending over the protective layer. The bump is disposed above the wiring part.

Abstract: The present invention relates to a monomer having the general formula (I) in which R1 and R2 stand, independently of one another, for hydrogen, for an optionally substituted C1-C20-alkyl group or C1-C20-oxyalkyl group, optionally interrupted by 1 to 5 oxygen atoms and/or sulfur atoms, or jointly for an optionally substituted C1-C20-dioxyalkylene group or C6-C20-dioxyarylene group, wherein the monomer has a colour in a range of a Hazen colour number determined according to test method described herein of at least 20, to a Gardner colour number determined according to test method described herein of not more than 5. The present invention also relates to a method for the manufacture of a capacitor, a capacitor obtained by this method and to the use of a monomer.

Abstract: In a monolithic ceramic capacitor, the size of end surfaces of a capacitor body in a two-dimensional surface in which ceramic layers extend is greater than the size of side surfaces in the two-dimensional surface in which the ceramic layers extend. External terminal electrodes include a resistive component. In each of first to fourth internal electrodes, a width-direction size of a lead-out portion is less than a width-direction size of a capacitance portion. The lead-out portions of the first and third internal electrodes and the lead-out portions of the second and fourth internal electrodes are arranged so as to partially overlap each other or not to overlap each other.

Abstract: A metallized plastic film is formed by winding two sheets of film vapor-deposited with an electrode metal as one group and a film capacitor, comprising; three individual splittings of electrode metal by predetermined width and length and then adjoining of splitting parts. Accordingly, self-heating of the film capacitor can be restrained and a capacitance reduction rate caused by the operation of the fuse parts can be reduced.

Abstract: Composite carbon electrodes for use in, for example, Capacitive Deionization (CDI) of a fluid stream or, for example, an electric double layer capacitor (EDLC) are described. Methods of making the composite carbon electrodes are also described. The composite carbon electrode comprises an electrically conductive porous matrix comprising carbon; and an electric double layer capacitor, comprising an activated carbonized material, dispersed throughout the pore volume of the electrically conductive porous matrix.

Abstract: Disclosed herein are a coating solution for the formation of a dielectric thin film and a method for the formation of a dielectric thin film using the coating solution. The coating solution comprises a titanium alkoxide, a ?-diketone or its derivative, and a benzoic acid derivative having an electron donating group. The method comprises spin coating the coating solution on a substrate to form a thin film and drying the thin film at a low temperature to crystallize the thin film. The titanium-containing coating solution is highly stable. In addition, the coating solution enables formation of a thin film, regardless of the kind of substrates, and can be used to form dielectric thin films in an in-line mode in the production processes of PCBs.

Abstract: A dielectric device having a dielectric layer and first to nth metal layers (where n is an integer of 2 or greater) in contact with the dielectric layer. At least one of the first to nth metal layers contains a base metal. Interfaces between the first to nth metal layers and the dielectric layer have respective arithmetic mean roughnesses of Ra1 to Ran (nm), while an average value Ram (nm) of the arithmetic mean roughnesses of Ra1 to Ran (nm) and a thickness T (nm) of the dielectric layer satisfy T/Ram ?1.3.

Abstract: A structure including a TiW oxygen plasma mask, a photoresist mask above and in contact with the TiW oxygen plasma mask, a 2000 angstrom thick oxygen plasma vaporizable RuO0.8 electrode layer partially under and in contact with the TiW oxygen plasma mask, the RuO0.8 electrode layer not being completely covered by a pattern of the TiW oxygen plasma mask, a first side of a PZT ferroelectric layer in contact with the RuO0.8 electrode layer and a second RuO0.8 electrode layer in contact with a second side of the PZT ferroelectric layer.

Abstract: An article having a cyanoresin dielectric film is described. The cyanoresin dielectric film includes nanostructures of a toughening material. A method of forming such a cyanoresin dielectric film is also described. A capacitor having a cyanoresin dielectric film is presented.

Abstract: The method for forming the microelectronic device having at least one two or three dimensional capacitor includes creating, on a substrate, a plurality of components and a number of superimposed metal interconnection levels. An insulating layer is formed above a metal interconnection level, and a horizontal metal zone of a next metal interconnection level in which one or more of the insulating blocks created from this insulating layer are incorporated is formed therein. The zone is designed to form a lower structural part of the capacitor.

Abstract: The present invention relates to a semiconductor device, and more particularly to a method for forming a metal/insulator/metal (MIM). The method comprises the steps of: forming a metal wiring surrounded by the inter-metal dielectric film; forming a plurality of insulating film on the metal wiring in sequence; and forming a metal barrier film on the insulating film, whereby the insulating film functioning as a buffer film can mitigate the stress between the films.

Abstract: In a multilayer capacitor, widths of lead conductors of internal electrode and widths of lead conductors of internal electrode in an ESR control section are smaller than any one of widths of internal electrode and widths of internal electrode in a capacitance section. This narrows cross sections of the conductor portions connecting between the internal electrodes and the external electrodes, so as to her increase ESR. The widths of the respective lead conductors in the ESR control section are wider than widths of respective lead conductors in the capacitance section. This effectively prevents open failure and improves a yield of products.

Abstract: A capacitor is disclosed. The capacitor includes a magnetic layer, a first dielectric layer, a second dielectric layer, a first conductive layer and a second conductive layer. The magnetic layer is capable of generating a magnetic field, and is disposed between the first dielectric layer and the second dielectric layer. The first conductive layer is disposed below the first dielectric layer, and second conductive layer is disposed above the second dielectric layer, wherein both the first and the second conductive layer are non-magnetic.

Abstract: A high frequency device having a membrane structure with improved mechanical strength is provided. The high frequency device includes: a substrate having an aperture; a first dielectric layer that is formed from a material having etching selectivity in relation to a material of the substrate and is provided on the substrate to cover the aperture; a second dielectric layer on the first dielectric layer; and a high frequency element provided in a position opposed to the aperture on the second dielectric layer.

Abstract: A thin-film capacitor and a method for making the thin-film capacitor having a structure that can prevent vertical stress acting on outer connecting terminals, such as bumps, from concentrating on electrode layers, and capable of easily increasing the equivalent series resistance to a desired value. The thin-film capacitor includes a substrate, a capacitor unit disposed above the substrate and composed of at least one dielectric thin film and two electrode layers, a protective layer covering at least part of the capacitor unit, a lead conductor electrically connected to one of the electrode layers of the capacitor unit, and a bump disposed above the lead conductor. The lead conductor includes a connecting part disposed in an opening in the protective layer and electrically connected to one of the electrode layers of the capacitor unit, and a wiring part extending over the protective layer. The bump is disposed above the wiring part.

Abstract: A method with which Quantum Batteries (super capacitors) can be produced from materials which consist of chemically highly dipolar crystals in the form of nanometer-sized grains or layers that are embedded in electrically insulating matrix material or intermediate layers, and are applied to a compound foil or fixed flat base. The materials are assembled so as to form wound capacitors or flat capacitors which are able to store electrical energy in a range of up to 15 MJ/kg or more without any loss due to the effect of virtual photon resonance.

Abstract: A conductive composition comprises a ? conjugated conductive polymer, a polyanion, and a hydroxy group-containing aromatic compound containing two or more hydroxy groups. An antistatic coating material comprises the conductive composition and a solvent. An antistatic coating is produced by applying the antistatic coating material. A capacitor comprises an anode composed of a porous valve metal body; a dielectric layer formed by oxidizing a surface of the anode; and a cathode formed on the dielectric layer, wherein the cathode has a solid electrolyte layer comprising the conductive composition.

Abstract: A method of manufacturing a capacitor-embedded PCB is disclosed. The method may include fabricating a capacitor substrate having at least one inner electrode formed on one side of a dielectric layer; aligning a semi-cured insulation layer with one side of a core layer, and aligning the capacitor substrate with the semi-cured insulation layer such that the inner electrode faces the semi-cured insulation layer; and collectively stacking the core layer, the semi-cured insulation layer, and the capacitor substrate.

Abstract: A multi-layer ceramic capacitor comprises dielectric sheets including a first external electrode, a first internal electrode joined to the first external electrode via an interposed dielectric portion, a second external electrode joined to the first internal electrode, and a second internal electrode joined to the first internal electrode.