Abstract: A multi-layer substrate includes a ground structure, a plurality of dielectric layers on the ground structure and a plurality of conductive layers separating the plurality of dielectric layers. The conductive layers include a first conductive layer and a second conductive layer and a connection electrically coupling the first conductive layer and the second conductive layer. The first conductive layer and the ground structure are configured to define a first parasitic capacitance there between and the first conductive layer and the second conductive layer are configured to define a second, negating parasitic capacitance there between.
Type:
Application
Filed:
June 1, 2012
Publication date:
September 20, 2012
Inventors:
Thomas A. Hertel, Erich H. Soendker, Horacio Saldivar
Abstract: A multilayer ceramic capacitor includes: a ceramic element; a plurality of first and second inner electrodes formed at the interior of the ceramic element and including capacity contribution portions facing each other and capacity non-contribution portions extending from the capacity contribution portions and having one end alternately exposed from the side of the ceramic element; first and second outer electrodes formed at the side of the ceramic main body and electrically connected with the first and second inner electrodes, wherein the thickness of the capacity non-contribution portion is greater than that of the capacity contribution portion and connectivity of the capacity non-contribution portion is higher than that of the capacity contribution portion at one or more of the first and second inner electrodes.
Type:
Grant
Filed:
July 28, 2010
Date of Patent:
September 11, 2012
Assignee:
Samsung Electro-Mechanics Co., Ltd.
Inventors:
Hyea Sun Yun, Gee Lyong Kim, Doo Young Kim, Gi Woo Lee, Dong Ik Chang
Abstract: A laminated ceramic capacitor which has a dielectric ceramic with a high dielectric constant and has excellent reliability against changes in temperature and mechanical shocks, even when dielectric ceramic layers are reduced in thickness employs a dielectric ceramic containing (Ba1-xCax)yTiO3 (where 0.045?x?0.15 and 0.98?y?1.05) as its main constituent and containing Re2O3 (where Re is at least one of Gd, Dy, Ho, Yb, and Y), MgO, MnO, V2O5, and SiO2 as accessory constituents, which is represented by the general formula: 100(Ba1-xCax)yTiO3+aRe2O3+bMgO+cMnO+dV2O5+eSiO2, and satisfies each of the following conditions: 0.65?a?1.5; 0.98?y?1.05; 0.15?b?2.0; 0.4?c?1.5; 0.02?d?0.25; and 0.2?e?3.0.
Abstract: In this process of forming a dielectric thin film, when a dielectric thin film represented by Ba1?xSrxTiyO3 (0.2<x<0.6 and 0.9<y<1.1) is formed by a sol-gel method, the process from coating to baking is carried out 2 to 9 times, the thickness of the thin film formed after the initial baking is 20 nm to 80 nm, the thickness of each thin film formed after the second baking and beyond is 20 nm to less than 200 nm, each baking from the first time to the second to ninth times is carried out by heating to a prescribed temperature within the range of 500° C. to 800° C. at a heating rate of 1° C. to 50° C.
Abstract: Devices for storing energy at a high density are described. The devices include a solid dielectric that is preformed to present a high exposed area onto which an electrode is formed. The dielectric material has a high dielectric constant (high relative permittivity) and a high breakdown voltage, allowing a high voltage difference between paired electrodes to effect a high stored energy density.
Abstract: A method for forming a capacitor dielectric includes depositing a tantalum oxide layer over a substrate, performing a post-treatment on the tantalum oxide layer to provide the tantalum oxide layer with a tetragonal phase, and depositing a zirconium oxide layer over the tantalum oxide layer such that the zirconium oxide layer has a tetragonal phase.
Abstract: An enhanced toy produces repeating, decaying notes in response to applied pressure. The tone of each note is determined, based on the location at which a user applies pressure. The initial amplitude of each note is proportional to the intensity, as measured by a stress sensor. The toy periodically repeats each note, attenuating the amplitude of each successive repetition by a decay factor. The toy may alter the notes associated with each of a plurality of locations. For example, if all currently repeating notes have decayed below a predetermined threshold, the currently available set of notes may be exchanged for a new set of notes, e.g. with different tones or timbres. The stress sensors may comprise flexible capacitors within the toy. As the user applies pressure, the geometry of one or more capacitors deform, altering the measured capacitance, through which the intensity of the applied pressure is determined.
Abstract: A metallized film capacitor includes a dielectric film and two metal vapor-deposition electrodes facing each other across the dielectric film. At least one of the metal vapor-deposition electrodes is made of substantially only aluminum and magnesium. This metallized film capacitor has superior leak current characteristics and moisture resistant performances, and can be used for forming a case mold type capacitor with a small size.
Abstract: There are provided a ceramic electronic component and a method for producing the ceramic electronic component, where a ground electrode layer can be directly coated with lead-free solder without lowering reliabilities. Terminal electrode 3 is provided with a ground electrode layer 21 of Cu having been formed by firing, a solder layer 22 formed of a lead-free solder based on five elements of Sn—Ag—Cu—Ni—Ge, and a diffusion layer 23 having been formed by the diffusion of Ni between the ground electrode layer 21 and the solder layer 22. Because the diffusion layer 23 of Ni is formed between the ground electrode layer 21 and the solder layer 22, the diffusion layer 23, which functions as a barrier layer, suppresses the solder leach of Cu from the ground electrode layer 21. The diffusion layer 23 of Ni can also suppress the growth of fragile intermetallic compounds of Sn—Cu. Therefore, a decrease in the bonding strength between the ground electrode layer 21 and the solder layer 22 can be prevented.
Abstract: The capacitor material of the present invention is comprised by laminating a titanium dioxide layer and a titanate compound layer having perovskite crystals.
Type:
Grant
Filed:
January 25, 2008
Date of Patent:
August 28, 2012
Assignee:
Showa Denko K.K.
Inventors:
Akihiko Shirakawa, Ryuichi Mitsumoto, Koji Tokita
Abstract: In a laminated ceramic electronic component in which, by directly carrying out a plating process on an outer surface of a component main body, an external electrode is formed thereon, an attempt is made to improve the adhesion strength between a plated film forming the external electrode and the component main body. A brazing material containing Ti is applied to at least one portion of a surface on which external electrodes of a component main body is formed, and by baking this brazing material, a metal layer containing Ti is formed. Moreover, the external electrodes are formed by a plating process so as to coat at least the metal layer, and a heating process is then carried out so as to cause counter diffusion between the metal layer and the plated film that is to form the external electrodes.
Abstract: A multilayer ceramic capacitor is provided. In the multilayer ceramic capacitor, a plurality of first and second inner electrodes are formed inside a ceramic sintered body. Ends of the first and second inner electrodes are alternately exposed to both ends of the ceramic sintered body. First and second outer electrodes are formed on both ends of the ceramic sintered body and connected to the first and second inner electrodes. The first and second outer electrodes include a first region having a porosity in the range of 1% to 10%, and a second region having a porosity less than that of the first region.
Type:
Grant
Filed:
September 15, 2010
Date of Patent:
August 21, 2012
Assignee:
Samsung Electro-Mechanics Co., Ltd.
Inventors:
Kang Heon Hur, Sang Hoon Kwon, Doo Young Kim, Eun Sang Na, Byung Gyun Kim, Seok Joon Hwang, Kyoung Jin Jun, Hye Young Choi
Abstract: A capacitor structure includes: a first electrode configured to include a plurality of openings; a second electrode formed in each center of the openings; and a dielectric layer formed to surround the second electrode and fill the openings of the first electrode.
Abstract: A method for manufacturing a TiN/Ta2O5/TiN capacitor, including the steps of depositing, on a TiN layer, a Ta2O5 layer by a plasma enhanced atomic deposition method (PEALD), within a temperature range from 200 to 250° C., by repeating the successive steps of: depositing a tantalum layer from a precursor at a partial pressure ranging between 0.05 and 10 Pa; and applying an oxygen plasma at an oxygen pressure ranging between 1 and 2000 Pa.
Abstract: A bulk capacitor includes a first electrode formed of a metal foil and a semi-conductive porous ceramic body formed on the metal foil. A dielectric layer is formed on the porous ceramic body for example by oxidation. A conductive medium is deposited on the porous ceramic body filling the pores of the porous ceramic body and forming a second electrode. The capacitor can then be encapsulated with various layers and can include conventional electrical terminations. A method of manufacturing a bulk capacitor includes forming a conductive porous ceramic body on a first electrode formed of a metal foil, oxidizing to form a dielectric layer and filling the porous body with a conductive medium to form a second electrode. A thin semi-conductive ceramic layer can also be disposed between the metal foil and the porous ceramic body.
Type:
Grant
Filed:
September 3, 2009
Date of Patent:
August 7, 2012
Assignee:
Vishay Sprague, Inc.
Inventors:
Reuven Katraro, Nissim Cohen, Marina Kravchik-Volfson, Eli Bershadsky, John Bultitude
Abstract: A capacitor includes a ceramic capacitor body having opposite ends and comprised of a plurality of electrode layers and dielectric layers and first and second external terminals attached to the ceramic capacitor body. The internal active electrodes within the ceramic capacitor body are configured in an alternating manner. Internal electrode shields within the ceramic capacitor body are used to assist in providing resistance to arc-over. The shields may include a top internal electrode shield and an opposite bottom internal electrode shield wherein the top internal electrode shield and the opposite bottom internal electrode shield are on opposite sides of the plurality of internal active electrodes and each internal electrode shield extends inwardly to or beyond a corresponding external terminal to thereby provide shielding. Side shields are used. The capacitor provides improved resistance to arc-over, high voltage breakdown in air, and allows for small case size.
Type:
Grant
Filed:
August 11, 2008
Date of Patent:
August 7, 2012
Assignee:
Vishay Sprague, Inc.
Inventors:
John Bultitude, John Jiang, John Rogers
Abstract: This invention relates to compositions, and the use of such compositions for protective coatings, particularly of electronic devices. The invention concerns a fired-on-foil ceramic capacitors coated with a composite encapsulant and embedded in a printed wiring board.
Type:
Grant
Filed:
December 11, 2007
Date of Patent:
July 31, 2012
Assignee:
CDA Processing Limited Liability Company
Abstract: In a ceramic capacitor, first and second electrode terminals each include a bonded-to-substrate portion, a first bonded-to-electrode portion bonded to a first edge of one of first and second external electrodes, a second bonded-to-electrode portion bonded to a second edge of the one of first and second external electrodes and disposed at a distance from the first bonded-to-electrode portion in the first directions, and a connecting portion connecting the first and second bonded-to-electrode portions and the bonded-to-substrate portion. W1/W0 is about 0.3 or more, and h/L is about 0.1 or more.
Abstract: There is provided a multilayer ceramic capacitor. The multilayer ceramic capacitor includes inner electrodes and dielectric layers stacked alternately with each other. When a continuity level of each of the inner electrodes is defined as B/A where A denotes a total length of the inner electrode and B denotes a length of the inner electrode excluding pores of the inner electrode, and a section of the inner electrode, having a predetermined length from each end of the inner electrode, is defined as an outer section, a section of the inner electrode excluding the outer section is defined as an inner section, and a section of the dielectric layers from each end of the inner electrode to a corresponding surface of the multilayer ceramic capacitor is defined as an edge section, a length of the outer section is 0.1 to 0.3 times that of the edge section, and the outer section of the inner electrode has a lower continuity level than that of the inner section of the inner electrode.
Type:
Grant
Filed:
July 30, 2010
Date of Patent:
July 31, 2012
Assignee:
Samsung Electro-Mechanics Co., Ltd.
Inventors:
Soon Sam Cho, Dong Ik Chang, Doo Young Kim
Abstract: In a case-molded capacitor, an electrode of a capacitor element is connected with a busbar having an electrode terminal for external connection. The capacitor element and the busbar are placed in a metal case having an upper surface opening and are resin molded. A thermally-conductive insulator layer is provided between the capacitor element and a bottom surface of the metal case, hence providing the case-molded capacitor with a heat resistance.
Abstract: One embodiment includes an apparatus that includes an implantable device housing, a capacitor disposed in the implantable device housing, the capacitor including a dielectric comprising CaCu3Ti4O12 and BaTiO3, the dielectric insulating an anode from a cathode and pulse control electronics disposed in the implantable device housing and connected to the capacitor.
Abstract: A capacitor having at least one electrode pair being separated by a dielectric component, with the dielectric component being made of a polymer such as a norbornylene-containing polymer with a dielectric constant greater than 3 and a dissipation factor less than 0.1 where the capacitor has an operating temperature greater than 100° C. and less than 170° C.
Abstract: A capacitor device prevents capacitor failure and pixel failure by preventing the capacitor from experiencing a short circuit caused by disconnection of a bridge formed between electrodes of the capacitor and a display apparatus having the capacitor device. A display device comprises a thin film transistor, a light emitting device, and the capacitor device described above.
Abstract: A ceramic electronic component achieves a sufficient drop resistance strength even when terminal electrodes are formed with a higher density. The ceramic electronic component includes a ceramic laminate including ceramic laminates which are laminated to each other, first terminal electrodes disposed in a peripheral portion of a bottom surface of the ceramic laminate, catch pad electrodes arranged in the ceramic laminate so as to face the respective first terminal electrodes, and sets each including at least two first via hole conductors, which electrically connect the first terminal electrodes and the respective catch pad electrodes.
Abstract: A thin-film device comprises a base electrode made of a metal, a first dielectric layer, a first inner electrode, a second dielectric layer, a second inner electrode, and a third dielectric layer. Letting T1 be the thickness of the lowermost first dielectric layer in contact with the base electrode in the plurality of dielectric layers, and Tmin be the thickness of the thinnest dielectric layer in the plurality of dielectric layers excluding the first dielectric layer, T1>Tmin. Making the first dielectric layer thicker than the thinnest, dielectric layer in the other dielectric layers can increase the distance between a metal part projecting from a metal surface because of the surface roughness of the base electrode and the inner electrode mounted on the lowermost dielectric layer, thereby reducing leakage currents.
Abstract: A nickel oxide that is co-doped with a first alkali metal dopant and a second metal dopant may be used, for example, to form a dielectric material in an electronic device. The dielectric material may be used, for example, in a capacitor. The second metal dopant of the nickel oxide may be, for example, tin, antimony, indium, tungsten, iridium, scandium, gallium, vanadium, chromium, gold, yttrium, lanthanum, ruthenium, rhodium, molybdenum or niobium.
Type:
Grant
Filed:
January 22, 2008
Date of Patent:
July 3, 2012
Assignee:
Agency for Science, Technology and Research
Inventors:
Michael B. Sullivan, Jian Wei Zheng, Ping Wu
Abstract: Embodiments of an integrated passive device include a high-aspect ratio conductive line positioned on a carrier, a substrate, and a bump that secures the high-aspect ratio conductive line to the substrate.
Abstract: A dielectric ceramic with stable insulation properties even after calcination under a reducing atmosphere, as is preferred for a laminated ceramic capacitor, is a CaTiO3 composition containing Sn. It is preferable for the dielectric ceramic to contain, as its main component, (Ca1-xBaxSny)TiO3 (0?x<0.2, 0.01?y<0.2) with a solution of Sn at the B site.
Type:
Grant
Filed:
January 28, 2010
Date of Patent:
July 3, 2012
Assignee:
Murata Manufacturing Co., Ltd.
Inventors:
Megumi Morita, Shoichiro Suzuki, Toshikazu Takeda, Tomomi Koga
Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.
Type:
Application
Filed:
March 1, 2012
Publication date:
June 28, 2012
Inventors:
John D. Prymak, Chris Stolarski, Alethla Melody, Antony P. Chacko, Gregory J. Dunn
Abstract: Methods of forming an oxide are disclosed and include contacting a ruthenium-containing material with a tantalum-containing precursor and contacting the ruthenium-containing material with a vapor that includes water and optionally molecular hydrogen (H2). Articles including a first crystalline tantalum pentoxide and a second crystalline tantalum pentoxide on at least a portion of the first crystalline tantalum pentoxide, wherein the first tantalum pentoxide has a crystallographic orientation that is different than the crystallographic orientation of the second crystalline tantalum pentoxide, are also disclosed.
Abstract: An electrical multilayer component has a stack of dielectric layers and electrode layers arranged one above another. An electrically insulating stiffening element is arranged at a distance from at least one electrode layer on the same dielectric layer as the electrode layer. The stiffening element preferably has an increased flexural strength with respect to dielectric material surrounding it.
Type:
Grant
Filed:
March 15, 2010
Date of Patent:
June 19, 2012
Assignee:
Epcos AG
Inventors:
Axel Pecina, Gerald Schlauer, Gernot Feiel
Abstract: To provide a dielectric ceramics achieving a high insulation resistance even at a low applied voltage, and minimizing insulation resistance drop when the voltage is increased, and also provide a multilayer ceramic capacitor including the dielectric ceramics as a dielectric layer, and having excellent life characteristics in a high temperature load test. The dielectric ceramics has crystal grains composed mainly of barium titanate and containing vanadium, and a grain boundary phase existing between the crystal grains. The dielectric ceramics contains 0.0005 to 0.03 moles of vanadium in terms of V2O5, with respect to 1 mole of barium constituting the barium titanate. In the X-ray diffraction chart of the dielectric ceramics, the diffraction intensity of (004) plane indicating the tetragonal system of barium titanate is larger than the diffraction intensity of (400) plane indicating the cubic system of barium titanate.
Abstract: A semiconductor device and a method of fabricating the same include an electrode having a nickel layer with impurities. The electrode having a nickel layer with impurities can be a gate electrode or a capacitor electrode. The electrode having a nickel layer with impurities may include a combination of a pure nickel layer and a nickel layer with impurities.
Type:
Application
Filed:
February 23, 2012
Publication date:
June 14, 2012
Applicant:
HYNIX SEMICONDUCTOR INC.
Inventors:
Kwan-Woo DO, Kee-Jeung LEE, Deok-Sin KIL, Young-Dae KIM, Jin-Hyock KIM, Kyung-Woong PARK, Jeong-Yeop LEE
Abstract: A capacitor structure and a manufacturing method thereof. The capacitor structure includes a first conductor layer, a dielectric layer and a second conductor layer. The first conductor layer has a first metal material and a second metal material. The first metal material is formed with voids and the second metal material is filled in the voids via hot melt. Accordingly, in the first conductor layer, the second metal material is filled into the voids of the first metal material by means of hot melt to bond with the first metal material. In this case, the thermal treatment temperature can be effectively lowered and the electrical conductivity of the capacitor structure can be increased. Also, the strength of the capacitor structure is increased.
Abstract: A capacitor and a method of manufacturing the capacitor are disclosed. The capacitor may include a board, a polymer layer formed on one side of the board, a circuit pattern selectively formed over the polymer layer, and a titania nanosheet corresponding with the circuit pattern. Embodiments of the invention can provide flatness in the board, and allows the copper of the board to maintain its functionality as an electrode while increasing the adhesion to the titania nanosheet. The titania nanosheet may thus be implemented on a patterned board in a desired shape, number of layers, and thickness.
Type:
Grant
Filed:
April 2, 2008
Date of Patent:
June 12, 2012
Assignee:
Samsung Electro-Mechanics Co., Ltd.
Inventors:
Sung-Taek Lim, Yul-Kyo Chung, Woon-Chun Kim
Abstract: The present invention is directed to a microfabricated RF capacitor. The capacitor includes two signal wirebond pads configured for being connected to an electrical current source. The capacitor further includes two backbone structures which are connected to the wirebond pads and receive electrical current from the electrical current source via the wirebond pads, each backbone structure including a first backbone portion and a second backbone portion. The capacitor further includes a plurality of protrusions which are connected to the backbone portions of the backbone structures. The protrusions are spaced apart from each other and parallel to each other. Further, the protrusions are configured for distributing current received by the backbone structures and for promoting structural stability of the capacitor. The capacitor further includes a ground wall structure which may be configured for receiving ground current from a ground current source.
Type:
Grant
Filed:
August 16, 2010
Date of Patent:
June 12, 2012
Assignee:
Rockwell Collins, Inc.
Inventors:
Robert L. Palandech, Nathan P. Lower, Mark M. Mulbrook, Nathaniel P. Wyckoff
Abstract: An electrical component includes a ceramic base body that includes a surface that is partially ceramic, electrodes in the ceramic base body that have ends that form parts of the surface of the ceramic base body, and a bonding layer on the surface of the ceramic base body. The bonding layer has a composition such that, when the bonding layer is heated, the bonding layer is less adhesive to the ends of the electrodes than when not heated.
Type:
Grant
Filed:
August 3, 2005
Date of Patent:
June 5, 2012
Assignee:
EPCOS AG
Inventors:
Harald Köppel, Robert Krumphals, Axel Pecina
Abstract: A multi-layered capacitor includes three or more capacitor layers. A first layer includes a first DC-biased, tunable capacitor. A second layer, acoustically coupled to the first layer, includes a second DC-biased, tunable capacitor. A third layer, acoustically coupled to the second layer, includes a third DC-biased, tunable capacitor. Each dielectric of the first, second, and third capacitors has a resonance of about the same frequency, within 5%, and inner electrodes of the first, second, and third capacitors have a resonance of about the same frequency, within 5%. The resonance of each layer is a function of at least thickness, density, and material. The first, second, and third layers are biased to generate destructive acoustic interference, and the multi-layer capacitor is operable at frequencies greater than 0.1 GHz.
Type:
Grant
Filed:
March 20, 2009
Date of Patent:
June 5, 2012
Assignee:
Paratek Microwave, Inc.
Inventors:
Mircea Capanu, Andrew Cervin-Lawry, Marina Zelner
Abstract: A ceramic material has a perovskite structure and is represented by formula of (1?x)ABO3-xYZO3. In the formula, “x” is a real number that is greater than 0 and is less than 1 each of “A,” “B,” “Y,” and “Z” is one or more kinds selected from a plurality of metal ions M other than a Pb ion and alkali metal ions, “A” is bivalent, “B” is tetravalent, “Y” is trivalent or combination of trivalent metal ions, and “Z” is bivalent and/or trivalent metal ions, or a bivalent and/or pentavalent metal ions.
Type:
Grant
Filed:
July 6, 2010
Date of Patent:
June 5, 2012
Assignees:
Denso Corporation, The Univeristy of Tokyo
Abstract: A multilayer ceramic capacitor includes a capacitor body in which inner electrodes and dielectric layers are alternately laminated, and a length difference rate (D) of the inner electrodes is 7% or less. The length difference rate (D) is defined by D={L?1}/L×100, where L is a maximum length of the inner electrode, and l is a minimum length of the inner electrode.
Type:
Grant
Filed:
July 26, 2010
Date of Patent:
June 5, 2012
Assignee:
Samsung Electro-Mechanics Co., Ltd.
Inventors:
Hyo Jung Kim, Dong Ik Chang, Doo Young Kim, Ji Hun Jeong
Abstract: Disclosed herein is a capacitative element, including: a first electrode formed on a substrate; and a second electrode provided so as to sandwich a dielectric between the first electrode and the second electrode and so as to surround the first electrode on four sides along a surface of the substrate.
Abstract: Provided is a dielectric element comprising a dielectric thin film formed of a layer of perovskite nanosheets. The dielectric element has the advantages of inherent properties and high-level texture and structure controllability of the perovskite nanosheets, therefore realizing both a high dielectric constant and good insulating properties in a nano-region.
Type:
Grant
Filed:
December 20, 2007
Date of Patent:
May 22, 2012
Assignee:
National Institute for Materials Science
Abstract: A monolithic ceramic capacitor includes dielectric ceramic layers having a thickness of less than 1 ?m. When this thickness is t and the crystal grains of a dielectric ceramic of the layers have a mean diameter of r, a mean number N of grain boundaries satisfies 0<N?2 where N=t/r?1. The dielectric ceramic contains, as a main component, a perovskite type compound ABO3 (where A is Ba or Ba and at least one of Ca and Sr, B is Ti or Ti and at least one of Zr and Hf), and further contains Mn and V as auxiliary components. On the basis of 100 molar parts of the main component, the content of Mn is 0.05 to 0.75 molar parts, the content of V is 0.05 to 0.75 molar parts, and the total content of Mn and V is 0.10 to 0.80 molar parts.
Abstract: An organic dielectric material comprises a branched and/or hyperbranched macromolecule having delocalized electrons. Such macro-molecular organic material systems have desirable delocalized charge and optionally one or more micro-crystalline regions. Organic dielectric materials include, for example, branched polyanilines and phthalocyanines. Delocalized excitations within the macromolecular framework of the organic dielectric material may be used in various applications, such as light harvesting, nonlinear optical, quantum optical, and electronic applications, e.g., capacitors. Electrical devices may comprise such dielectric materials, including capacitors that have very high energy density, storage, and transfer. Also provided are methods of preparing such materials.
Type:
Grant
Filed:
June 27, 2008
Date of Patent:
May 15, 2012
Assignee:
The Regents of The University of Michigan
Abstract: The present invention related to a method for forming a capacitor device, comprising steps of: providing a substrate, forming a first metal layer on the substrate, forming a dielectric on the first metal layer, applying a laser-annealing to the dielectric, and forming a second metal layer on the dielectric.
Abstract: In a method for manufacturing a monolithic ceramic electronic component, when an inner conductor is formed by printing an electrically conductive paste, a smear may be generated in an opening of the inner conductor at a side of the opening near to a position from which printing is started in a printing direction. The smear may cause an unwanted contact between the inner conductor and a via conductor, which is a conductor extending through the opening and having a potential different from that of the inner conductor, and cause a short-circuit. The inner conductor is printed in such a manner that the center of each of the via conductors is deviated from the center of the opening in the direction in which the electrically conductive paste is printed. With this structure, even if the smear is generated in the opening, the probability that the inner conductor contact the via conductor and cause a short-circuit is minimized.
Abstract: In a method of manufacturing ceramic capacitor according to the present invention, a pair of interdigitated internal electrodes are arranged perpendicularly to the surface of the substrate, subsequent to which the respective end faces of this pair of internal electrodes are exposed, and a pair of external electrodes are formed at these exposed end faces. In this method of manufacturing ceramic capacitor, formation of the external electrodes on the end faces of the respective internal electrodes, with these internal electrodes being interdigitately integrally-formed and the end faces thereof being exposed, it possible to reliably and easily form the external electrodes.
Abstract: There is provided a ceramic electronic component including a ceramic sintered body, internal conductive layers, and external electrodes. Each of the external electrodes includes a first electrode layer, a conductive resin layer covering the first electrode layer, and a second electrode layer covering the conductive resin layer and having an extension length greater than the length of the first electrode layer extending from one of the side surfaces of the ceramic sintered body to the portions of the top and bottom surfaces thereof. The distance from the top or bottom surface of the ceramic sintered body to the closest layer of the internal conductive layers is greater than or equal to the length of the first electrode layer extending from one of the side surfaces of the ceramic sintered body to the portions of the top and bottom surfaces thereof.
Type:
Grant
Filed:
December 28, 2009
Date of Patent:
May 8, 2012
Assignee:
Samsung Electro-Mechanics Co., Ltd.
Inventors:
Dong Hwan Seo, Kang Heon Hur, Doo Young Kim
Abstract: Disclosed are apparatus and methodology for providing a precision laser adjustable (e.g., trimmable) thin film capacitor array. A plurality of individual capacitors are formed on a common substrate and connected together in parallel by way of fusible links. The individual capacitors are provided as laddered capacitance value capacitors such that a plurality of lower valued capacitors corresponding to the lower steps of the ladder, and lesser numbers of capacitors, including a single capacitor, for successive steps of the ladder, are provided. Precision capacitance values can be achieved by either of fusing or ablating selected of the fusible links so as to remove the selected subcomponents from the parallel connection. In-situ live-trimming of selected fusible links may be performed after placement of the capacitor array on a hosting printed circuit board.
Abstract: There is provided a dielectric ceramic composition including a base powder expressed by a composition formula of Bam(Ti1-xZrx)O3, where 0.995?m?1.010 and 0<x?0.10, and first to fifth accessory components, and a multilayer ceramic capacitor having the same. The multilayer ceramic capacitor having the dielectric ceramic composition has a high dielectric constant and superior high-temperature reliability.
Type:
Grant
Filed:
August 19, 2010
Date of Patent:
April 24, 2012
Assignee:
Samsung Electro-Mechanics Co., Ltd.
Inventors:
Sung Hyung Kang, Kang Heon Hur, Sang Hoon Kwon, Joon Yeob Cho, Sang Hyuk Kim