Particular Biasing Patents (Class 365/185.18)
Multiple pulses (e.g., ramp) (Class 365/185.19)
Reference signal (e.g., dummy cell) (Class 365/185.2)
Drive circuitry (e.g., word line driver) (Class 365/185.23)
Threshold setting (e.g., conditioning) (Class 365/185.24)
Line charging (e.g., precharge, discharge, refresh) (Class 365/185.25)
Floating electrode (e.g., source, control gate, drain) (Class 365/185.26)
Substrate bias (Class 365/185.27)
Tunnel programming (Class 365/185.28)
Erase (Class 365/185.29)
  • Semiconductor memory device
    Patent number: 8971120
    Abstract: According to one embodiment, a semiconductor memory device includes memory cells, word lines, a driver circuit, and a control circuit. The memory cells are stacked above a semiconductor substrate, and each includes a charge accumulation layer and control gate. The word lines are coupled to the control gates. The driver circuit repeats a programming operation to write data in a memory cell coupled to a selected word line. In the programming operation, a first voltage is applied to the selected word line, a second voltage to a first unselected word line, and a third voltage to a second unselected word line. The control circuit steps up the first voltage and steps down the second voltage in repeating the programming.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Adaptive initial program voltage for non-volatile memory
    Patent number: 8971128
    Abstract: When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: March 3, 2015
    Assignee: Sandisk Technologies Inc.
    Inventors: Henry Chin, Dana Lee
  • Methods of forming non-volatile memory devices including vertical NAND strings
    Patent number: 8971118
    Abstract: A NAND based non-volatile memory device can include a plurality of memory cells vertically arranged as a NAND string and a plurality of word line plates each electrically connected to a respective gate of the memory cells in the NAND string. A plurality of word line contacts can each be electrically connected to a respective word line plate, where the plurality of word line contacts are aligned to a bit line direction in the device.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Beom-jun Jin, Byung-seo Kim, Sung-Dong Kim
  • NROM device with reduced power unit
    Patent number: 8971129
    Abstract: A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local bit lines of two neighboring memory cells to a receiving unit, such as a ground supply or two sense amplifiers. Also included is an array performing the method.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 3, 2015
    Assignee: Spansion Israel Ltd
    Inventor: Eduardo Maayan
  • Low power phase change memory cell
    Patent number: 8971089
    Abstract: A memory may include two electrodes and phase change material having an amorphous reset state and a partially crystalized set state, coupled between the two electrodes. The phase change material in the set state may have a highly nonlinear current-voltage response in a subthreshold voltage region. The phase change material may be an alloy of indium, antimony, and tellurium.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 3, 2015
    Assignee: Intel Corporation
    Inventors: Elijah V. Karpov, Kuo-Wei Chang, Gianpaolo Spadini
  • Method of programming a multi-level memory device
    Patent number: 8971112
    Abstract: Method of programming a multi-level memory cell may include transferring one or more values between an auxiliary latch of the multi-level memory cell and a most significant bit (MSB) latch of the multi-level memory cell and/or between the auxiliary latch and a least significant bit (LSB) latch of the multi-level memory cell while programming the multi-level memory cell.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: March 3, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Luca Crippa, Rino Micheloni
  • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DATA PROGRAMMING METHOD
    Publication number: 20150055416
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes memory cell units, bit lines, word lines, and a controller. Each of the memory cell units includes a plurality of memory cells connected in series. Bit lines are connected respectively to the corresponding memory cell units. Each of the word lines is commonly connected to control gates of the corresponding memory cells of the memory cell units. The controller is configured to control a programming operation of data to the memory cells. The controller is configured to execute a first procedure including programming the data to the memory cell connected to the (4n?3)th (n being a natural number) bit line and the memory cell connected to the (4n?2)th bit line, and a second procedure including programming the data to the memory cell connected to the (4n?1)th bit line and the memory cell connected to the 4nth bit line.
    Type: Application
    Filed: March 6, 2014
    Publication date: February 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke UMEZAWA, Shigeru Kinoshita
  • CONTROLLER
    Publication number: 20150055415
    Abstract: According to one embodiment, CONTROLLER includes a phase comparator that receives a data strobe signal outputted from a memory in response to a read enable signal, and a delayed data strobe signal formed by applying a delay to the data strobe signal, and outputs a result of comparison between phases of two signals. The controller also includes a Duty control unit that corrects a Duty of the read enable signal outputted to the memory based upon the comparison result of the phase comparator.
    Type: Application
    Filed: November 22, 2013
    Publication date: February 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Yamamoto, Hiroshi Deguchi
  • STORAGE DEVICE AND DATA LATCH TIMING ADJUSTMENT METHOD
    Publication number: 20150058705
    Abstract: According to one embodiment, a storage device includes a storage medium, a DLL circuit, a latch circuit, and a delay amount adjustment circuit. The DLL circuit gives a predetermined amount of delay to an inputted clock signal, the latch circuit latches data outputted from the storage medium in accordance with the clock signal delayed in the DLL circuit, the delay amount adjustment circuit adjusts the delay amount that the DLL circuit is to give to the clock signal based on a latch result by the latch circuit.
    Type: Application
    Filed: November 29, 2013
    Publication date: February 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji SAKAUE, Edward Bandy SAMIGAT, Atsushi TAKAYAMA, Yutaka TANGO
  • METHOD AND APPARATUS FOR CONTROLLING OPERATION OF FLASH MEMORY
    Publication number: 20150055417
    Abstract: A method and apparatus for controlling the operation of flash memory are provided. The apparatus for controlling the operation of flash memory includes a control unit and a voltage adjustment unit. The control unit outputs a control signal adapted to change one or more of the program, erase and read voltage conditions for the flash memory to the voltage adjustment unit in response to the input of a PUF mode selection signal. The voltage adjustment unit changes the one or more of the program, erase and read voltage conditions for the flash memory in response to the input of the control signal.
    Type: Application
    Filed: July 21, 2014
    Publication date: February 26, 2015
    Inventors: Moon-Seok KIM, Sang-Kyung YOO, Sanghan LEE
  • Memory cell string based on gated-diode cell and memory array using the same
    Patent number: 8964475
    Abstract: The present invention provides a nonvolatile memory cell string and a memory array using the same. According to the present invention, a wall type semiconductor separated into twin fins and a memory cell string formed with memory cells having a gated diode structure along each fin are enabled to increase the degree of integration and basically prevent the interferences between adjacent cells. And a first semiconductor layer and a depletion region of a PN junction wrapped up by a gate electrode are enabled to remove GSL and CSL by GIDL memory operation and significantly increase the degree of integration for applying to a neuromorphic technology.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: February 24, 2015
    Assignee: Seoul National University R&DB Foundation
    Inventor: Jong-Ho Lee
  • Off-die charge pump that supplies multiple flash devices
    Patent number: 8964469
    Abstract: A system and method for storing data uses multiple flash memory dies. Each flash memory die includes multiple flash memory cells. A charge pump is adapted to supply charge at a predetermined voltage to each flash memory die of the flash memory dies, and an interface is adapted to receive instructions for controlling the charge pump.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: February 24, 2015
    Assignee: Apple Inc.
    Inventors: Michael J. Cornwell, Christopher P. Dudte
  • Non-volatile memory devices, operating methods thereof and memory systems including the same
    Patent number: 8964476
    Abstract: Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Il Shim, Jae-Hoon Jang, Donghyuk Chae, Youngho Lim, Hansoo Kim, Jaehun Jeong
  • Nonvolatile memory device and sub-block managing method thereof
    Patent number: 8964481
    Abstract: A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently. The row decoder is configured to select the memory block by a sub-block unit. The voltage generator is configured to generate an erase word line voltage to be provided to a first word line of a selected sub-block of the sub-blocks and a cut-off voltage, higher than the erase word line voltage, to be provided to a second word line of the selected sub-block during an erase operation. The control logic is configured to control the row decoder and the voltage generator to perform an erase operation on the selected sub-block.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Chu Oh, Junjin Kong
  • Secure memory which reduces degradation of data
    Patent number: 8964471
    Abstract: A method for managing a non-volatile memory may include a first phase of writing data to a first bank of a memory plane of the non-volatile memory, and then a second phase of writing the same data to a second bank of the same memory plane of the non-volatile memory in the case of success of the first writing phase.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: February 24, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • Detecting programmed word lines based on NAND string current
    Patent number: 8964480
    Abstract: A number (Nwl) of programmed word lines in a block of NAND strings is determined by measuring a reference combined current (Iref) in the block when all of the memory cells are in a conductive state. Subsequently, to determine if a word line is a programmed word line, an additional combined current (Iadd) in the block is measured with a demarcation voltage applied to the selected word line. The selected word line is determined to be programmed word lines if Idd is less than Iref by at least a margin. Nwl can be used to adjust an erase-verify test of an erase operation by making the erase-verify test relatively hard to pass when the number is relatively small and relatively easy to pass when the number is relatively large. Or, Nwl can be used to identify a next word line to program in the block.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: February 24, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Man L Mui, Yingda Dong, Chris Avila
  • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20150049551
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array includes a plurality of memory cell layers that are stacked. Each memory cell layer comprises a plurality of memory cells formed on a semiconductor layer. The plurality of memory cell layers include: a first memory cell layer where the semiconductor layer is configured of monocrystalline silicon; and a second memory cell layer where the semiconductor layer is configured of polycrystalline silicon. The control circuit, when controlling write or read of data to/from a memory cell belonging to the first memory cell layer, performs control based on a first parameter, and when controlling write or read of data to/from a memory cell belonging to the second memory cell layer, performs control based on a second parameter that differs from the first parameter.
    Type: Application
    Filed: October 23, 2013
    Publication date: February 19, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Kenji SAWAMURA
  • NON-VOLATILE MEMORY DEVICE AND OPERATION AND FABRICATING METHODS THEREOF
    Publication number: 20150049557
    Abstract: Provided is a non-volatile memory device having a zigzag body wiring. First word lines and second word lines are disposed on a substrate, arranged periodically and extended along a first direction. First inter-poly dielectric films are disposed on the substrate and respectively beneath the first word lines. Second inter-poly dielectric films are disposed on the substrate and respectively beneath the second word lines, wherein the first inter-poly dielectric films are thinner than the second inter-poly dielectric films. A floating gate is disposed between the substrate and each of the first and second inter-poly dielectric films. A tunnel oxide film is disposed between the substrate and each of the floating gates. Bit lines are disposed above the first and second word lines and extended along a second direction different from the first direction.
    Type: Application
    Filed: August 19, 2013
    Publication date: February 19, 2015
    Applicant: Phison Electronics Corp.
    Inventor: Hiroshi Watanabe
  • MEMORY SYSTEM INCLUDING A MEMORY DEVICE, AND METHODS OF OPERATING THE MEMORY SYSTEM AND THE MEMORY DEVICE
    Publication number: 20150049554
    Abstract: A method is provided for operating a memory device. The method includes counting, from among memory cells, a number of first off-cells with respect to a first reading voltage and a number of second off-cells with respect to a second reading voltage, comparing the number of first off-cells and the number of second off-cells, and determining, based on a result of the comparing, whether a programming error exists in a storage region in which the memory cells are included.
    Type: Application
    Filed: August 11, 2014
    Publication date: February 19, 2015
    Inventors: HYE-JIN YIM, SANG-YONG YOON
  • DATA STORAGE DEVICE
    Publication number: 20150049552
    Abstract: A data storage device includes a nonvolatile memory device; and a controller electrically coupled with the nonvolatile memory device, and configured to control an operation of the nonvolatile memory device, wherein the controller is configured to change a frequency of an internal clock and a level of an internal voltage, according to whether data is being transmitted through a channel.
    Type: Application
    Filed: November 27, 2013
    Publication date: February 19, 2015
    Applicant: SK hynix Inc.
    Inventor: Seung Jin PARK
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20150049553
    Abstract: A semiconductor memory device includes a memory cell, a sense amplifier electrically connected to the memory cell, the sense amplifier including a node for sensing a voltage during a sense operation and a data latch electrically connected to the node and configured to hold a first voltage corresponding to a voltage of the node when a strobe signal is issued during a strobe operation, and a controller configured to raise the voltage of the node during the strobe operation before the strobe signal is issued.
    Type: Application
    Filed: February 25, 2014
    Publication date: February 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi MAEJIMA
  • 2T and flash memory array
    Patent number: 8958248
    Abstract: Flash memory arrays are described. In one embodiment, a flash memory array includes memory sectors of Two-Transistor (2T) AND memory cells. Within each of the memory sectors, a row of sector selection transistors is configured such that writing data onto a memory column within the memory sector is controlled by applying a voltage to a bit line, independent from the row of sector selection transistors. Other embodiments are also described.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: February 17, 2015
    Assignee: NXP B.V.
    Inventors: Michiel Jos van Duuren, Maurits Mario Nicolaas Storms, Erik Maria van Bussel
  • Logic-based multiple time programming memory cell compatible with generic CMOS processes
    Patent number: 8958245
    Abstract: The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: February 17, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Te-Hsun Hsu, Wei-Ren Chen, Wen-Hao Ching, Wen-Chuan Chang
  • Method and apparatus for optimizing reference voltages in a nonvolatile memory
    Patent number: 8958250
    Abstract: A system including a divider module, a read module, a counting module, and a reference voltage setting module. The divider module is configured to select a voltage range in which to adjust a reference voltage used to read memory cells of nonvolatile memory, and to divide the voltage range into a plurality of bins, where each of the bins is defined by a pair of voltages. The read module is configured to perform a plurality of read operations by applying, to the memory cells, the voltages defining the bins. The counting module is configured to generate, in each of the read operations, counts of a number of memory cells having threshold voltages in each of the bins. The reference voltage setting module is configured to adjust, based on the counts, the reference voltage to a voltage selected from one or more voltages associated with the bins.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: February 17, 2015
    Assignee: Marvell World Trade Ltd.
    Inventor: Xueshi Yang
  • Semiconductor memory device
    Patent number: 8958247
    Abstract: A semiconductor memory device includes a memory string having first and second selective transistors, each of which includes a charge storage layer and a control gate, a back gate transistor which includes a charge storage layer and a control gate, and memory cell transistors connected to each other and to the back gate transistor in series between the first and second selective transistors. In case any of the memory cell transistors is defective, the defect is indicated by storing a charge in the charge storage layer of at least one of the first and second selective transistors and the back gate transistor.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Norichika Asaoka, Masanobu Shirakawa
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20150043279
    Abstract: Provided is a semiconductor memory device including an oxide semiconductor insulated gate FET and having a capability to implement advanced performance without being affected by a variation in threshold voltage. A memory cell MC includes a memory node Nm formed at a connection point of a gate of a first transistor element T1, a source of a second transistor element T2, and one end of a capacitive element Cm, and a control node Nc formed at a connection point of a drain of the first transistor element T1 and a drain of the second transistor element T2.
    Type: Application
    Filed: February 14, 2013
    Publication date: February 12, 2015
    Inventor: Yoshimitsu Yamauchi
  • METHOD OF ESTIMATING DETERIORATION STATE OF MEMORY DEVICE AND RELATED METHOD OF WEAR LEVELING
    Publication number: 20150043282
    Abstract: A method of estimating a deterioration state of a memory device comprises reading data from selected memory cells connected to a selected wordline of a memory cell array by applying to the selected wordline a plurality of distinct read voltages having values corresponding to at least one valley of threshold voltage distributions of the selected memory cells, generating quality estimation information indicating states of the threshold voltage distributions using the data read from the selected memory cells, and determining a deterioration state of a storage area including the selected memory cells based on the generated quality estimation information.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 12, 2015
    Inventors: BEOM-KYU SHIN, UNG-HWAN KIM, JUN-JIN KONG, EUN-CHEOL KIM, DONG-MIN SHIN, MYUNG-KYU LEE
  • NON-VOLATILE STORAGE WITH TEMPERATURE COMPENSATION BASED ON NEIGHBOR STATE INFORMATION
    Publication number: 20150043281
    Abstract: Data is programmed into and read from a set of target memory cells. When reading the data, temperature compensation is provided. The temperature compensation is based on temperature information and the state of one or more neighbor memory cells. In one embodiment, when data is read from set of target memory cells, the system senses the current temperature and determines the differences in temperature between the current temperature and the temperature at the time the data was programmed. If the difference in temperature is greater than a threshold, then the process of reading the data includes providing temperature compensation based on temperature information and neighbor state information. In one alternative, the decision to provide the temperature compensation can be triggered by conditions other than a temperature differential.
    Type: Application
    Filed: October 27, 2014
    Publication date: February 12, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Gerrit Jan Hemink, Shinji Sato
  • EPROM CELL
    Publication number: 20150042381
    Abstract: The present invention relates to a register cell comprising one output node, at least two power supply nodes, and a first flash transistor and a second flash transistor, wherein the register cell is configured so that the output node can be driven by at least one of the power supply nodes as a function of the value stored in at least one of the flash transistors. The invention further relates to an FPGA comprising the register cell.
    Type: Application
    Filed: February 11, 2013
    Publication date: February 12, 2015
    Inventor: Richard Ferrant
  • Data Storage Device and Voltage Protection Method Thereof
    Publication number: 20150043280
    Abstract: A data storage device includes a flash memory, a voltage detection device, and a controller. The flash memory is arranged to store data. The voltage detection device is arranged to detect a supply voltage received by the data storage device. The controller is configured to receive write commands from a host, and perform a prohibition mode when the supply voltage is outside a predetermined range, wherein the write command is arranged to enable the controller to write the flash memory, and the controller is further configured to disable all of the write commands received from the host in the prohibition mode.
    Type: Application
    Filed: July 28, 2014
    Publication date: February 12, 2015
    Inventor: Yi-Hua Pao
  • Block level grading for reliability and yield improvement
    Patent number: 8953398
    Abstract: A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: February 10, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Dana Lee, Jianmin Huang, Mrinal Kochar, Ashish Ghai
  • Semiconductor memory device and method of operating the same
    Patent number: 8953381
    Abstract: A semiconductor memory device includes a memory cell array having memory cells coupled to a plurality of word lines and a peripheral circuit group configured to supply a pass voltage to unselected word lines among the plurality of word lines, wherein the peripheral circuit group stepwise raises the pass voltage supplied to the unselected word lines to a target level.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: February 10, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jong Soon Leem
  • Apparatuses and methods of reprogramming memory cells
    Patent number: 8953379
    Abstract: Apparatuses and methods for reprogramming memory cells are described. One or more methods for memory cell operation includes programming a number of memory cells such that each of the number of memory cells are at either a first program state or a second program state, the second program state having a first program verify voltage associated therewith; and reprogramming the number of memory cells such that at least one of the number of memory cells is reprogrammed to a third program state having a second program verify voltage associated therewith, wherein those of the number of memory cells having a threshold voltage less than the second program verify voltage represent a same data value.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Chiara Cerafogli, Agostino Macerola
  • Programming based on controller performance requirements
    Patent number: 8953374
    Abstract: Methods and solid state drives are disclosed, for example a solid state drive that is adapted to receive and transmit analog data signals representative of bit patterns of three or more levels (such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits). Programming of the solid state drive, comprising an array of non-volatile memory cells, might include adjusting the level of each memory cell being programmed in response to a desired performance level of a controller circuit.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: February 10, 2015
    Assignee: Mircon Technology, Inc.
    Inventors: Frankie F. Roohparvar, Vishal Sarin, Jung-Sheng Hoei
  • Systems, methods, and apparatus for memory cells with common source lines
    Patent number: 8953380
    Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: February 10, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Xiaojun Yu, Venkatraman Prabhakar, Igor Kouznetsov, Long Hinh, Bo Jin
  • Nonvolatile memory device and read method thereof
    Patent number: 8953376
    Abstract: According to example embodiments, a read method of a nonvolatile memory device includes Disclosed is a read method of a nonvolatile memory device which includes selecting one of a plurality of vertical strings in a nonvolatile memory device, judging a channel length between a common source line and a selected one of the plurality of vertical strings, selecting a sensing manner corresponding to the judged channel length, and performing a sensing operation according to the selected sensing manner. The plurality of vertical strings may extend in a direction perpendicular to a substrate of the nonvolatile memory device.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Wan Nam, Chiweon Yoon, Jung-Soo Kim
  • Method of programming non-volatile memory device and apparatuses for performing the method
    Patent number: 8953385
    Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells during a program operation, configured to supply a first negative voltage to the word line during a detrapping operation, and configured to supply a second negative voltage as a verify voltage to the word line during a program verify operation.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Hyun Joo
  • Split gate programming
    Patent number: 8953378
    Abstract: A method for programming a split gate memory cell includes performing a first programming of the split gate memory cell in a first programming cycle of the split gate memory cell; and, subsequent to the performing the first programming of the split gate memory cell, performing a second programming of the split gate memory cell in the first programming cycle, wherein the first programming is characterized as one of source-side injection (SSI) programming and channel-initiated secondary electron (CHISEL) programming, and the second programming is characterized as the other of SSI programming and CHISEL programming.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: February 10, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cheong Min Hong, Sung-Taeg Kang
  • FLASH MEMORY CELL WITH CAPACITIVE COUPLING BETWEEN A METAL FLOATING GATE AND A METAL CONTROL GATE
    Publication number: 20150036437
    Abstract: An apparatus includes a storage transistor. The storage transistor includes a floating gate configured to store electrical charge and a control gate. The floating gate is coupled to the control gate via capacitive coupling. The floating gate and the control gate are metal. The apparatus also includes an access transistor coupled to the storage transistor. A gate of the access transistor is coupled to a word line. The storage transistor and the access transistor are serially coupled between a bit line and a source line.
    Type: Application
    Filed: August 2, 2013
    Publication date: February 5, 2015
    Applicant: Qualcomm Incorporated
    Inventors: Xia Li, Bin Yang, Zhongze Wang
  • NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND METHOD OF OPERATING NONVOLATILE MEMORY DEVICE
    Publication number: 20150036435
    Abstract: A non-volatile memory device includes a non-volatile memory cell array including a plurality of word lines, a voltage generator configured to generate a first high-voltage using a supply voltage and a second high-voltage using an external voltage which is higher than the supply voltage, and a word line selection circuit configured.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 5, 2015
    Inventors: Sangchul Kang, Seokcheon Kwon, Soo-Woong Lee
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20150036429
    Abstract: A semiconductor memory device includes a memory block including memory strings formed between bit lines and a source line, wherein the bit lines and the source line are formed on a substrate, each of the memory strings includes a superordinate cell string connected between the bit line and pipe transistors formed on the substrate and a subordinate cell string connected between the source line and the pipe transistors, and an operation circuit configured to apply operation voltages to the memory strings to perform a program operation and apply different voltages to the pipe transistors of the memory strings connected to the same bit line in the memory block.
    Type: Application
    Filed: November 7, 2013
    Publication date: February 5, 2015
    Applicant: SK hynix Inc.
    Inventors: Nam Kuk KIM, Nam Jae LEE, Kwang Hee HAN, Il Chaek KIM, Sang Hyun AN
  • Memory architecture of 3D array with diode in memory string
    Patent number: 8947936
    Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: February 3, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Chun-Hsiung Hung, Shin-Jang Shen, Hang-Ting Lue
  • Integrated circuit and memory device
    Patent number: 8947947
    Abstract: An integrated circuit includes a plurality of internal circuits, an e-fuse array circuit configured to store a data used by the internal circuits, and a fuse circuit configured to store a trimming data to set the e-fuse array circuit.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: February 3, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jeongsu Jeong, Jeongtae Hwang, Igsoo Kwon, Yeonuk Kim
  • High-performance one-transistor floating-body DRAM cell device
    Patent number: 8947932
    Abstract: Provided is a one-transistor (1T) floating-body DRAM cell device including a substrate; a gate stack which is formed on the substrate; a control electrode which is disposed on the substrate and of which some or entire portion is surrounded by the gate stack; a semiconductor layer which is formed on the gate stack; a source and a drain which are formed in the surface of the semiconductor layer and of which lower surfaces are not in contact with the gate stack; a gate insulating layer which is formed on the semiconductor layer; and a gate electrode which is formed on the gate insulating layer, wherein the remaining portion of the semiconductor layer excluding the source and the drain is configured as a floating body. The miniaturization characteristic and performance of a MOS-based DRAM cell device can be improved, and a memory capacity can be increased.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: February 3, 2015
    Assignee: SNU R&DB Foundation
    Inventor: Jong-Ho Lee
  • Techniques for providing a direct injection semiconductor memory device
    Patent number: 8947965
    Abstract: Techniques for providing a direct injection semiconductor memory device are disclosed. In one exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array, a second region coupled to a respective source line of the array, a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region, and a third region coupled to a respective carrier injection line of the array, wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: February 3, 2015
    Assignee: Micron Technology Inc.
    Inventors: Michael A. Van Buskirk, Betina Hold, Wayne Ellis
  • Semiconductor memory device for storing multivalued data
    Patent number: 8947930
    Abstract: Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: February 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noboru Shibata, Tomoharu Tanaka
  • Two-transistor non-volatile memory cell and related program and read methods
    Patent number: 8947938
    Abstract: A memory device includes an N-channel transistor and a P-channel transistor. A word line is electrically connected to a drain terminal of the N-channel transistor, and a source terminal of the P-channel transistor. A first bit line is electrically connected to a source terminal of the N-channel transistor. A second bit line is electrically connected to a drain terminal of the P-channel transistor. Gate terminals of the N-channel transistor and the P-channel transistor are electrically connected and floating.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Te-Liang Lee, Chin-Yuan Ko, Ming-Yih Wang
  • Nonvolatile memory comprising mini wells at a floating potential
    Patent number: 8940604
    Abstract: The disclosure relates to an integrated circuit comprising a nonvolatile memory on a semiconductor substrate. The integrated circuit comprises a doped isolation layer implanted in the depth of the substrate, isolated conductive trenches reaching the isolation layer and forming gates of selection transistors of memory cells, isolation trenches perpendicular to the conductive trenches and reaching the isolation layer, and conductive lines parallel to the conductive trenches, extending on the substrate and forming control gates of charge accumulation transistors of memory cells. The isolation trenches and the isolated conductive trenches delimit a plurality of mini wells in the substrate, the mini wells electrically isolated from each other, each having a floating electrical potential and comprising two memory cells.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: January 27, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francesco La Rosa
  • High endurance nonvolatile memory
    Patent number: 8942038
    Abstract: A nonvolatile memory recycles previously written blocks by reassigning binary logic states and further programming memory cells with modified parameters. Cells are written twice between erase operations, thus reducing wear, and providing higher endurance. Flags indicate whether blocks are recycled, and what parameters to use in programming and reading the blocks.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: January 27, 2015
    Assignee: SanDisk Technologies, Inc.
    Inventors: Nian Niles Yang, Abhijeet Manohar
  • System and method of programming a memory cell
    Patent number: 8942034
    Abstract: A method includes selectively creating a first breakdown condition and a second breakdown condition at a semiconductor transistor structure. The first breakdown condition is between a source overlap region of the semiconductor transistor structure and a gate of the semiconductor transistor structure. The second breakdown condition is between ad rain overlap region of the semiconductor transistor structure and the gate.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: January 27, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Bin Yang