Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: According to one embodiment, a memory controller controlling a NAND memory having D bits/cell, includes: a code encoder which generates a code word having correction capability of t symbols; a write control unit which controls writing of the code word to the NAND memory; and a code decoder which decodes the code word read from the NAND memory, wherein the write control unit dispersedly allocates 2×D pages stored in adjacent two word lines in a block of the NAND memory to 2×D/t or more code words.

Abstract: A voltage tracking circuit, which comprises a voltage generating device, a first operational amplifier, a first voltage generator, and a diode-connected device. The voltage generating device provides a fixed voltage. The first operational amplifier has a first input terminal that can receive the fixed voltage, a second input terminal that is coupled with a protected device model, and an output terminal. The first voltage generator connects to the output terminal of the first operational amplifier and to a voltage limiter that is coupled with devices under protection. The diode-connected device is in a feedback loop that connects the second input terminal of the first operational amplifier to the first voltage generator.

Abstract: Data is programmed into and read from a set of target memory cells. When reading the data, temperature compensation is provided. The temperature compensation is based on temperature information and the state of one or more neighbor memory cells. In one embodiment, when data is read from set of target memory cells, the system senses the current temperature and determines the differences in temperature between the current temperature and the temperature at the time the data was programmed. If the difference in temperature is greater than a threshold, then the process of reading the data includes providing temperature compensation based on temperature information and neighbor state information. In one alternative, the decision to provide the temperature compensation can be triggered by conditions other than a temperature differential.

Abstract: A voltage switch circuit includes plural transistors, a first control circuit and a second control circuit. The first transistor has a source terminal connected to a first voltage source and a gate terminal connected to a node b1. The second transistor has a source terminal connected to a drain terminal of the first transistor, a gate terminal receiving an enabling signal and a drain terminal connected to a node b2. The third transistor has a source terminal connected to the node b2, a gate terminal connected to a second voltage source and a drain terminal connected to an output terminal. The first control circuit is connected to the node b1. The second control circuit is connected to the output terminal.

Abstract: A method of testing a non-volatile memory device and a method of managing the non-volatile memory device are provided. The method of testing the non-volatile memory device includes calculating first and second values based on program loop frequencies corresponding to word lines of a memory area. A characteristic value of the memory area may be calculated based on the first and second values, and may be compared to a reference value to determine whether the memory area is defective.

Abstract: A semiconductor memory includes a substrate configured to include a plurality of active regions which are defined by isolation layers extending in a first direction and word lines extending in a second direction intersecting the first direction; source line contacts configured to be alternately disposed over the active regions arranged in the first and second directions and disposed over each of the active regions arranged in a third direction intersecting the first and second directions; source lines configured to extend in the third direction while being coupled to the source line contacts; contacts configured to be disposed over each of the active regions over which the source line contacts are not disposed; variable resistance elements configured to be disposed over each of the contacts; bit line contacts configured to be disposed over each of the variable resistance elements; and bit lines configured to extend in a fourth direction intersecting the first to third directions while being coupled to the bit

Abstract: An operating method of a semiconductor device includes repeating an erase loop operable to lower threshold voltages of memory cells in a selected memory block by applying an erase voltage to the selected memory block and performing an erase verification to determine whether the threshold voltages of the memory cells in the selected memory block are less than or equal to a target level, wherein an erase voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or more of the erase loops, and repeating a program loop including applying a program voltage to a selected word line to increase threshold voltages of memory cells electrically coupled to the selected word line and performing a program verification to determine whether the threshold voltages are greater than or equal to a target level, wherein a program voltage is increased by a voltage difference wherein the voltage difference is increased between successive applications of two or mo

Abstract: Techniques for sensing the threshold voltage of a memory cell during reading and verify operations by compensating for changes, including temperature-based changes, in the resistance of a bit line or other control line. A memory cell being sensed is in a block in a memory array and the block is in a group of blocks. A portion of the bit line extends between the group of blocks and a sense component and has a resistance which is based on the length/distance and the temperature. Various parameters can be varied with temperature and the group of blocks to provide the compensation, including bit line voltage, selected word line voltage, source line voltage, sense time and/or sense current or voltage.

Abstract: A nonvolatile semiconductor memory device including: a memory cell array including NAND strings; a plurality of word lines; a plurality of bit lines; a source line; and a control circuit configured to execute a write operation. The control circuit is configured to, when charging an unselected memory string prior to the write operation, execute both first and second charging operations, the first charging operation applying to the bit line connected to the unselected memory string a first voltage and rendering conductive a first select transistor to charge the unselected memory string, and the second charging operation applying to the source line connected to the unselected memory string a second voltage and rendering conductive a second select transistor to charge the unselected memory string, the first and second charging operations being executed at different timings.

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line associated with a memory cell, the signal being generated based on digital information. The method can also include, while the signal is applied to the line, determining whether a state of the memory cell is near a target state when the digital information has a first value, and determining whether the state of the memory cell has reached the target state when the digital information has a second value. Other embodiments including additional memory devices and methods are described.

Abstract: The memory cells storing a group of codewords are read to obtain respective read signals each comprising N signal components corresponding to respective symbols of a codeword. The components of each read signal are ordered according to signal level to produce an ordered read signal. Correspondingly-positioned components of the ordered read signals are then ordered according to signal level to produce ordered component sets for respective component positions in a said ordered read signal. Each ordered component set is partitioned into subsets corresponding to respective memory cell levels, wherein the subsets of the ordered component sets contain respective numbers of components dependent on predefined probabilities of occurrence of different symbol values at different positions in a said codeword whose symbols are ordered according to symbol value. The reference signal level is determined in dependence on the signal components in the subsets corresponding to that memory cell level.

Abstract: An apparatus includes a reconfigurable charge pump including charge pump cells configurable into multiple different arrangements. The apparatus includes a control device configured to select a first arrangement of the charge pump cells from the multiple different arrangements based, at least in part, on an input voltage received by the reconfigurable charge pump and requested parameters of a drive signal for a touch screen panel. The reconfigurable charge pump can boost the input voltage based, at least in part, on the first arrangement of the charge pump cells. The control device can generate the drive signal according to the requested parameters based on the boosted input voltage.

Abstract: An integrated circuit of a memory is provided. The integrated circuit comprises a first data driving circuit and a transmitting transistor. The first data driving circuit outputs a first data voltage to a first node. The transmitting transistor is coupled between the first node and a second node. When the transmitting transistor receives a bias voltage and the voltage level of the first node is a first voltage level, the transmitting transistor makes the voltage level of the second node to be set as a third voltage level, third voltage level is close to or substantially equal to the first voltage level. When the transmitting transistor receives the bias voltage and the voltage level of the first node is the second voltage level, the voltage level of the second node is independently of the voltage level of the first node.

Abstract: According to one embodiment, a semiconductor includes a memory cell, a bit line, a word line, a sense amplifier, and a control circuit. The memory cell stores n levels (where n is a natural number of two or greater). The control circuit controls potentials of the word line and the bit line. In a read of k?1 levels (k?n) stored in the memory cell, the control circuit, upon applying a given voltage to the word line, determines read data based on first data corresponding to the voltage of the bit line read at a first timing by the sense amplifier and second data corresponding to the voltage of the bit line read, by the sense amplifier, at a second timing different from the first timing.

Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a row direction and a column direction in a matrix shape; word lines which select the memory cell in the row direction; bit lines which select the memory cells in the column direction; a sense amplifier circuit which determines values stored in the memory cells based on states of the bit line; and a charge/discharge circuit which is formed in a well where the memory cell array is arranged and which charges or discharges the bit lines.

Abstract: In a non-volatile semiconductor memory device outputting a data value determined according to a majority rule by reading-out data from each memory cell for an odd number of times, an odd number of latch circuits, each of which comprises a capacitor for selectively holding a voltage of each of the data read-out from the memory cell for the odd number of times in sequence, is provided. The capacitor of each latch circuit is connected in parallel after the capacitor of each latch circuit selectively holds the voltage of each of the data read-out from the memory cell for the odd number of times in sequence, and the data value is determined by the majority rule based on a composite voltage of the capacitor of each latch circuit connected in parallel.

Abstract: Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

Abstract: A method of writing data in a non-volatile memory device includes receiving a program command and a first row address corresponding to a first word line; performing a first partial programming operation with respect to first memory cells coupled to the first word line; performing a second partial programming operation with respect to second memory cells coupled to a second word line adjacent to the first word line; performing a first verification operation by verifying the first partial programming operation; and selectively performing a first additional programming operation with respect to the first memory cells depending on a result of the first verification operation.

Abstract: Fin field effect transistor integrated circuits and methods for producing the same are provided. A fin field effect transistor integrated circuit includes a plurality of fins extending from a semiconductor substrate. Each of the plurality of fins includes a fin sidewall, and each of the plurality of fins extends to a fin height such that a trough with a trough base is defined between adjacent fins. A second dielectric is positioned within the trough, where the second dielectric directly contacts the semiconductor substrate at the trough base. The second dielectric extends to a second dielectric height less than the fin height such that protruding fin portions extend above the second dielectric. A first dielectric is positioned between the fin sidewall and the second dielectric.

Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

Abstract: An image forming apparatus has, as operation modes, a normal mode and a power-saving mode with power consumption smaller than the normal mode. The image forming apparatus includes an operation unit for receiving an instruction from a user, having an operation area to which a prescribed instruction from the user is input. The image forming apparatus further includes: a first detection unit detecting an input from the user to the operation area in the normal mode; a power control unit controlling power supply in the normal mode and the power-saving mode, and turning off power supply to the first detection unit in the power-saving mode; and a second detection unit detecting an input from the user to the operation area in the power-saving mode.

Abstract: An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.

Abstract: A memory device is described that includes a three-dimensional array of memory cells having a plurality of levels of memory cells accessed by a plurality of word lines, and a plurality of bit lines. Control circuitry is coupled to the plurality of word lines and the plurality of bit lines. The control circuitry is adapted for programming a selected memory cell in a selected level of the array and on a selected word line, by hot carrier generation assisted FN tunneling, while inhibiting disturb in unselected memory cells in unselected levels and in the selected level and on unselected word lines by self-boosting.

Abstract: Apparatus are disclosed, such as a block including a number of strings of charge storage devices, each string including a number of charge storage devices associated with a pillar, and each pillar including semiconductor material. Methods are disclosed, such as a method that includes performing a first operation on a first charge storage device associated with a pillar in the block, modifying an electrical potential of the pillar, and performing a second operation on a second charge storage device in the block. Additional apparatus and methods are described.

Abstract: In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is scrubbed according to a scheme which weights particular data that is exposed to potentially damaging voltages. Data that may cause damage to other data is moved to a location where such potential damage is reduced.

Abstract: A method is provided for driving a nonvolatile memory device, including multiple strings, where each string is formed by penetrating plate-shaped word lines stacked on a substrate. The method includes configuring the word lines of a string in multiple zones based on zone configuration information, and applying zone voltages to the zones, respectively. The zone configuration information is varied according to a mode of operation.

Abstract: Provided is a method of fabricating a nonvolatile memory device.

Abstract: An external power control method includes determining whether to apply a second external voltage to a first node according to a drop of a first external voltage; generating a flag signal according to a drop of the second external voltage when the second external voltage is applied to the first node; transferring a voltage of the first node to a second node in response to the flag signal; and discharging at least one voltage of an internal circuit connected to the second node in response to the flag signal.

Abstract: Static random access memory (SRAM) circuits are used in most digital integrated circuits to store representations of data bits. To handle multiple concurrent memory requests, an efficient dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true/data side and the false/data-complement side of the SRAM bit cell may be accessed independently. Single-ended reads allow the two independent word lines and bit lines to handle two independent read operations in a single cycle using spatial domain multiplexing. Single-ended writes are enabled by adjusting the VDD power voltage supplied to a memory cell when writes are performed such that a single word line and bit line pair can be used write either a logical “0” or logical “1” into either side of the SRAM bit cell. Thus, spatial domain multiplexing with a voltage assist allows single-ended writes to handle two independent write operations to be handled in a single cycle.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array includes a plurality of memory cell layers that are stacked. Each memory cell layer comprises a plurality of memory cells formed on a semiconductor layer. The plurality of memory cell layers include: a first memory cell layer where the semiconductor layer is configured of monocrystalline silicon; and a second memory cell layer where the semiconductor layer is configured of polycrystalline silicon. The control circuit, when controlling write or read of data to/from a memory cell belonging to the first memory cell layer, performs control based on a first parameter, and when controlling write or read of data to/from a memory cell belonging to the second memory cell layer, performs control based on a second parameter that differs from the first parameter.

Abstract: In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells.

Abstract: Certain aspects of this disclosure relate to programming an at least one flash memory cell using an at least one programming pulse with a new programming voltage having a level. The level is maintained in at least one page in a block of a flash memory controller memory, wherein the level varies as a function of a number of programming cycles applied to the at least one flash memory cell.

Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

Abstract: A semiconductor storage system includes: a difference determining circuit configured to determine a difference between the number of first state values of sample data written to a memory and the number of first state values of read data read from the memory; and a compensation value determining circuit configured to determine a read voltage level compensation value corresponding to a difference between the number of the first state values of the sample data written to the memory and the number of the first state values of the read data read from the memory.

Abstract: Techniques are disclosed herein for determining whether there is a defect that occurred as a result of programming non-volatile storage elements. Example defects include: broken word lines, control gate to substrate shorts, word line to word line shorts, double writes, etc. The memory cells may be programmed such that there will be a substantially even distribution of the memory cells in different data states. After programming, the memory cells are sensed at one or more reference levels. Two sub-groups of memory cells are strategically formed based on the sensing to enable detection of defects in a simple and efficient manner. The sub-groups may have a certain degree of separation of the data states to avoid missing a defect. The number of memory cells in one sub-group is compared with the other. If there is a significant imbalance between the two sub-groups, then a defect is detected.

Abstract: In the disclosed technology, the device identification code of a memory integrated circuit is changeable. In some cases, multiple device identification codes are stored on the memory integrated circuit, and multiple device identification code selection data are stored on the memory integrated circuit. A device identification code register can store a selected device identification code.

Abstract: A method of manufacturing a double-gate electronic memory cell is presented. The cell includes a substrate; a first gate structure, with the first gate structure having a lateral flank; a stack including several layers and of which a layer is able to store electrical charges, the stack covering the lateral flank of the first gate structure and a portion of the substrate; and a second gate structure. The second gate structure includes a first portion formed from a first gate material; a second portion formed from a second gate material, with the first gate material able to be etched selectively in relation to the second gate material and with the second gate material able to be etched selectively in relation to the first gate material; a first zone of silicidation extending over the first portion of the second gate structure; and a second zone of silicidation extending over the second portion of the second gate structure.

Abstract: Aspects of the subject technology relate to a method for reading information stored in a flash memory device. In some implementations, the method can include steps including, obtaining a first read signal of a first cell, wherein the first cell is located in a first word line and a first bit line in the flash memory device, obtaining a programming level of a second cell, wherein the second cell is located in a second word line and the first bit line, and wherein the second word line is adjacent to the first word line. In certain aspects, the method may further comprise steps for obtaining decoding information for the first cell based on the programming level of the second cell. A data storage system and article of manufacture are also provided.

Abstract: A method for enabling users to select a configuration balance for a memory device is described. The method includes receiving an indication of a memory configuration for a mass memory including two or more of memory cells. One or more memory cells of the mass memory are selected based at least in part on 1) the indication, 2) a current configuration for each of the one or more memory cells and 3) a program-erase count for each of the one or more memory cells. The method also includes determining a new configuration for each of the selected one or more memory cells. For each of the selected one or more memory cells, the configuration of the memory cell is changed from the current configuration to the determined new configuration. Apparatus and computer readable media are also disclosed.

Abstract: Some embodiments of the present disclosure relate to a memory array having a cell voltage generator configured to provide a cell voltage header to a plurality of memory cells. The cell voltage generator is connected to the memory cells by way of supply voltage line and controls a supply voltage of the memory cells. The cell voltage generator has a pull-down element coupled between a control node of the supply voltage line and a ground terminal, and a one or more pull-up elements connected in parallel between the control node and a cell voltage source. A control unit is configured to provide one or more variable valued pull-up enable signals to input nodes of the pull-up elements. The variable valued pull-up enable signals operate the pull-up elements to selectively connect the supply voltage line from the cell voltage source to provide a cell voltage header with a high slew rate.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array; a first data latch; a second data latch; a first data bus; a second data bus; a first temporary latch; a second temporary latch; and a control unit. The first and the second data latches are electrically connected to the memory cell array. The first data bus is electrically connected to the first data latch. The second data bus is electrically connected to the second data latch. The first temporary latch is electrically connected to the first data bus. The second temporary latch is electrically connected to the second data bus. The control unit is configured to write data on the first temporary latch and transfer data retained in the first temporary latch to the first data latch while writing data on the second temporary latch.

Abstract: A program method of a nonvolatile memory device according to example embodiments includes a operation (a) of detecting a level of a program voltage; and a operation (b) of providing a unselected word line voltage and a bit line precharge voltage having a variable level respectively according to the detected level of the program voltage.

Abstract: A semiconductor storage includes memory cells, a bit line, and a sense amplifier having a first transistor that controls precharging of the bit line, a second transistor that controls charging of a first node, a third transistor that controls connection of the bit line to the first node, a fourth transistor that controls connection of the first node to a second node, a fifth transistor that controls connection of the first node to a third node, and a sixth transistor that is controlled to sense a potential of the third node. The controller controls the first through sixth transistors of data to perform a read operation based on the potential of the third node.

Abstract: A method of performing a write operation on memory cells of a memory array includes applying a first plurality of pulses the write operation on the memory cells in accordance with a first predetermined ramp rate, wherein the first plurality of pulses is a predetermined number of pulses; performing a comparison of a threshold voltage of a subset of the memory cells with an interim verify voltage; and if a threshold voltage of any of the subset of memory cells fails the comparison with the interim verify voltage, continuing the write operation by applying a second plurality of pulses on the memory cells in accordance with a second predetermined ramp rate which has an increased ramp rate as compared to the first predetermined ramp rate.

Abstract: A non-volatile semiconductor memory device includes a non-volatile memory cell array and a control circuit for controlling writing-in to the memory cell array. In the stage before an erasing pulse adding in an erasing process where data of written-in memory cells is erased, the control circuit detects a programming speed when writing-in to the memory cell array, determines a programming start voltage corresponding to the programming speed for every block or every word line, stores the determined programming start voltage in the memory cell array and reads-out the programming start voltage from the memory cell array to write-in predetermined data.

Abstract: A program method of a nonvolatile memory device according to example embodiments includes a operation (a) of detecting a level of a program voltage; and a operation (b) of providing a unselected word line voltage and a bit line precharge voltage having a variable level respectively according to the detected level of the program voltage.

Abstract: A non-volatile memory circuit is formed of a P-channel MOS transistor and includes a P-channel non-volatile memory element having a floating gate and a control gate capacitively coupled together. A resistor divider has a first resistor and a second resistor for dividing a voltage difference between a power supply voltage and a ground voltage. A divided voltage output of the resistor divider is connected to the control gate. First and second switches are connected in parallel to the respective first and second resistors. The first and second switches are controlled so that a voltage of the control gate is set to a voltage of the divided voltage output which maximizes an electric field between a pinch-off point and a drain point of the P-channel MOS transistor in a writing mode.

Abstract: A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.

Abstract: A method for enabling fabrication of memory devices requiring no or minimal additional mask for fabrication having a low cost, a small footprint, and multiple-time programming capability is disclosed. Embodiments include: forming a gate stack on a substrate; forming a source extension region in the substrate on one side of the gate stack, wherein no drain extension region is formed on the other side of the gate stack; forming a tunnel oxide liner on side surfaces of the gate stack and on the substrate on each side of the gate stack; forming a charge-trapping spacer on each tunnel oxide liner; and forming a source in the substrate on the one side of the gate stack and a drain in the substrate on the other side of the gate stack.