Abstract: The inventive concept relates to a nonvolatile memory device and a method of detecting a defective word line. The method includes executing a defective word line detection operation using a program/erase voltage applied to a selected word line, wherein the defective word line detection operation determines whether or not the selected word line is defective in relation to respective word line voltage responses for the first and second segments during execution of the program/erase operation.

Abstract: A semiconductor device includes a memory cell array including a vertical channel layer, two or more selection transistors, and a plurality of memory cells formed along the vertical channel; a peripheral circuit suitable for programming the two or more selection transistors and the memory cells; and a control circuit suitable for controlling the peripheral circuit to decrease a pass voltage applied to one word line adjacent to two or more selection lines coupled to the respective selection transistors, during a program operation in which the peripheral circuit applies a program voltage to the two or more selection lines and applies the pass voltage to a plurality of word lines connected to the memory cells.

Abstract: Technologies are generally related to a connecting storage gate memory device, system, and method of manufacture.

Abstract: A device comprises a non-volatile memory array, a first selection circuit selecting whether to make a first connection path between a first bit line and a first circuit node, and selecting whether to make a second connection path between the first bit line and a second circuit node, a power supplying circuit supplying a power supply voltage to the first circuit node, the power supply voltage being, when the first connection path is selected to be made, supplied to the first bit line, and a first voltage supplying circuit supplying a first voltage to the second circuit node, the first voltage being, when the second connection path is selected to be made, supplied to the first bit line, the first voltage and the power supply voltage being higher than a ground potential, and the first voltage being higher than the power supply voltage.

Abstract: A semiconductor device includes active strips. Active strip stack selection structures electrically couple to the active strip stacks at positions between the first and second ends, and select particular ones of the active strip stacks for operations. In one embodiment, different pads coupled to opposite pads have a higher voltage, depending on the memory cell selected for read. The same active strip stack selection structure can act as a pair of side gates for opposite sides of a first active strip stack, and as one side gate for each of the adjacent active strip stacks. Each active strip stack can have: a first structure from a first set acting as first and second side gates on a first side of word lines; and a second structure and a third structure from a second set respectively acting as third and fourth side gates on the second side of word lines.

Abstract: A bias voltage generator and generating method for a reference cell are provided. The bias voltage generator includes a data read detector, a cut-off signal generator and an output stage circuit. The data read detector generates a detection signal according to transition points of a sense amplifier enable signal and a sense amplifier latch signal. The cut-off signal generator delays the detection signal a delay time to generate a cut-off signal, wherein a start-up time of the cut-off signal is decided by the detection signal and the delay time. The output stage circuit starts or stops to provide a bias-voltage providing signal according to the cut-off signal.

Abstract: A semiconductor device and a manufacturing method and an operating method for the same are provided. The semiconductor device comprises a substrate, a doped region and a stack structure. The doped region is in the substrate. The stack structure is on the substrate. The stack structure comprises a dielectric layer, an electrode layer, a solid electrolyte layer and an ion supplying layer.

Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes applying a test voltage to a word line of the rewritable non-volatile memory module to read a plurality of verification bit data. The method also includes calculating a variation of bit data identified as a first status among the verification bit data, obtaining a new read voltage value set based on the variation, and updating a threshold voltage set for the word line with the new read voltage value set. The method further includes using the updated threshold voltage set to read data from a physical page formed by memory cells connected to the word line. Accordingly, storage states of memory cells in the rewritable non-volatile memory module can be identified correctly, thereby preventing data stored in the memory cells from losing.

Abstract: A non-volatile memory apparatus and a data verification method thereof are provided. The non-volatile memory apparatus includes a plurality of memory cells, a page buffer, a write circuit, a sense amplifier, and a sense and compare circuit. The page buffer stores a plurality of buffered data and programs the plurality of memory cells according to the plurality of buffered data. The write circuit receives a program data or a rewrite-in data and writes the program data or the rewrite-in data to the page buffer. The sense amplifier senses data read from the memory cells for generating a read-out data. The sense and compare circuit reads the buffered data, and compares the read-out data and a compared buffered data to generate a rewrite-in data. The sense and compare circuit determines the rewrite-in data to be the buffered data or an inhibiting data according to the compared result.

Abstract: A semiconductor memory device includes a first data bus having a first width, and a second data bus which is separate from the first data bus and which has a second width which is different from the first width. The semiconductor memory device further includes a data transfer unit configured for transferring data from memory cells connected to a plurality of bit lines. In a first operational mode, the data transfer unit connects a first number of bit lines from among the plurality of bit lines to the first data bus to transfer the data, the first number being equal to the first width. In a second operational mode, the data transfer unit connects a second number of bit lines from among the plurality of bit lines to the second data bus to transfer the data, the second number being equal to the second width.

Abstract: According to one embodiment, a non-volatile semiconductor storage device includes a memory cell array, a row decoder, a potential generating circuit, first plural potential selection circuits, a second potential selection circuit, a first discharge circuit, and a second discharge circuit. The first plural potential selection circuits select one of output potentials of the potential generating circuit by receiving a first control signal and apply the selected output potential to a first signal line. The second potential selection circuit applies a potential of the first signal line to a second signal line connected to the row decoder by receiving a second control signal. The first discharge circuit is arranged in the first potential selection circuit. The second discharge circuit is arranged in the second potential selection circuit.

Abstract: Methods and systems are disclosed for sector-based regulation of program voltages for non-volatile memory (NVM) systems. The disclosed embodiments regulate program voltages for NVM cells based upon feedback signals generated from sector return voltages that are associated with program voltage drivers that are driving program voltages to NVM cells within selected sectors an NVM array. As such, drops in program voltage levels due to IR (current-resistance) voltage losses in program voltage distribution lines are effectively addressed. This sector-based regulation of the program voltage effectively maintains the desired program voltage at the cells being programmed regardless of the sector being accessed for programming and the number of cells being programmed. Sector return voltages can also be used along with local program voltages to provide two-step feedback regulation for the voltage generation circuitry. Test mode configurations can also be provided using test input and/or output pads.

Abstract: In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings.

Abstract: The present invention relates to semiconductor technology, and provides methods for erasing, reading and programming a flash memory. In the present invention, when an erase operation is performed on the flash memory, for a sector selected for the erase operation, its N-type well is applied with a voltage of 8V˜12V, its bit line is applied with a voltage of 4V˜6V, and its word line is applied with a voltage of ?7V˜?10V. When a read operation is performed on the flash memory, for a sector selected for the read operation, its N-type well is applied with a VCC voltage; for a flash memory cell selected for the read operation, its bit line is applied with the VCC voltage, and its source line is applied with a voltage of 0V. When a program operation is performed on the flash memory, for a flash memory cell selected for the program operation, its bit line is applied with a voltage of VCC?6.5V˜VCC?4.5V, and its bit line is applied with a voltage of VCC+6V˜VCC+9V.

Abstract: A semiconductor integrated circuit includes a transistor with a source region, a drain region, and a control gate electrode. The integrated circuit additionally includes a controller that selectively applies voltages to the control gate of the transistor. The controller may apply a first voltage that forms a permanent conductive path between the source and drain of the transistor.

Abstract: A method of operation of a non-volatile memory system includes: providing a control field effect transistor having a source electrode and a body-tie electrode; coupling a resistive storage element to the source electrode; and opening a well switch coupled to the body-tie electrode for increasing a well voltage and resetting the resistive storage element by the source electrode floating on the well voltage.

Abstract: Disclosed is a 2-transistor flash memory that includes a memory cell array, a row driver, a read/write circuit, a charge pump generating a high voltage, and control logic configured to transfer the high voltage to the row driver, the read/write circuit, and the memory cell array. If programming, the row driver and the read/write circuit apply voltages such that a control gate of a cell transistor in an unselected memory cell on a different row from a selected memory cell is floated.

Abstract: A non-volatile memory apparatus includes a memory cell array, a power supply configured to generate an operation voltage according to an operation mode and provide the memory cell array with the operation voltage, and a controller configured to provide the memory cell array with a first verification voltage and a second verification voltage in a program verification operation, detect a high speed program cell by the first verification voltage and the second verification voltage from selected memory cells to be programmed and set the high speed program cell to be in a program inhibition state, and detect a low speed program cell by the second verification voltage.

Abstract: A method of reading a nonvolatile memory device comprises applying a read voltage to a memory cell array to read selected memory cells, counting a number of the selected memory cells that have a threshold voltage higher or lower than the read voltage, and comparing the counted number with a reference value to determine a number of bits stored in the selected memory cells.

Abstract: Methods for programming memory cells and memory devices are disclosed. One such method for programming includes performing a program verify operation of a group of memory cells. A number of potential CS2 situations are detected. If the number of detected potential CS2 situations is greater than a threshold, programming compensation for a CS2 situation is used in a subsequent programming operation.

Abstract: In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block.

Abstract: A method includes storing data in a memory, which includes multiple strings of analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines and a third dimension associated with sections, such that each string is associated with a respective bit line and a respective section and includes multiple memory cells that are connected to the respective word lines. For a group of the strings, respective values of a property of the strings in the group are evaluated. Source-side voltages are calculated for the respective strings in the group, depending on the respective values of the property, and respective source-sides of the strings in the group are biased with the corresponding source-side voltages. A memory operation is performed on the strings in the group while the strings are biased with the respective source-side voltages.

Abstract: A memory repairing method for a rewritable non-volatile memory module and a memory controller and a memory storage apparatus are provided. The method includes monitoring a wear degree of the rewritable non-volatile memory module; determining whether the wear degree of the rewritable non-volatile memory module is larger than a threshold; and heating the rewritable non-volatile memory module such that the temperature of the rewritable non-volatile memory module lies in between 100° C.˜600° C. if the wear degree of the rewritable non-volatile memory module is larger than the threshold. Accordingly, deteriorated memory cells in the rewritable non-volatile memory module can be repaired, thereby preventing data loss.

Abstract: A method transfers read data from a flash memory to a controller synchronously with respect to a data strobe signal during a read data transfer period. During an initial control period of the read data transfer period, the cycle of the data strobe signal is expanded such that a pulse width of the resulting cycle-controlled data strobe signal is greater than a pulse width of the data strobe signal.

Abstract: A method for testing an integrated circuit includes, in a burn-in test mode, two steps during which gate oxides of conductive high voltage MOS transistors of the integrated circuit are subjected to a first test voltage, and blocked high voltage MOS transistors of the integrated circuit are subjected to a second test voltage. The first test voltage is set to a value higher than a high supply voltage supplied to the high voltage MOS transistors in a normal operating mode, to make the gate oxides of transistors considered as insufficiently robust break down. The second test voltage is set to a value lower than the first test voltage and which can be supported by the blocked transistors, the states of the transistors being changed between the two steps.

Abstract: A method of operating a resistive switching device includes applying a program stress to a two terminal resistive memory unit. The program stress is applied at a program voltage configured to change a state of the memory unit from a first state to a second state. The method further includes applying a verification/stabilization stress to the two terminal resistive memory unit. The verification/stabilization stress is applied at a verification/stabilization voltage. An erase stress is applied to the two terminal resistive memory unit. The erase stress is applied at an erase voltage configured to change a state of the memory unit from the second state to the first state. The verification/stabilization voltage is between the program voltage and the erase voltage.

Abstract: Some embodiments relate to apparatuses and methods associated with blocks of memory cells. The blocks of memory cells may include two or more sub-blocks of memory cells. Sub-blocks may comprise a vertical string of memory cells including a source select transistor and a drain select transistor. An apparatus may include two or more drain select lines, of which a first drain select line is coupled to a drain select transistor in a first sub-block of a first block and to a drain select transistor in a first sub-block of a second block. A second drain select line in the apparatus may be coupled to a drain select transistor in a second sub-block of the first block and to a drain select transistor in a second sub-block of the second block. Other apparatuses and methods are described.

Abstract: This disclosure concerns memory cell sensing. One or more methods include determining a data state of a first memory cell coupled to a first data line, determining a data state of a third memory cell coupled to a third data line, transferring determined data of at least one of the first and the third memory cells to a data line control unit corresponding to a second data line to which a second memory cell is coupled, the second data line being adjacent to the first data line and the third data line, and determining a data state of the second memory cell based, at least partially, on the transferred determined data.

Abstract: A method for operating a semiconductor structure is provided. The semiconductor structure includes a first conductor extending in a first direction, a second conductor extending in a second direction different from the first direction, and a dielectric layer between the first conductor and the second conductor. The method for operating the semiconductor structure comprises following steps. A current is provided to flow in the first direction in the first conductor.

Abstract: Methods and apparatus to improve flash memory system endurance using temperature based flash memory settings are described. In one embodiment, memory controller logic applies one of a first trim profile or a second trim profile to a flash memory storage device based at least partially on a comparison of a threshold temperature value and a sensed temperature of the flash memory storage device. Other embodiments are also disclosed and claimed.

Abstract: A device, a computer readable medium and a method that may include performing a shortened read attempt of multiple data memory cells that store data to provide an estimate of the data; wherein the shortened read attempt has a duration that is shorter than a duration of a full read attempt; performing a shortened read attempt of redundant memory cells that store redundant information to provide an estimate of the redundant information; wherein the estimate of the redundant information is indicative of an expected number of data memory cells that store a certain logic value; determining, based on the estimate of the data, an estimated number of data memory cells that store the certain logic value; comparing the expected number to the estimated number; and providing the estimate of the data as a read result if the expected number and the estimated number equal each other.

Abstract: A method for programming a plurality of memory cells of a nonvolatile semiconductor memory device comprises the steps of: dividing the plurality of memory cells into M number of groups (M is an integer); successively selecting each of the M number of groups; generating M number of successive overlapping pulse signals; and programming the memory cells of the M number of groups in response to the respective M number of successive overlapping pulse signals.

Abstract: Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.

Abstract: Disclosed herein is a method that includes providing a non-volatile memory device which includes a plurality of cells, a plurality of selection transistors each having a gate and each coupled to associated one of the cells, and a selection line coupled in common to the gates of the selection transistors, applying a first program voltage to the selection line, and applying a second program voltage to the selection line when at least one of the selection transistors have not been shifted to a program condition.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: According to one embodiment, a semiconductor memory device includes memory units each includes a first transistor, memory cell transistors, and a second transistor serially coupled between first and second ends. A memory cell transistor of each memory unit has its gate electrode coupled to each other. A bit line is coupled to the first ends. First and second drivers output voltage applied to selected and unselected first transistors, respectively. Third and fourth drivers output voltage applied to selected and unselected second transistors, respectively. A selector couples the gate electrode of the first transistor of each memory unit to the first or second driver, and that of the second transistor of each memory unit to the third or fourth driver.

Abstract: A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level.

Abstract: Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory devices includes initially programming a cell with a coarse programming pulse to move its threshold voltage in a large step close to the programmed state. The neighboring cells are then programmed using coarse programming. The algorithm then returns to the initially programmed cells that are then programmed with one or more fine pulses that slowly move the threshold voltage in smaller steps to the final programmed state threshold voltage.

Abstract: Provided is a programming method of a nonvolatile memory device which includes a plurality of strings each including a source select transistor, a plurality of memory cells, and a drain select transistor which are connected in series between a common source line and a bit line, The programming method includes: applying a first voltage to the common source line during a first period in which a channel of a plurality of memory cells of an unselected string is floated; and applying a second voltage increased more than the first in voltage to the common source line during a second period in which a selected memory cell is programmed, when a selected word line belongs to a word line group adjacent to the common source line.

Abstract: A nonvolatile memory apparatus includes: a memory cell area including a plurality of memory cells connected to a word line and a bit line; a program time controller configured to determine a program voltage application time for a selected word line, as the selected word line is selected in response to a program command and an address signal; and a controller configured to apply a program voltage to the selected word line according to the program voltage application time determined by the program time controller.

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying a signal to a line associated with a memory cell, the signal being generated based on digital information. The method can also include, while the signal is applied to the line, determining whether a state of the memory cell is near a target state when the digital information has a first value, and determining whether the state of the memory cell has reached the target state when the digital information has a second value. Other embodiments including additional memory devices and methods are described.

Abstract: Techniques are presented to detect word line failures (such as word line to word line shorts, control gate to substrate shorts, broken word lines, and so on) in non-volatile memory arrays. A first simultaneous read of multiple word lines is performed, followed by a second simultaneous read of the same word lines, where the read conditions of the two reads are shifted by a margin. For example, one of the read could use a standard read voltage on the word lines, while the other read could shift these levels slightly higher. The results of the two reads can then be compared on a bit line by bit line basis, XOR-ing the results to determine is the set of word lines may include any defective members.

Abstract: A non-volatile memory device incorporates a write buffer within a multi-level column decoder to enable multiple memory cells associated with a single write driver to be written in parallel. In this manner, in a non-volatile memory such as a flash memory that performs batch write operation, a group of data bits for a single I/O can be written to the memory cells at a time, thereby reducing the number of write cycles required for writing a block of program data and increasing the speed of write operation.

Abstract: A semiconductor memory device and a method of operating a semiconductor memory device includes connecting selected even bit lines to selected even cell strings, programming memory cells in the selected even cell strings by using a second program permission voltage higher than a first program permission voltage, connecting selected odd bit lines to selected odd cell strings when programming of the memory cells is finished, and programming memory cells in the selected odd cell strings by using the first program permission voltage.

Abstract: Disclosed herein are techniques for providing a programming voltage to a selected word line in a non-volatile memory array. This may be a 3D NAND, 2D NAND, or another type of memory array. The programming voltage may be quickly ramped up on the selected word line, without the need for adding a stronger charge pump to the memory device. The voltage on the selected word line may be ramped up to a target voltage during a channel pre-charge phase. The target voltage may be limited in magnitude so that program disturb does not occur. Next, during a channel boosting phase, the unselected word lines are increased to a boosting voltage. The voltage on the selected word line is also increased during the boosting phase to a second target level. Then, the voltage on the selected word line is charged up from the second target level to a program voltage.

Abstract: A non-volatile memory and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (VNEG) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than VNEG is coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array to reduce a bias applied to a non-volatile memory transistor in an unselected memory cell to reduce program disturb of data programmed in the unselected memory cell due to programming.

Abstract: In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.

Abstract: Writing data to a thermally sensitive memory device, including: receiving a physical layout of the thermally sensitive memory device; receiving the direction of airflow across the thermally sensitive memory device; selecting an address for writing data to the thermally sensitive memory device in dependence upon the physical layout of the thermally sensitive memory device and the direction of airflow across the thermally sensitive memory device; and writing data to the selected address of the thermally sensitive memory device.

Abstract: In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.

Abstract: Embodiments of the present invention provide a memory array of macro cells. Each macro cell comprises a storage element and a calibration element. The storage element and its corresponding calibration element are part of a common memory array within an integrated circuit, and therefore, are in close proximity to each other. The calibration element may store a parameter used to modify the threshold voltage of the storage element.