Abstract: A manufacturing method of a microcrystalline silicon film includes the steps of forming a first microcrystalline silicon film over an insulating film by a plasma CVD method under a first condition; and forming a second microcrystalline silicon film over the first microcrystalline silicon film under a second condition. As a source gas supplied to a treatment chamber, a deposition gas containing silicon and a gas containing hydrogen are used. In the first condition, a flow rate of hydrogen is set at a flow rate 50 to 1000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 67 to 1333 Pa inclusive. In the second condition, a flow rate of hydrogen is set at a flow rate 100 to 2000 times inclusive that of the deposition gas, and the pressure inside the treatment chamber is set 1333 to 13332 Pa inclusive.

Abstract: The graphene electronic device may include a gate oxide on a conductive substrate, the conductive substrate configured to function as a gate electrode, a pair of first metals on the gate oxide, the pair of the first metals separate from each other, a graphene channel layer extending between the first metals and on the first metals, and a source electrode and a drain electrode on both edges of the graphene channel layer.

Abstract: A thin-film transistor device manufacturing method for forming a crystalline silicon film of stable crystallinity using a visible wavelength laser includes: a process of forming a plurality of gate electrodes above a substrate; a process of forming a silicon nitride layer on the plurality of gate electrodes; a process of forming a silicon oxide layer on the silicon nitride layer; a process of forming an amorphous silicon layer on the silicon oxide layer; a process of crystallizing the amorphous silicon layer using predetermined laser light to produce a crystalline silicon layer; and a process of forming a source electrode and a drain electrode on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes. A film thickness of the silicon oxide layer, a film thickness of the silicon nitride layer, and a film thickness of the amorphous silicon layer satisfy predetermined conditional expressions.

Abstract: This invention provides a transistor with an etching stop layer and a manufacturing method thereof. The transistor structure includes a substrate, a crystalline semiconductor layer, an etching stop structure, an ohmic contact layer, a source, a drain, a gate insulating layer, and a gate. The manufacturing method is performed by patterning the ohmic contact layer and the crystalline semiconductor layer at the same time with the same mask; and patterning the ohmic contact layer and the source/drain layer at the same time with another the same mask.

Abstract: A switching element includes an active pattern including a channel portion, a source portion connected to the channel portion, and a drain portion connected to the channel portion, the source portion, a gate electrode overlapping the channel portion of the active pattern, a gate insulation layer disposed between the channel portion of the active pattern and the gate electrode, a source electrode disposed on the source portion of the active pattern to make ohmic contact with the source portion, and a drain electrode disposed on the drain portion of the active pattern to make ohmic contact with the drain portion. The drain portion and the channel portion of the active pattern include the same or substantially the same material.

Abstract: A manufacturing method of an LTPS-TFT array substrate is provided. The exemplary method comprises a step of sequentially forming a poly-silicon layer and a data-line-metal layer on a base substrate, and performing a patterning process by using a third mask to simultaneously form an active layer and source and drain electrodes, the active layer being provided on the gate insulating layer and corresponding to the gate electrode, and the source and drain electrodes being provided on the active layer.

Abstract: The present disclosure relates to the field of fabricating microelectronic devices. In at least one embodiment, the present disclosure relates to forming an isolated nanowire, wherein isolation structure adjacent the nanowire provides a substantially level surface for the formation of microelectronic structures thereon.

Abstract: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

Abstract: An array substrate having a wiring of a pad region formed without an insulating film or without an insulating film and an organic film to reduce abnormal operations due to an increase in resistance caused by a contact margin at a high temperature, and a method for manufacturing the same are provided. The array substrate includes: an insulating substrate including a pad region and a thin film transistor (TFT) formation region; a first electrode layer formed in the pad region of the substrate; and a second electrode formed on the first electrode layer in an overlapping manner.

Abstract: A method of manufacturing oxide thin film transistor and display device are provided. In the method of manufacturing an oxide thin film transistor, the method includes: forming an active layer of an oxide semiconductor on a substrate, and performing surface treatment with plasma for the active layer to permeate oxygen into the active layer.

Abstract: Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.

Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and forming a trench in the semiconductor substrate by etching the semiconductor substrate. The methods also includes forming a threshold-adjusting layer doped with a certain type of threshold-adjusting ions to adjust the threshold voltage of the transistor on the semiconductor substrate in the trench; and forming a carrier drifting layer on the threshold-adjusting layer. Further the method includes forming a gate structure on the carrier drifting layer corresponding to the trench.

Abstract: A method of fabricating a field effect transistor with a fin structure is described. At least a fin structure is formed on a substrate. A planar insulation layer covering the fin structure is formed. A trench is formed in the insulation layer and intersects the fin structure both lengthwise. The trench is disposed over portions of the fin structure, and a lengthwise direction of the trench intersects a lengthwise direction of the fin structure, and thereby an upper portion of the fin structure is exposed to the trench. The exposed upper portion of the fin structure will serve as a gate channel region. A gate structure covering the upper portion is formed within the trench. The upper portion of the fin structure may be further trimmed.

Abstract: A thin film transistor includes a gate electrode, a first insulating layer on the gate electrode, a semiconductor layer on the gate electrode and separated from the gate electrode by the first insulating layer, the semiconductor layer including a channel region corresponding to the gate electrode, a source region, and a drain region, a hydrogen diffusion barrier layer on the semiconductor layer, the hydrogen diffusion barrier layer covering the channel region and exposing the source and drain regions, and a second insulation layer on the source and drain regions and on the hydrogen diffusion barrier layer, such that the hydrogen diffusion barrier layer is between the second insulation layer and the channel region.

Abstract: One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material.

Abstract: FinFET structures and methods of formation are disclosed. Fins are formed on a bulk substrate. A crystalline insulator layer is formed on the bulk substrate with the fins sticking out of the epitaxial oxide layer. A gate is formed around the fins protruding from the crystalline insulator layer. An epitaxially grown semiconductor region is formed in the source drain region by merging the fins on the crystalline insulator layer to form a fin merging region.

Abstract: A method for growing a graphene layer on a metal foil includes placing a vessel into a chemical vapor deposition chamber, the vessel having a metal foil positioned therein. The method includes evacuating the chemical vapor deposition chamber, introducing hydrogen gas into the chamber to achieve a first pressure less than atmospheric pressure, heating the atmosphere in the chamber to anneal the metal foil, introducing methane and hydrogen into the chamber to achieve a second pressure less than atmospheric pressure.

Abstract: Thin-film transistors and techniques for forming thin-film transistors (TFT). In some embodiments, there is provided a method of forming a TFT, comprising forming a body region of the TFT comprising an organic semiconducting material, and forming a protective layer comprising an organic insulating material. Forming the protective layer comprises contacting the body region of the TFT with a solution comprising the organic insulating material. The organic insulating material is a material that phase separates with the organic semiconducting material when the solution contacts the organic semiconducting material. In other embodiments, there is provided an apparatus comprising a TFT.

Abstract: A thin-film transistor device manufacturing method and others according to the present disclosure includes: forming a plurality of gate electrodes above a substrate; forming a gate insulating layer on the plurality of gate electrodes; forming an amorphous silicon layer on the gate insulating layer; forming a buffer layer and a light absorbing layer above the amorphous silicon layer; forming a crystalline silicon layer by crystallizing the amorphous silicon layer with heat generated by heating the light absorbing layer using a red or near infrared laser beam; and forming a source electrode and a drain electrode on the crystalline silicon layer in a region that corresponds to each of the plurality of gate electrodes, and film thicknesses of the gate insulating layer, the amorphous silicon layer, the buffer layer, and the light absorbing layer satisfy predetermined expressions.

Abstract: A method of manufacturing an organic light emitting diode (OLED) display includes forming an upper electrode power source line outside of a pixel area over a substrate, forming a lower electrode in the pixel area, forming at least one layer of an organic material layer in the pixel area and areas outside of the pixel area, forming an upper electrode in the pixel area, selectively removing portions of the organic material layer that are exposed outside of the upper electrode, thereby exposing the upper electrode power source line, and coating a conductive material between the upper electrode and the upper electrode power source line in a normal pressure condition such that the conductive material overlaps the upper electrode and the upper electrode power source line, thereby forming a connection portion.

Abstract: A method for manufacturing an active device array substrate includes providing a flexible substrate having a transistor region and a transparent region; forming a gate electrode on the transistor region; sequentially forming a dielectric layer and a semiconductor layer to cover the gate electrode and the flexible substrate; removing a part of the semiconductor layer to form a channel layer above the gate electrode and removing a thickness of the dielectric layer disposed on the transparent region, such that a portion of the dielectric layer on the gate electrode has a first thickness, and another portion of the dielectric layer on the transparent region has a second thickness less than the first thickness; respectively forming a source electrode and a drain electrode on opposite sides of the channel layer; and forming a pixel electrode electrically connected to the drain electrode.

Abstract: A post-planarization recess etch process is employed in combination with a replacement gate scheme to enable formation of multi-directional wiring in gate electrode lines. After formation of disposable gate structures and a planarized dielectric layer, a trench extending between two disposable gate structures are formed by a combination of lithographic methods and an anisotropic etch. End portions of the trench overlap with the two disposable gate structures. After removal of the disposable gate structures, replacement gate structures are formed in gate cavities and the trench simultaneously. A contiguous gate level structure can be formed which include portions that extend along different horizontal directions.

Abstract: In a manufacturing process of a bottom-gate transistor including an oxide semiconductor film, dehydration or dehydrogenation through heat treatment and oxygen doping treatment are performed. A transistor including an oxide semiconductor film subjected to dehydration or dehydrogenation through heat treatment and oxygen doping treatment can be a highly reliable transistor having stable electric characteristics in which the amount of change in threshold voltage of the transistor between before and after the bias-temperature stress (BT) test can be reduced.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a local silicon-on-insulator (SOI) substrate in which a portion of a line-shaped active region is connected to a semiconductor substrate, and a remaining portion thereof is insulated from the semiconductor substrate, gate structures formed in a line shape to be substantially perpendicular to the active region on the active region insulated from the semiconductor substrate, and to surround a side and an upper surface of the active region, and having a stacking structure of a gate insulating layer, a liner conductive layer, a gate conductive layer, and a hard mask layer, a source region formed in the active region connected to the semiconductor substrate, and a drain region formed in the active region insulated from the semiconductor substrate between the gate structures.

Abstract: A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.

Abstract: A method of manufacturing an integrated circuit (IC) for driving a flexible display includes depositing a pattern of spatially non-repetitive features in a first layer on a flexible substrate, said pattern of spatially non-repetitive features not substantially regularly repeating in both of two orthogonal directions (x,y) in the plane of the substrate; depositing a pattern of spatially repetitive features in a second layer on said first layer; aligning said second layer and said first layer so as to allow electrical coupling between said non-repetitive features and said repetitive features, wherein distortion compensation is applied during deposition of said repetitive features to enable said alignment.

Abstract: A p channel TFT of a driving circuit has a single drain structure and its n channel TFT, an LDD structure. A pixel TFT has the LDD structure. A pixel electrode disposed in a pixel unit is connected to the pixel TFT through a hole bored in at least a protective insulation film formed of an inorganic insulating material and formed above a gate electrode of the pixel TFT, and in an inter-layer insulation film disposed on the insulation film in close contact therewith. These process steps use 6 to 8 photo-masks.

Abstract: Methods for processing an amorphous silicon thin film sample into a polycrystalline silicon thin film are disclosed. In one preferred arrangement, a method includes the steps of generating a sequence of excimer laser pulses, controllably modulating each excimer laser pulse in the sequence to a predetermined fluence, masking portions of each fluence controlled laser pulse in the sequence with a two dimensional pattern of slits to generate a sequence of fluence controlled pulses of line patterned beamlets, irradiating an amorphous silicon thin film sample with the sequence of fluence controlled slit patterned beamlets to effect melting of portions thereof, and controllably sequentially translating a relative position of the sample with respect to each of the fluence controlled pulse of slit patterned beamlets to thereby process the amorphous silicon thin film sample into a single or polycrystalline silicon thin film.

Abstract: Methods of forming and resulting devices are described that include graphene devices on boron nitride. Selected methods of forming and resulting devices include graphene field effect transistors (GFETs) including boron nitride.

Abstract: A transistor, a display device, and associated methods, the transistor including a substrate; an active layer pattern disposed on the substrate, the active layer pattern including silicon and graphene; a gate insulating layer disposed on the active layer pattern; a gate electrode disposed on the gate insulating layer; an insulating interlayer covering the active layer pattern and the gate electrode; and a source electrode and a drain electrode in contact with the active layer pattern.

Abstract: A TFT array substrate has an organic insulating film formed of a photosensitive organic resin material. A common electrode and a lead-out wiring are formed on the organic insulating film, and a pixel electrode is formed above the common electrode with an interlayer insulating film provided between them. The pixel electrode is connected to the lead-out wiring through a contact hole formed in the interlayer insulating film. The lead-out wiring and the common electrode are connected to a drain electrode and a common wiring, respectively, through contact holes formed in the organic insulating film. A metal cap film is provided on each of the lead-out wiring and the common electrode in the contact holes formed in the organic insulating film.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stacked structure on a silicic substrate; depositing a Nickel-based metal layer on the substrate and the gate stacked structure; performing a first annealing so that the silicon in the substrate reacts with the Nickel-based metal layer to form a Ni-rich phase of metal silicide; performing an ion implantation by implanting doping ions into the Ni-rich phase of metal silicide; performing a second annealing so that the Ni-rich phase of metal to silicide is transformed into a Nickel-based metal silicide source/drain, and meanwhile, forming a segregation region of the doping ions at an interface between the Nickel-based metal silicide source/drain and the substrate.

Abstract: A method for making a semiconductor device is provided which includes (a) providing a layer stack comprising a semiconductor layer (211) and a dielectric layer (209) disposed between the substrate and the semiconductor layer, (b) creating a trench (210) which extends through the semiconductor layer and which exposes a portion of the dielectric layer, the trench having a sidewall, (c) creating a spacer structure (221) which comprises a first material and which is adjacent to the sidewall of the trench, and (d) forming a stressor layer (223) which comprises a second material and which is disposed on the bottom of the trench.

Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

Abstract: There is provided a method of manufacturing a thin-film device, the method including forming a first substrate on a supporting base by a coating method, the first substrate being formed by using a resin material; forming a second substrate on the first substrate by using any one of a thermosetting resin and energy ray-curable resin; forming an active element on the second substrate; and removing the supporting base from the first substrate. The resin material used to form the first substrate has a glass transition temperature of at least 180° C.

Abstract: Disclosed are a thin film transistor and a method of forming the thin film transistor, wherein the thin film transistor includes a gate electrode, an oxide semiconductor pattern, a first gate insulating layer pattern interposed between the gate electrode and the oxide semiconductor pattern, wherein the first gate insulating layer pattern has an island shape or has two portions of different thicknesses from each other, a source electrode and a drain electrode electrically connected to the oxide semiconductor pattern, wherein the source electrode and the drain electrode are separated from each other, and a first insulating layer pattern placed between the source electrode and drain electrode and the oxide semiconductor pattern, wherein the first insulating layer pattern partially contacts the source electrode and drain electrode and the first gate insulating layer pattern, and wherein the first insulating layer is enclosed by an outer portion.

Abstract: A method for fabricating a field effect transistor with fin structure includes the following sequences. First, a substrate is provided and at least a fin structure is formed on the substrate. Then, an etching process is performed to round at least an upper edge in the fin structure. Finally, a gate covering the fin structure is formed.

Abstract: An organic thin film transistor is disclosed, including a substrate formed of an organic insulating layer, a first layer deposited on the substrate using a plating technique to be used for forming a source electrode and a drain electrode, a second layer of a metal material deposited covering the first layer using a further plating technique to be used for forming the source electrode and the drain electrode with the metal material capable of forming an ohmic contact with an organic semiconductor material lower than the first layer, and an organic semiconductor layer over a region between the source electrode and the drain electrode, which are each formed with the first layer and the second layer. Also disclosed is an electric device provided with the organic thin film transistor.

Abstract: The stability of steps of processing a wiring formed using copper or the like is increased. The concentration of impurities in a semiconductor film is reduced. Electrical characteristics of a semiconductor device are improved. A semiconductor device includes a semiconductor film, a pair of first protective films in contact with the semiconductor film, a pair of conductive films containing copper or the like in contact with the pair of first protective films, a pair of second protective films in contact with the pair of conductive films on the side opposite the pair of first protective films, a gate insulating film in contact with the semiconductor film, and a gate electrode overlapping with the semiconductor film with the gate insulating film therebetween. In a cross section, side surfaces of the pair of second protective films are located on the outer side of side surfaces of the pair of conductive films.

Abstract: An etchant composition includes about 25 percent by weight to about 35 percent by weight of phosphoric acid, about 3 percent by weight to about 9 percent by weight of nitric acid, about 10 percent by weight to about 20 percent by weight of acetic acid, about 5 percent by weight to about 10 percent by weight of a nitrate, about 6 percent by weight to about 15 percent by weight of a sulfonic acid, about 1 percent by weight to about 5 percent by weight of an amine compound including a carboxyl group, about 0.1 percent by weight to about 1 percent by weight of a water-soluble amino acid, about 0.01 percent by weight to about 1 percent by weight of an azole compound, and water.

Abstract: An array for an in-plane switching (IPS) mode liquid crystal display device includes a gate line formed on a substrate to extend in a first direction, a common line formed on the substrate to extend in the first direction, a data line formed to extend in a second direction, a thin film transistor formed at an intersection between the gate line and the data line, wherein the thin film transistor includes a gate line, a gate insulating layer, an active layer, a source electrode, and a drain electrode, a passivation film formed on the substrate including the thin film transistor, a pixel electrode formed on the passivation film located on a pixel region defined by the gate line and the data line, the pixel electrode being electrically connected to the drain electrode, a common electrode formed on the passivation film, and a common electrode connection line connected to the common electrode and the common line, wherein the common electrode connection line overlaps with the common line and the drain electrode.

Abstract: A semiconductor device including a low-concentration impurity region formed on the drain side of an n-type MIS transistor, in a non-self-aligned manner with respect to an end portion of the gate electrode. A high-concentration impurity region is placed with a specific offset from the gate electrode and a sidewall insulating film. The semiconductor device enables the drain breakdown voltage to be sufficient and the on-resistance to decrease. A silicide layer is also formed on the surface of the gate electrode, thereby achieving gate resistance reduction and high frequency characteristics improvement.

Abstract: A method for fabricating a pixel structure includes the following steps. A patterned semiconductor layer, an insulation layer, and a patterned metal layer are formed on a substrate sequentially. A first inter-layer dielectric (ILD) layer is formed to cover the patterned metal layer. A low temperature annealing process is performed after forming the first ILD layer. A hydrogen plasma treatment process is performed after the low temperature annealing process. A second ILD layer is formed to cover the first ILD layer after the hydrogen plasma treatment process. A third ILD layer is formed to cover the second ILD layer. A source electrode and a drain electrode are formed on the third ILD layer. A passivation layer is formed on the source electrode and the drain electrode. A pixel electrode is formed on the passivation layer. A pixel structure manufactured by the above-mentioned method is also provided.

Abstract: Merged active devices on a common substrate are presented. Methods for operating and fabricating such merged active devices are also presented.

Abstract: A transistor includes a buffer layer, a channel layer over the buffer layer, a barrier layer over the channel layer, a source electrode electrically connected to the channel layer, a drain electrode electrically connected to the channel layer, a gate electrode on the barrier layer between the source electrode and the drain electrode, a backside metal layer, a substrate between a first portion of the buffer layer and the backside metal layer; and a dielectric between a second portion of the buffer layer and the backside metal layer.

Abstract: A semiconductor device having a well, a p well implant bounded at least in part within a substrate by the well, a conductive layer disposed on the substrate, a high voltage n? (HVN?) doped well implanted in the p well implant, a high voltage p doped (HVPD) well implanted in the p well implant, and a drain n? well and a source n? well disposed in the HVN? doped well and HVPD well, respectively, is provided. A method of fabricating the semiconductor device is also provided. In certain embodiments, the method of fabricating the semiconductor device is characterized by implanting the HVN? ions at a first tilt angle and/or implanting the HVPD ions at a second tilt angle.

Abstract: A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices.

Abstract: A finFET and method of fabrication are disclosed. A sacrificial layer is formed on a bulk semiconductor substrate. A top semiconductor layer (such as silicon) is disposed on the sacrificial layer. The bulk semiconductor substrate is recessed in the area adjacent to the transistor gate and a stressor layer is formed in the recessed area. The sacrificial layer is selectively removed and replaced with an insulator, such as a flowable oxide. The insulator provides isolation between the transistor channel and the bulk substrate without the use of dopants.

Abstract: After formation of raised source and drain regions, a conformal dielectric material liner is deposited within recessed regions formed by removal of shallow trench isolation structures and underlying portions of a buried insulator layer in a semiconductor-on-insulator (SOI) substrate. A dielectric material that is different from the material of the conformal dielectric material liner is subsequently deposited and planarized to form a planarized dielectric material layer. The planarized dielectric material layer is recessed selective to the conformal dielectric material liner to form dielectric fill portions that fill the recessed regions. Horizontal portions of the conformal dielectric material liner are removed by an anisotropic etch, while remaining portions of the conformal dielectric material liner form an outer gate spacer. At least one contact-level dielectric layer is deposited. Contact via structures electrically isolated from a handle substrate can be formed within the contact via holes.

Abstract: A silicon-on-insulator (SOI) substrate structure and method of fabrication including a single crystal silicon substrate, a layer of single crystal rare earth oxide formed on the substrate, a layer of engineered single crystal silicon formed on the layer of single crystal rare earth oxide, and a single crystal insulator layer of IIIOxNy formed on the engineered single crystal silicon layer. In some embodiments the III material in the insulator layer includes more than on III material. In a preferred embodiment the single crystal rare earth oxide includes Gd2O3 and the single crystal insulator layer of IIIOxNy includes one of AlOxNy and AlGaOxNy.