Abstract: Transistor devices having a self-aligned gate structure on transparent substrates and techniques for fabrication thereof are provided. In one aspect, a method of fabricating a transistor device includes the following steps. A channel material is formed on a transparent substrate. Source and drain electrodes are formed in contact with the channel material. A dielectric layer is deposited on the channel material. A photoresist is deposited on the dielectric layer and developed using UV light exposure through the transparent substrate. A gate metal(s) is deposited on the exposed portions of the dielectric layer and the undeveloped portions of the photoresist. The undeveloped portions of the photoresist are removed along with portions of the gate metal over the source and drain regions to form a gate of the device on the dielectric layer over the channel material which is self-aligned to the source and drain electrodes.

Abstract: A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described.

Abstract: A device and method for fabricating a nanowire include patterning a first set of structures on a substrate. A dummy structure is formed over portions of the substrate and the first set of structures. Exposed portions of the substrate are etched to provide an unetched raised portion. First spacers are formed about a periphery of the dummy structure and the unetched raised portion. The substrate is etched to form controlled undercut etched portions around a portion of the substrate below the dummy structure. Second spacers are formed in the controlled undercut etched portions. Source/drain regions are formed with interlayer dielectic regions formed thereon. The dummy structure is removed. The substrate is etched to release the first set of structures. Gate structures are formed including a top gate formed above the first set of structures and a bottom gate formed below the first set of structures to provide a nanowire.

Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, which comprises: forming a plurality of fins on a substrate, which extend along a first direction and have rhombus-like cross-sections; forming a gate stack structure on each fin, which traverses the plurality of fins and extends along a second direction; wherein a portion in each fin that is under the gate stack structure forms a channel region of the device, and portions in each fin that are at both sides of the gate stack structure along the first direction form source and drain regions. The semiconductor device and its manufacturing method according to the present invention use rhombus-like fins to improve the gate control capability to effectively suppress the short channel effect, moreover, an epitaxial quantum well is used therein to better limit the carriers, thus improving the device drive capability.

Abstract: An embodiment of the invention relates to a TFT-LCD array substrate comprising a substrate, a gate line and a data line formed on the substrate, a pixel electrode and a thin film transistor formed in a pixel region defined by the gate line and the data line, wherein the thin film transistor comprises a gate electrode, a source electrode, and a transparent drain electrode, and the transparent drain electrode is electrically connected with the pixel electrode.

Abstract: In one aspect, a method of fabricating an electronic device includes the following steps. An alternating series of device and sacrificial layers are formed in a stack on an SOI wafer. Nanowire bars are etched into the device/sacrificial layers such that each of the device layers in a first portion of the stack and each of the device layers in a second portion of the stack has a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region. The sacrificial layers are removed from between the nanowire bars. A conformal gate dielectric layer is selectively formed surrounding the nanowire channels in the first portion of the stack which serve as a channel region of a nanomesh FET transistor. Gates are formed surrounding the nanowire channels in the first and second portions of the stack.

Abstract: A static random access memory (SRAM) includes: a first carbon nanotube (CNT) inverter, a second CNT inverter, a first switching transistor, and a second switching transistor. The first CNT inverter includes at least a first CNT transistor. The second CNT inverter is connected to the first CNT inverter and includes at least one second CNT transistor. The first switching transistor is connected to the first CNT inverter. The second switching transistor is connected to the second CNT inverter.

Abstract: An integrated circuit includes a graphene layer, the graphene layer comprising a region of undoped graphene, the undoped graphene comprising a channel of a transistor, and a region of doped graphene, the doped graphene comprising a contact of the transistor; and a gate of the transistor, the gate comprising a carbon nanotube film. A method of fabricating an integrated circuit comprising graphene and carbon nanotubes, includes forming a graphene layer; doping a portion of the graphene layer, resulting in doped graphene and undoped graphene; forming a carbon nanotube film; and etching the carbon nanotube film to form a gate of a transistor, wherein the transistor further comprises a channel comprising the undoped graphene and a contact comprising the doped graphene. A transistor includes a gate, the gate comprising a carbon nanotube film; a channel, the channel comprising undoped graphene; and a contact, the contact comprising doped graphene.

Abstract: A system for displaying images is provided. The system includes an emissive display device including a plurality of pixel elements arranged in an array. Each pixel element includes a first substrate and a second substrate disposed thereunder, wherein the first substrate includes at least three subpixel regions. An organic light-emitting device is disposed between the first and second substrates and on the second substrate. At least one patterned polarizer film is disposed between the first and second substrates to be correspondingly located at one of the subpixel regions. At least one retarder film is disposed between the first and second substrates and affixed to the patterned polarizer film.

Abstract: The present invention discloses a TFT array substrate and a manufacturing method thereof and a liquid crystal display device, which is aiming at lowering the resistance value of a common electrode and not diminishing the aperture ratio of pixels on the premise that the manufacturing cost is not additionally increased. The TFT array substrate includes: a substrate, a common electrode layer arranged on the substrate, a first insulating layer arranged on the common electrode layer and a plurality of pixel electrodes arranged in an array on the first insulating layer, wherein via holes penetrating through the first insulating layer are formed between adjacent pixels in some of a plurality of pixels, and common electrode lines are grown between rows and/or columns of pixels in some of the plurality of pixels, and in parallel with the common electrode layer below the first insulating layer through the via holes.

Abstract: A thin-film transistor (TFT) substrate includes a flexible substrate. A first barrier layer is formed on the flexible substrate. The first barrier layer includes a first silicon oxide layer and a first silicon nitride layer. A second barrier layer is formed on the first barrier layer. The second barrier layer includes a second silicon oxide layer and a second silicon nitride layer. A TFT layer is formed on the second barrier layer. The second silicon oxide layer is disposed adjacent to the TFT layer.

Abstract: Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.

Abstract: Example embodiments relate to a method of forming a core-shell structure. According to a method, a region in which the core-shell structure will be formed is defined on a substrate, and a core and a shell layer may be sequentially stacked in the defined region. A first shell layer may further be formed between the substrate and the core. When the core and the shell layer are sequentially stacked in the core-shell region, the method may further include forming a groove on the substrate, forming the first shell layer covering surfaces of the groove, forming the core in the groove of which surfaces are covered by the first shell layer, and forming a second shell layer covering the core.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a fin in an upper surface of a semiconductor substrate to extend in a first direction, forming a mask film, making a plurality of first trenches in the mask film to extend in a second direction to reach the fin, filling sidewall members into the first trenches, making a second trench by removing the mask film from a portion of a space between the sidewall members, forming a gate insulating film and a gate electrode on a surface of a first portion of the fin disposed inside the second trench, making a third trench by removing the mask film from the remaining space between the sidewall members, and causing a second portion of the fin disposed inside the third trench to become a conductor.

Abstract: An array substrate for a display device includes an insulation substrate, a gate line formed on the insulation substrate, a data line crossing the gate line to define a pixel area, a thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode, a passivation layer covering the gate line, the data line and the thin film transistor and including a drain contact hole to expose the drain electrode, and a pixel electrode formed on the pixel area and being connected to the drain contact hole through the drain contact hole. Each of the data line, the source electrode and the drain electrode includes a lower layer having copper and an upper layer covering upper and side surfaces of the lower layer, and the upper layer is thinner than the lower layer.

Abstract: Embodiments of a manufacturing process for recessed gate devices on silicon-on-insulator (SOI) substrate with self-aligned lateral isolation are described. This allows the creation of true in-pitch recessed gate devices without requiring an extra isolation dimension. A lateral isolation trench is formed between pairs of recessed gate devices by etching the silicon-on-insulator area down to a buried oxide layer on which the silicon-on-insulator layer is formed. The position of the trench is self-aligned and defined by the gate width and the dimension of spacers disposed on either side of the gate. The isolation trench is filled with a dielectric material and then etched back to the middle of the SOI body and the remaining volume is filled with a doped conductive material. The doped conductor is subject to a thermal cycle to create source and drain regions of the device through out-diffusion of the doped material.

Abstract: One object is to provide a method for manufacturing a display device in which shift of the threshold voltage of a thin film transistor including an oxide semiconductor layer can be suppressed even when ultraviolet light irradiation is performed in the process for manufacturing the display device. In the method for manufacturing a display device, ultraviolet light irradiation is performed at least once, a thin film transistor including an oxide semiconductor layer is used for a switching element, and heat treatment for repairing damage to the oxide semiconductor layer caused by the ultraviolet light irradiation is performed after all the steps of ultraviolet light irradiation are completed.

Abstract: An aspect of this invention is a method for fabricating an extremely thin semiconductor-on-insulator (ETSOI) field-effect transistor (FET) having an epitaxial source and drain. The method includes providing an ETSOI substrate; forming at least one isolation structure on the ETSOI substrate; forming a gate on the ETSOI substrate; forming a spacer-on the ETSOI substrate; and using an epitaxial growth process to provide a raised source/drain structure having a non-uniform concentration of carbon along a vertical axis.

Abstract: A thin film transistor (TFT) structure includes a first metal layer. The first metal layer is configured with an insulating layer, a surface of the insulating layer corresponding to an area above the first metal layer is configured with an active layer made of an indium gallium zinc oxide (IGZO), a second metal layer is formed on a surface of the active layer, the second metal layer is configured with a gap on an upper surface of the active layer, and a groove is formed at the upper surface of the active layer corresponding to an area of the gap.

Abstract: As stated above, methods of forming a source/drain contact for a transistor are disclosed. In one embodiment, a transistor is formed on a semiconductor-on-insulator (SOI) substrate, which includes a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate. This forming can include forming a gate and a source/drain region. A hardmask can then be formed over the transistor and a self-assembling (DSA) polymer can be directed to cover a portion of the source/drain region. A set of trenches can be formed through the hardmask and into the source/drain region using the DSA polymer as a mask. Then the polymer and the hardmask can be stripped, leaving the trenched source/drain region.

Abstract: An aspect of this invention is a method for fabricating an extremely thin semiconductor-on-insulator (ETSOI) field-effect transistor (FET) having an epitaxial source and drain. The method includes providing an ETSOI substrate; forming at least one isolation structure on the ETSOI substrate; forming a gate on the ETSOI substrate; forming a spacer on the ETSOI substrate; and using an epitaxial growth process to provide a raised source/drain structure having a non-uniform concentration of carbon along a vertical axis.

Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.

Abstract: The reliability of a semiconductor device including a MOSFET formed over an SOI substrate is improved. A manufacturing method of the semiconductor device is simplified. A semiconductor device with n-channel MOSFETsQn formed over an SOI substrate SB includes an n+-type semiconductor region formed as a diffusion layer over an upper surface of a support substrate under a BOX film, and a contact plug CT2 electrically coupled to the n+-type semiconductor region and penetrating an element isolation region, which can control the potential of the support substrate. At a plane of the SOI substrate SB, the n-channel MOSFETsQn each extend in a first direction, and are arranged between the contact plugs CT2 formed adjacent to each other in the first direction.

Abstract: The present disclosure relates to the field of microelectronic transistor fabrication and, more particularly, to forming a graphene layer as a channel layer for a microelectronic transistor.

Abstract: It is an object to form a high quality gate insulating film which is dense and has a strong insulation resistance property, and to propose a high reliable organic transistor in which a tunnel leakage current is little. One mode of the organic transistor of the present invention has a step of forming the gate insulating film by forming the conductive layer which becomes the gate electrode activating oxygen (or gas including oxygen) or nitrogen (or gas including nitrogen) or the like using dense plasma in which density of electron is 1011 cm?3 or more, and electron temperature is a range of 0.2 eV to 2.0 eV with plasma activation, and reacting directly with a portion of the conductive layer which becomes the gate electrode to be insulated.

Abstract: Provided is a method of producing a light-emitting apparatus having a field effect transistor for driving an organic EL device, the field effect transistor including an oxide semiconductor containing at least one element selected from In and Zn, the method including the steps of: forming a field effect transistor on a substrate; forming an insulating layer; forming a lower electrode on the insulating layer; forming an organic layer for constituting an organic EL device on the lower electrode; forming an upper electrode on the organic layer; and after the step of forming the semiconductor layer of the field effect transistor and before the step of forming the organic layer, performing heat treatment such that an amount of a component that is desorbable as H2O from the field effect transistor during the step of forming the organic layer is less than 10?5 g/m2.

Abstract: A first oxide insulating film is formed over a substrate. After a first oxide semiconductor film is formed over the first oxide insulating film, heat treatment is performed, so that hydrogen contained in the first oxide semiconductor film is released and part of oxygen contained in the first oxide insulating film is diffused into the first oxide semiconductor film. Thus, a second oxide semiconductor film with reduced hydrogen concentration and reduced oxygen defect is formed. Then, the second oxide semiconductor film is selectively etched to form a third oxide semiconductor film, and a second oxide insulating film is formed. The second oxide insulating film is selectively etched and a protective film covering an end portion of the third oxide semiconductor film is formed. Then, a pair of electrodes, a gate insulating film, and a gate electrode are formed over the third oxide semiconductor film and the protective film.

Abstract: When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.

Abstract: A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a plurality of shallow trench isolation structures extending into the silicon substrate and filled with an insulating dielectric material to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.

Abstract: The present invention provides a method for manufacturing a semiconductor structure. The method comprises: providing an SOI substrate and forming a gate structure on said SOI substrate; etching a SOI layer and a BOX layer of the SOI substrate on both sides of the gate structure to form a trench exposing the BOX layer, said trench partially entering into the BOX layer; forming a stressed layer that fills up a part of said trench; forming a semiconductor layer covering the stressed layer in the trench. Correspondingly, the present invention also provides a semiconductor structure formed by the above method. In the semiconductor structure and the method for manufacturing the same according to the present invention, a trench is formed on an ultrathin SOI substrate, first filled with a stressed layer, and then filled with a semiconductor material to be ready for forming a source/drain region.

Abstract: Processes for making field effect transistors relax a buried stressor layer to induce strain in a silicon surface layer above the buried stressor layer. The buried stressor layer is relaxed and the surface layer is strained by implantation into at least the buried stressor layer, preferably on both sides of a portion of the surface layer that is to be stressed. For example, implanting ions through the surface silicon layer on either side of the gate structure of the preferred FET implementation into an underlying stressor layer can induce strain in a channel region of the FET. This process can begin with a silicon or silicon-on-insulator substrate with a buried silicon germanium layer having an appropriate thickness and germanium concentration. Other stressor materials can be used.

Abstract: Methods of forming thin-film transistors and memories are disclosed. In one such method, polycrystalline silicon is hydrogen plasma doped to form doped polycrystalline silicon. The doped polycrystalline silicon is then annealed. The hydrogen plasma doping and the annealing are decoupled.

Abstract: A second conduction-type MIS transistor in which a source is coupled to a second power source over the surface of a first conduction-type well and a drain is coupled to the open-drain signal terminal is provided. A second conduction-type first region is provided at both sides of the MIS transistor in parallel with a direction where the electric current of the MIS transistor flows and coupled to the open-drain signal terminal. The whole these components are surrounded by a first conduction-type guard ring coupled to the second power source and the outside surrounded by the first conduction-type guard ring is further surrounded by a second conduction-type guard ring coupled to a first power source. Thereby, the semiconductor device is capable of achieving ESD protection of an open-drain signal terminal having a small area and not providing a protection element between power source terminals.

Abstract: A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.

Abstract: A method for designing a semiconductor device includes arranging at least a pattern of a first active region in which a first transistor is formed and a pattern of a second active region in which a second transistor is formed; arranging at least a pattern of a gate wire which intersects the first active region and the second active region; extracting at least a first region in which the first active region and the gate wire are overlapped with each other; arranging at least one pattern of a compressive stress film on a region including the first active region; and obtaining by a computer a layout pattern of the semiconductor device, when the at least one pattern of the compressive stress film is arranged, end portions of the at least one pattern thereof are positioned based on positions of end portions of the first region.

Abstract: The present disclosure provides a method for manufacturing a semiconductor field effect transistor, comprising: forming a semiconductor substrate having a local Silicon-on-Insulator (SOI) structure, which comprises a local buried isolation dielectric layer; forming a fin on a silicon substrate above the local buried isolation dielectric layer; forming a gate stack structure on a top and on side faces of the fin; forming source/drain structures in the fin at both sides of the gate stack structure; and metallizing. The present disclosure uses a conventional top-to-bottom process based on quasi-plane, which has a good compatibility with CMOS planar processes. Also, the method can suppress short channel effects and help to reduce the dimensions of MOSFETs.

Abstract: RC delay in gate lines of a wide display is reduced by using a low resistivity conductor in the gate lines and a different conductor for forming corresponding gate electrodes. More specifically, a corresponding display substrate includes a gate line made of a first gate line metal, a data line made of a first data line metal, a pixel transistor and a first connection providing part. The pixel transistor includes a first active pattern formed of polycrystalline silicon (poly-Si) and a first gate electrode formed there above and made of a conductive material different from the first gate line metal. The first connection providing part connects the first gate electrode to the gate line. On the other hand, the source electrode is integrally extended from the data line.

Abstract: An object of the invention is to provide a TFT substrate and a method for producing a TFT substrate which is capable of drastically reducing the production cost by decreasing the number of steps in the production process and improving production yield. A TFT substrate comprises: a substrate; a first oxide layer formed above the substrate; a second oxide layer formed above the first oxide layer with a channel part interposed therebetween; gate insulating film formed above the substrate, the first oxide layer and the second oxide layer; a gate electrode and a gate wire formed above the gate insulating film.

Abstract: The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved.

Abstract: An approach for sinking heat from a transistor is provided. A method includes forming a substrate contact extending from a first portion of a silicon-on-insulator (SOI) island to a substrate. The method also includes forming a transistor in a second portion of the SOI island. The method further includes electrically isolating the substrate contact from the transistor by doping the first portion of the SOI island.

Abstract: A method for forming a thin film transistor includes joining a crystalline substrate to an insulating substrate. A doped layer is deposited on the crystalline substrate, and the doped layer is patterned to form source and drain regions. The crystalline substrate is patterned to form an active area such that a conductive channel is formed in the crystalline substrate between the source and drain regions. A gate stack is formed between the source and drain regions, and contacts are formed to the source and drain regions and the gate stack through a passivation layer.

Abstract: A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate, and forming a gate structure having a gate dielectric layer and a gate metal layer on the semiconductor substrate. The method also includes forming offset sidewall spacers at both sides of the gate structure, and forming lightly doped regions in semiconductor substrate at both sides of the gate structure. Further, the method includes forming a first metal silicide region in each of the lightly doped regions, and forming main sidewall spacers at both sides of the gate structure. Further, the method includes forming heavily doped regions in semiconductor substrate at both sides of the gate structure and the main sidewall spacers, and forming a second metal silicide region in each of the heavily doped regions.

Abstract: In an organic light-emitting display device and a method of manufacturing the same, the organic light-emitting display device comprises: a substrate in which a light-emitting region and a thin-film transistor (TFT) region are defined; and a plurality of insulating films formed on the substrate. A refractive index changes at only one of the interfaces between insulating films, which correspond to the light-emitting region and are formed between the substrate and a first electrode of an organic electroluminescence display element, and a refractive index changes at two or more of the interfaces between insulating films which correspond to the TFT region.

Abstract: A method for forming a Ge-on-insulator structure is provided, comprising steps of: forming a Ge layer (1200) on a substrate (2000); treating a first surface of the Ge layer (1200) to form a first semiconducting metal-germanide passivation layer (1300); bonding the first semiconducting metal-germanide passivation layer (1300) with a silicon substrate (1100), wherein on a surface of the silicon substrate (1100) an oxide insulating layer is formed; and removing the substrate (2000). Further, a Ge-on-insulator structure formed by the method is also provided.

Abstract: A method is provided for forming a printed top gate thin film transistor (TFT) with a short channel length. The method provides a substrate with a low surface energy top surface. A metal ink line is continuously printed across a region of the substrate top surface, and in response to the surface tension of the printed metal ink, discrete spherical ink caps are formed in the region. Then, the surface energy of the substrate top surface in the region is increased. A source metal ink line is printed overlying a source spherical ink cap contact, and a drain metal ink line, parallel to the source metal ink line, is printed overlying a drain spherical ink cap contact. After depositing a semiconductor film, a channel is formed in the semiconductor film between the source and drain spherical ink cap contacts having a channel length equal to the first distance.

Abstract: A thin film transistor including a first insulating layer disposed on a substrate and having a first hole; a second insulating layer disposed on the substrate and having a second hole; a gate insulating layer disposed between the first and second insulating layers; a gate electrode formed in the first hole; a source electrode and second drain electrode formed at both sides of an inner portion of the second hole; and an activated layer formed between the source electrode and the second drain electrode of the inner portion of the second hole, and having a planarization layer.

Abstract: A semiconductor structure including a test structure for detection of a gap in a conductive layer of the semiconductor structure includes a semiconductor substrate; the test structure, the test structure being located on the semiconductor substrate, the test structure comprising a multilayer gate stack, wherein the multilayer gate stack includes a single conductive layer region including: a gate dielectric located on the semiconductor substrate; the conductive layer located on the gate dielectric; and an undoped amorphous silicon layer located on the conductive layer; and wherein the test structure is configured to detect the presence of the gap in the conductive layer.

Abstract: One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming a first oxide component over a base component, causing crystal growth which proceeds from a surface toward an inside of the first oxide component by first heat treatment to form a first oxide crystal component at least partly in contact with the base component, forming a second oxide component over the first oxide crystal component; and causing crystal growth by second heat treatment using the first oxide crystal component as a seed to form a second oxide crystal component.

Abstract: A permeation barrier film structure for organic electronic devices includes one or more bilayers having a hybrid permeation barrier composition. Each of the one or more bilayers includes a first region having a first composition corresponding to a first CF4—O2 Plasma Reactive Ion Etch Rate and a second region having a second composition corresponding to a second CF4—O2 Plasma Reactive Ion Etch Rate, wherein the second Etch Rate is greater than the first Etch Rate by a factor greater than 1.2 and the hybrid permeation barrier film is a homogeneous mixture of a polymeric material and a non-polymeric material, wherein the mixture is created from a single precursor material.