Abstract: A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on the substrate; providing a first projection extending above the insulating layer, the first projection including an Si material and a Si1-xGex material; and exposing the first projection to preferential oxidation to yield a second projection including a center region comprising Ge/Si1-yGey and a covering region comprising SiO2 and enclosing the center region.

Abstract: A nanowire tunnel field effect transistor (FET) device includes a channel region including a silicon portion having a first distal end and a second distal end, the silicon portion is surrounded by a gate structure disposed circumferentially around the silicon portion, a drain region including an doped silicon portion extending from the first distal end, a portion of the doped silicon portion arranged in the channel region, a cavity defined by the second distal end of the silicon portion and an inner diameter of the gate structure, and a source region including a doped epi-silicon portion epitaxially extending from the second distal end of the silicon portion in the cavity, a first pad region, and a portion of a silicon substrate.

Abstract: Embodiments of the present invention provide a thin film transistor, a manufacturing method thereof and a display device. The method for manufacturing the thin film transistor, comprising the following steps: providing a substrate; forming a semiconductor layer on the substrate; forming a gate insulating layer; and forming a gate electrode, wherein the gate insulating layer comprises a first gate insulating layer, the first gate insulating layer being formed by oxidizing a portion of the semiconductor layer, and the unoxidized portion of the semiconductor layer forming an active layer, and wherein the gate electrode is formed in such a way that the gate insulating layer is sandwiched between the gate electrode and the active layer.

Abstract: A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

Abstract: A method of manufacturing a display device including an electrostatic discharge protection circuit, the method including: forming an amorphous silicon layer on a substrate; crystallizing a partial region of the amorphous silicon layer into a polycrystalline silicon layer; and forming at least one transistor on the amorphous silicon layer that was not crystallized into the polycrystalline layer, wherein the electrostatic discharge protection circuit comprises the at least one transistor.

Abstract: Methods of semiconductor device fabrication techniques using double patterning are disclosed. According to various embodiments of the invention, methods of semiconductor device fabrication using self-aligned double patterning are provided. Particular embodiments of the invention allow creation of logic circuit patterns using two lithographic operations. One embodiment of the invention employs self-aligned double patterning to define two or more sets of parallel line features with a connection feature between the sets. In such embodiments, the sets of parallel line features along with the connection features are formed using two lithographic masks, without the need for an additional mask layer to form the connection. In other embodiments, other features in addition to the connection can be added in the same mask layer.

Abstract: Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.

Abstract: A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.

Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

Abstract: A substrate includes a first source region and a first drain region each having a first semiconductor layer disposed on a second semiconductor layer and a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes; nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members include the first semiconductor layer, and opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes. The substrate further includes a second source and drain regions having the characteristics of the first source and drain regions, and a single channel member suspended by the second source region and the second drain region and having the same characteristics as the nanowire channel members. A width of the single channel member is at least several times a width of a single nanowire member.

Abstract: Disclosed are a thin film transistor array substrate and a producing method thereof in the embodiments of the present invention, the producing method comprising: forming an active layer thin film and a conductive layer thin film on a substrate; depositing a source/drain electrode layer thin film on the conductive layer thin film, treating the conductive layer thin film and the source/drain electrode layer thin film using gray tone or half tone masking process, to form at least two data lines, a pixel electrode and source/drain electrodes of the thin film transistor (TFT); after depositing an insulating layer thin film covered the active layer thin film, the source/drain electrodes, the data lines and the pixel electrode, forming a through hole and a gate insulating layer of the TFT on the insulating layer, to form an active layer of the TFT; forming a gate electrode of the TFT and at least two gate scanning lines cross with the data wires.

Abstract: Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.

Abstract: A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius.

Abstract: A semiconductor device and method of making same. The device includes a substrate comprising a semiconductor layer on an insulating layer, the semiconductor layer including a semiconductor body having a body contact region and an abutting switching region; a bridged gate over the semiconductor body, the bridged gate having a bridge gate portion and an abutting gate portion, the bridge gate portion comprising a multilayer first gate stack and the gate portion comprising a multilayer second gate stack comprising the gate dielectric layer on the semiconductor body; first and second source/drains formed in the switching region on opposite sides of the channel; and wherein a first work function difference between the bridge portion and the body contact region is different from a second work function difference between the gate portion and the channel region.

Abstract: A thin film transistor array panel includes a substrate, a semiconductor that is positioned on the substrate and that has a source area, a drain area, and a channel area, a gate insulating layer that is positioned on the semiconductor, a gate electrode that is positioned on the gate insulating layer and that overlaps the channel area, a first interlayer insulating layer that is positioned on the gate electrode and that has contact holes that expose the source area and the drain area, respectively, of which the source area and the drain area have a same plane pattern as that of the contact holes, and a source electrode and a drain electrode that are positioned on the first interlayer insulating layer and that are connected to the source area and the drain area, through the contact holes, respectively.

Abstract: An electro-optical device includes a light-emitting layer provided with a white light-emitting element; and a reflective filter layer that is located at one side of the light-emitting layer and is provided with a reflective color filter.

Abstract: A light-emitting device having at least one spacer located at a bottom surface is disclosed. In two other embodiments, an electronic display system and an electronic system having such light-emitting device are disclosed. The light-emitting device comprises a plurality of leads, a light source die, and a body. The body encapsulates a portion of the plurality of leads and the light source die. The body has a least one side surface and a bottom surface. The at least one spacer is located at the bottom surface. In use, the light-emitting device is attached to a top surface of a substrate. The spacer is configured to create an air vent between the bottom surface and the top surface of the substrate when the light-emitting device is attached to, and the spacer is in contact with the substrate.

Abstract: A precision resistor is formed with a controllable resistance to compensate for variations that occur with temperature. An embodiment includes forming a resistive semiconductive element having a width and a length on a substrate, patterning an electrically conductive line across the width of the resistive semiconductive element, but electrically isolated therefrom, and forming a depletion channel in the resistive semiconductive element under the electrically conductive line to control the resistance value of the resistive semiconductive element. The design enables dynamic adjustment of the resistance, thereby improving the reliability of the resistor or allowing for resistance modification during final packaging.

Abstract: An object is to provide a method for manufacturing a thin film transistor and a display device with reduced number of masks, in which adverse effects of optical current are suppressed. A manufacturing method comprises forming a stack including, from bottom to top, a light-blocking film, a base film, a first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; performing first etching on the whole thickness of the stack using a first resist mask formed over it; forming a gate electrode layer by side etching the first conductive film in a second etching; forming a second resist mask over the stack; and performing third etching down to the semiconductor film, and partially etching it, using the second resist mask to form a source and drain electrode layer, a source and drain region, and a semiconductor layer.

Abstract: The present invention generally relates to an amorphous semiconductor material and TFTs containing the material. The semiconductor material contains a single cation, such as zinc, and multiple anions. For the multiple anions, only one of the anions can be oxygen or nitrogen. The anions compete with each other to twist the resulting structure. For example, if one of the anions bonded with the cation would result in a cubic structure, and another of the anions bonded with the cation would result in a hexagonal structure, the competing anions would twist the resulting structure so that the structure remains amorphous rather than crystalline. Further, because a single cation is utilized, there is no grain boundary and thus, the material has a high mobility.

Abstract: Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.

Abstract: A method for fabricating a carbon-based semiconductor device. A substrate is provided and source/drain contacts are formed on the substrate. A graphene channel is formed on the substrate connecting the source contact and the drain contact. A dielectric layer is formed on the graphene channel with a molecular beam deposition process. A gate contact is formed over the graphene channel and on the dielectric. The gate contact is in a non-overlapping position with the source and drain contacts leaving exposed sections of the graphene channel between the gate contact and the source and drain contacts.

Abstract: A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate and fin structures on the substrate. A sidewall spacer is formed along sidewall of fin structures in the precursor. A portion of fin structure is recessed to form a recessing trench with the sidewall spacer as its upper portion. A semiconductor is epitaxially grown in the recessing trench and continually grown above the recessing trench to form an epitaxial structure.

Abstract: The invention provides a graphene device structure and a method for manufacturing the same, the device structure comprising a graphene layer; a gate region in contact with the graphene layer; semiconductor doped regions formed in the two opposite sides of the gate region and in contact with the graphene layer, wherein the semiconductor doped regions are isolated from the gate region; a contact formed on the gate region and contacts formed on the semiconductor doped regions. The on-off ratio of the graphene device is increased through the semiconductor doped regions without increasing the band gap of the graphene material, i.e., without affecting the mobility of the material or the speed of the device, thereby increasing the applicability of the graphene material in CMOS devices.

Abstract: An embodiment of the invention provides a method for manufacturing an array substrate, wherein the procedure for forming a data line, an active layer with a channel, a source electrode, a drain electrode and a pixel electrode comprises applying a photoresist on a data line metal thin film and performing exposure and development processes by using a multi-tone mask so as to form a photoresist pattern including a third thickness region, a second thickness region and a first thickness region whose thicknesses are successively increased, the third thickness region at least corresponding to the pixel electrode, the second thickness region corresponding to the data line, the active layer, the source electrode and the drain electrode, and the first thickness region corresponding to the other regions.

Abstract: A flat panel display having a thin-film transistor (TFT) and a pixel unit and a method of manufacturing the same are disclosed. In one embodiment, the method includes forming a step difference layer having a relatively high step and a relatively low step on a substrate and forming an amorphous silicon layer on the step difference layer along a height shape of the step difference layer. The method further includes crystallizing the amorphous silicon layer into a crystalline silicon layer and polishing the crystalline silicon layer to form a planarized surface of the crystalline silicon layer having no height differences so that the crystalline silicon layer remains on a region corresponding to the low step and an active layer is formed. According to this method, crystallization protrusions are effectively removed from the active layer, and thus, stable brightness characteristics of the display apparatus are guaranteed.

Abstract: Drive units arranged on a transistor array substrate include faulty drive units. The pixel electrodes include first pixel electrodes and second pixel electrodes, the first pixel electrodes corresponding one-to-one to the faulty drive units, and the second pixel electrodes corresponding one-to-one to the non-faulty drive units, a portion of each second pixel electrode is embedded in the contact hole corresponding thereto, and is in contact with a power supply pad of the non-faulty drive unit corresponding thereto, so that the second pixel electrode is electrically connected to the non-faulty drive unit. Each first pixel electrode is electrically insulated from the faulty drive unit corresponding thereto, and is connected by a connector to any of the second pixel electrodes adjacent thereto. A surface of each connector facing the interlayer insulation film is entirely in contact with the interlayer insulation film.

Abstract: The present invention discloses a thin-film transistor (TFT) array substrate and a manufacturing method thereof. Depositing a transparent conductive layer and a first metal layer in turn on a substrate patterned by a first multi-tone mask (MTM) to form a gate, a common electrode and a reflecting layer; depositing a gate insulation layer and a semiconductor layer patterned by a second MTM to remain the semiconductor layer on the gate; and depositing a second metal layer patterned by a third MTM to form a source and a drain.

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

Abstract: A catalyst film (2) is formed over a substrate (1). A graphene (3) is grown on the catalyst film (2). A gap through which a lower surface of the catalyst film (2) is exposed is formed. The catalyst film (2) is removed through the gap.

Abstract: A method of fabricating a TFT includes providing a substrate where a gate, an insulating layer, and a channel layer are formed. A conductive layer is formed on the substrate to cover the channel layer and the insulating layer. A photoresist layer is formed on the conductive layer. A photo mask is placed above the photoresist layer and has a data line pattern, a source pattern, and a drain pattern. A first width (W1) between the source pattern and the drain pattern and a second width (W2) of the data line pattern satisfy the following: if W1?1(um), then W2+a(um), and 0.3<a<0.7. An exposing process is performed by using the photo mask, and a development process is performed to pattern the photoresist layer. The conductive layer is patterned by using the photoresist layer as an etching mask to form a source, a drain, and a data line.

Abstract: Disclosed are embodiments of a field effect transistor with a gate-to-body tunnel current region (GTBTCR) and a method. In one embodiment, a gate, having adjacent sections with different conductivity types, traverses the center portion of a semiconductor layer to create, within the center portion, a channel region and a GTBTCR below the adjacent sections having the different conductivity types, respectively. In another embodiment, a semiconductor layer has a center portion with a channel region and a GTBTCR. The GTBTCR comprises: a first implant region adjacent to and doped with a higher concentration of the same first conductivity type dopant as the channel region; a second implant region, having a second conductivity type, adjacent to the first implant region; and an enhanced generation and recombination region between the implant regions. A gate with the second conductivity type traverses the center portion.

Abstract: A method for manufacturing a semiconductor device includes forming a transistor having a stacked structure in a peripheral circuit region to increase net die and forming a metal silicide layer over a source/drain region of a transistor formed over an upper layer to reduce a contact resistance. The semiconductor device may include: a second active region including a silicon layer connected to a first active region of a semiconductor substrate; a gate formed over the second active region; a spacer formed on sidewalls of the gate; a source/drain region form at both sides of the spacer; and a metal silicide layer formed over the gate and the source/drain region.

Abstract: A method for forming a semiconductor device is disclosed. In the semiconductor device, a gate is formed to enclose a fin structure in a 6F2 saddle fin gate structure transistor, so that the size of a channel region increases. In accordance with an aspect of the present invention, a method for forming a semiconductor device includes: defining an active region by forming a device isolation film over a semiconductor substrate; forming a first recess extending to a first level in the active region; forming a sacrificial film at a lower portion of the first recess; forming a fin structure over the sacrificial film; separating the fin structure from the semiconductor substrate in the active region by removing the sacrificial film and forming a hole between the fin structure and the active region; and forming a gate to enclose the fin structure.

Abstract: A display substrate includes a pixel electrode, an m-th data line (‘m’ is a natural number), a floating electrode, a (m+1)-th data line and a storage electrode. The pixel electrode is disposed in a pixel area of the substrate. The m-th data line is disposed at a first side of the pixel electrode and electrically connected to the pixel electrode. The floating electrode partially overlaps with the m-th data line. The (m+1)-th data line is disposed at a second side of the pixel electrode. The storage electrode is spaced apart from the (m+1)-th data line.

Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.

Abstract: Objects are to provide a semiconductor device for high power application in which a novel semiconductor material having high productivity is used and to provide a semiconductor device having a novel structure in which a novel semiconductor material is used. The present invention is a vertical transistor and a vertical diode each of which has a stacked body of an oxide semiconductor in which a first oxide semiconductor film having crystallinity and a second oxide semiconductor film having crystallinity are stacked. An impurity serving as an electron donor (donor) which is contained in the stacked body of an oxide semiconductor is removed in a step of crystal growth; therefore, the stacked body of an oxide semiconductor is highly purified and is an intrinsic semiconductor or a substantially intrinsic semiconductor whose carrier density is low. The stacked body of an oxide semiconductor has a wider band gap than a silicon semiconductor.

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device (e.g., FinFET device) having a gate structure formed on a planar surface thereof. Specifically, a uniform, oxide-fin (OF) surface is formed. Then, a “dummy” gate structure and a set of spacers are formed thereon. Once the gate structure and set of spacers have been formed, the OF surface may be recessed. In one embodiment, the OF surface is uniformly recessed. In another embodiment, the OF surface is selectively recessed to yield a set of fins. In any event, after the recessing, an epitaxial layer is grown and an oxide fill is performed. Then, the “dummy” gate structure is removed (from between the set of spacers) and an oxide recess is performed to yield a set of channel fins between the spacers.

Abstract: A method of forming a metal silicide region. The method comprises forming a metal material over and in contact with exposed surfaces of a dielectric material and silicon structures protruding from the dielectric material. A capping material is formed over and in contact with the metal material. The silicon structures are exposed to heat to effectuate a multidirectional diffusion of the metal material into the silicon structures to form a first metal silicide material. The capping material and unreacted portions of the metal material are removed. The silicon structures are exposed to heat to substantially convert the first metal silicide material into a second metal silicide material. A method of semiconductor device fabrication, an array of silicon structures, and a semiconductor device structure are also described.

Abstract: A semiconductor device includes a semiconductor substrate having an active layer in which an element region and a contact region are formed, a support substrate supporting the active layer, and a buried insulation layer interposed between the active layer and the support substrate. A transistor element is formed in the element region, the transistor element having a transistor buried impurity layer formed within the active layer. The semiconductor device further includes a substrate contact having a contact buried impurity layer formed within the contact region and a through contact extending from the surface of the active layer to the support substrate through the contact buried impurity and the buried insulation layer, the contact buried impurity layer being in the same layer as the transistor buried impurity layer.

Abstract: A method of forming a semiconductor device is presented. The method includes providing a substrate. The method further includes forming a gate stack having a gate electrode on the substrate, which includes forming a metal gate electrode layer. A buffer gate electrode layer is formed on top of the metal gate electrode layer and a top gate electrode layer having a poly-silicon alloy is formed over the metal gate electrode layer.

Abstract: Embodiments of the disclosed technology disclose manufacture methods of a thin film transistor and an array substrate and a mask therefor are provided. The manufacture method of the thin film transistor comprises: patterning a wire layer by using a exposure machine and a mask with a first exposure amount larger than a normal exposure amount during formation of source and drain electrodes; forming a semiconductor layer on the patterned wire layer; patterning the semiconductor layer by using the exposure machine and the mask with a second exposure amount smaller than the first exposure amount. The mask comprises a source region for forming the source electrode, a drain region for forming the drain electrode and a slit provided between the source region and the drain region, and the width of the slit is smaller than the resolution of the exposure machine.

Abstract: A method is provided for preparing a printed metal surface for the deposition of an organic semiconductor material. The method provides a substrate with a top surface, and a metal layer is formed overlying the substrate top surface. Simultaneous with a thermal treatment of the metal layer, the metal layer is exposed to a gaseous atmosphere with thiol molecules. In response to exposing the metal layer to the gaseous atmosphere with thiol molecules, the work function of the metal layer is increased. Subsequent to the thermal treatment, an organic semiconductor material is deposited overlying the metal layer. In one aspect, the metal layer is exposed to the gaseous atmosphere with thiol molecules by evaporating a liquid containing thiol molecules in an ambient air atmosphere. Alternatively, a delivery gas is passed through a liquid containing thiol molecules. An organic thin-film transistor (OTFT) and OTFT fabrication process are also provided.

Abstract: A thin-film transistor including an oxide semiconductor layer is disclosed. The oxide semiconductor layer includes a first area, a second area and a third area forming a well-type potential in the film-thickness direction. The first area forms a well of the well-type potential and has a first electron affinity. The second area is disposed nearer to the gate electrode than the first area and has a second electron affinity smaller than the first electron affinity. The third area is disposed farther from the gate electrode than the first area and has a third electron affinity smaller than the first electron affinity. At least an oxygen concentration at the third area is lower than an oxygen concentration at the first area.

Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.

Abstract: Disclosed are an active layer ion implantation method and an active layer ion implantation method for thin-film transistor. The active layer ion implantation method comprises: applying a photoresist on the active layer; and implanting ions into the active layer through the photoresist.

Abstract: A stem wiring (13a) having a broad line width is formed above branch wirings (13b) having a narrow line width. In a region where the stem wiring (13a) is connected to the branch wiring (13b), the stem wiring (13a) overlaps with the branch wiring (13b) via a gate insulating film when seen in a plan view, a contact hole is provided in the gate insulating film so as to uncover the branch wiring (13b), and the stem wiring (13a) is electrically connected to the branch wiring (13b) via a connecting conductor formed in the contact hole. Consequently, a TFT array substrate can be achieved, in which a disconnection failure or an abnormal line width is reduced without enlarging the dimension of a driving circuit region.

Abstract: Transistor devices including stressors are disclosed. One such transistor device includes a channel region, a dielectric layer and a semiconductor substrate. The channel region is configured to provide a conductive channel between a source region and a drain region. In addition, the dielectric layer is below the channel region and is configured to electrically insulate the channel region. Further, the semiconductor substrate, which is below the channel region and below the dielectric layer, includes dislocation defects at a top surface of the semiconductor substrate, where the dislocation defects are collectively oriented to impose a compressive strain on the channel region such that charge carrier mobility is enhanced in the channel region.

Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.

Abstract: A microelectronic device includes a thin film transistor having an oxide semiconductor channel and an organic polymer passivation layer formed on the oxide semiconductor channel.