Abstract: A method begins by a processing module obtaining a set of encoded data slices for transmission to a receiving entity via a network, wherein the set of encoded data slices represents data that has been dispersed storage error encoded. The method continues with the processing module dividing the set into a plurality of sub-sets of encoded data slices in accordance with an error coding distributed routing protocol. The method continues with the processing module determining a plurality of routing paths within the network in accordance with the error coding distributed routing protocol. The method continues with the processing module transmitting the plurality of sub-sets of encoded data slices via the plurality of routing paths to the receiving entity in accordance with the error coding distributed routing protocol.

Abstract: A rate adjustment apparatus includes a calculating section to calculate a number of outputs where bits of input data are sequentially output when a number of times of puncturing of the input data to be punctured is smaller than a number of remaining bits after puncturing, and a processing section to sequentially output bits of the input data and puncture the bits of the input data based on the number of outputs calculated by the calculating section.

Abstract: Systems and methods enabling ultra-high-speed optical transport The systems and methods include receiving a modulated, encoded input stream. Channel impairments are removed using MAP equalization. Symbols are detected in the input stream to produce a stream of encoded data. The stream of encoded data is decoded with one or more low density parity check (LDPC) decoders that use an LDPC code built by modified progressive edge growth. The LDPC code is built by iteratively expanding trees from each variable node until all check nodes are connected to the respective variable node, while controlling both the local girth and the global girth of the code.

Abstract: An error detection and correction (EDAC) circuit mitigates the effect of single event upsets (SEU) events in a redundant memory system. The EDAC circuit includes a first input for receiving first data and parity information stored by a first memory device and a second input for receiving second data and parity information stored by a second memory device. First parity check logic calculates parity for the received first data and parity information. Second parity check logic calculates parity for the received second data and parity information. Bit comparison logic detects differences between the first data and the second data, and between the first parity information and the second parity information. Based on the parity check calculated for the first and second data, and the bit comparison, data select logic selects either the first data or the second data for provision to a data bus.

Abstract: A User Equipment (UE) configured for jointly encoding a Scheduling Request Indicator (SRI) and Acknowledgments/Negative Acknowledgments (ACK/NACKs) is disclosed. The UE includes a processor and instructions stored in memory. The UE generates a Scheduling Request Indicator (SRI) bit and a plurality of Acknowledgement/Negative Acknowledgement (ACK/NACK) bits. The UE also encodes the SRI bit and the plurality of ACK/NACK bits with unequal error protection to generate a jointly-encoded SRI and ACK/NACK message and transmits the jointly-encoded SRI and ACK/NACK message.

Abstract: The error correction processing includes: data reproduction processing of reproducing recording data, constituted by a plurality of data units each made of a plurality of bits, from a recording medium sequentially; error correction processing of performing error correction in the row direction and error correction in the column direction at least once for an error correction code block that has the reproduced recording data arranged in the row direction over a plurality of rows; determination processing of determining whether uncorrectable data is left behind after execution of the error correction processing; and erasure correction processing of performing, when it is determined that uncorrectable data is left behind, column-direction error correction considering data constituting at least one row of the error correction code block as erasure data, even in cases where uncorrectable data in the error correction in the row direction is not left behind.

Abstract: Systems and methods are disclosed for data recovery using outer codewords stored in volatile memory. Outer codewords can be associated with one or more horizontal portions or vertical portions of a non-volatile memory (“NVM”). In some embodiments, an NVM interface of an electronic device can program user data to a super block of the NVM. The NVM interface can then determine if a program disturb has occurred in the super block. In response to detecting that a program disturb has occurred in the super block, the NVM interface can perform garbage collection on the super block. The NVM interface can then use outer codewords associated with the super block to recover from any uncorrectable error correction code errors detected in the super block.

Abstract: A method includes reading data from a data area of a word line and reading first ECC data from an ECC area of the word line. The method also includes, in response to determining that an error indicator exceeds a threshold, storing second ECC data in the ECC area. The second ECC data corresponds to a subsection of the data area.

Abstract: A received optical signal (SH, Sv) is coherently demodulated and converted into orthogonal x-polarisation samples (rx(n)), and y-polarisation samples (ry(n)). These samples are converted into signal x-samples zx(n) and signal y-samples zy(n) by an FIR butterfly filter (8). Correction values are calculated in an error calculating circuit (12) of a control unit (11) and added to filter transfer functions derived by a standard algorithm to determine corrected filter coefficients. Degenerate convergences calculating the transfer functions are avoided.

Abstract: A transmission device according to the present invention splits information bits, calculates two parity bit sequences from the split information bits, combines the parity bit sequences with information bits (encoded information bit) such that the calculated two parity bit sequences are not added to the same information bits. Then, the transmission device changes the order of the combined information, distributes each of the reordered information to levels L0 and L1, and performs multi level modulation, thus making the reliability of each bit constant.

Abstract: A digital broadcast system and a method of processing data are provided. The transmitting system of the digital broadcast system includes an encoder for encoding mobile data for FEC to build RS frames, a signaling encoder for encoding TPC data including the RS frame mode information, a divider for dividing at least one of the RS frames into a plurality of portions, a block processor for converting one portion to a plurality of SCCC blocks, a converter for converting the SCCC blocks to data blocks, a group formatter for forming data groups, a packet formatter for forming data packets including data in the data groups, a multiplexer for multiplexing main data packets including main data and the data packets, a trellis encoder for performing trellis encoding on data in the multiplexed data packets and a transmission unit for transmitting the broadcast signal including a parade of the data groups.

Abstract: A communication device is disclosed. The device is configured to generate a first block of first cyclic redundancy check (CRC) parity bits on a transport block wherein the first block of CRC parity bits is based on a first generator polynomial, to attach the first block of CRC parity bits to the transport block and to segment the transport block into multiple code blocks. The processor is also configured to generate a second block of CRC parity bits on each code block wherein each of the second blocks of CRC parity bits is based on a second generator polynomial that is different than the first generator polynomial. The first and second generator polynomials have a common degree. A second block of CRC parity bits is attached to each code block, and the code blocks are concatenated after channel encoding.

Abstract: A method includes accepting modulated symbols, which carry bits of a code word of a Low Density Parity Check (LDPC) code, and computing respective soft input metrics for the bits. The code word is decoded using an iterative LDPC decoding process that includes selecting, based on a predefined criterion, a number of internal iterations to be performed by an LDPC decoder (84) in the process, performing the selected number of the internal iterations using the LDPC decoder so as to estimate decoded bits and soft output metrics indicative of the input bits based on the soft input metrics, performing an external iteration that updates one or more of the soft input metrics based on one or more of the soft output metrics produced by the LDPC decoder, and repeating at least one of the internal iterations using the updated soft input metrics.

Abstract: Embodiments of the present invention provide a method for retransmission based on forward error correction. The method includes: when received source data packets loss occurs, judging whether all of the lost source data payloads can be decoded by using the received source data payloads and check data; if all of the lost source data payloads cannot be decoded, determining needed source data symbols for decoding all of the lost source data payloads by using the received source data payloads and the check data; and requesting for retransmitting the needed source data symbols.

Abstract: An apparatus for determination of a position of a 1-bit error includes an error position determiner of the inner code, an error syndrome determiner of the outer code, a derivative determiner and an overall error position determiner. The error position determiner of the inner code determines at least one possible error position of a bit error in the coded bit sequence on the basis of the inner code. The error syndrome determiner of the outer code determines a value of a non-linear syndrome bit of the outer code on the basis of a non-linear function of bits in the coded bit sequence. Furthermore, the derivative determiner determines a value of a derivative bit for at least one determined, possible error position of the bit error on the basis of derivation of the non-linear function based on the bit at the determined, possible error position in the coded bit sequence.

Abstract: A semiconductor memory includes multi-mode reporting signals, a state register, and parity detectors. The parity detector determines whether signals received on a communication bus contain a desired parity. The multi-mode reporting signals enable reporting of communication faults without adding additional signals to the semiconductor memory by being configured in a normal operating mode or a parity fault mode for reporting communication faults to an external memory controller. The state register enables storing of received values from the communication bus. With the state register, a memory controller may determine correctly received signal patterns and failing signal patterns. Parity may be defined as even or odd and may be generated based on various signal configurations. The invention may be configured as a computing system comprising a processor, an input device, an output device, the memory controller, and at least one semiconductor memory.

Abstract: The present invention provides a method and apparatus for selectively updating error correction code bits. One embodiment of the method includes determining a first subset of a plurality of error correction code bits formed from a plurality of data bits in response to changes in a first subset of the data bits. The first subset of the plurality of error correction code bits is less than all of the plurality of error correction code bits.

Abstract: Detecting, avoiding and/or correcting problematic puncturing patterns in parity bit streams used when implementing punctured Turbo codes is achieved without having to avoid desirable code rates. This enables identification/avoidance of regions of relatively poor Turbo code performance. Forward error correction comprising Turbo coding and puncturing achieves a smooth functional relationship between any measure of performance and the effective coding rate resulting from combining the lower rate code generated by the Turbo encoder with puncturing of the parity bits. In one embodiment, methods to correct/avoid degradations due to Turbo coding are implemented by puncturing interactions when two or more stages of rate matching are employed.

Abstract: In one embodiment, a communications system has a write path and a read path. In the write path, a local/global interleaver interleaves a user data stream, and an error-correction (EC) encoder encodes the user data stream to generate an EC codeword. A local/global de-interleaver de-interleaves the parity bits of the EC codeword, and both the original un-interleaved user data and the de-interleaved parity bits are transmitted via a noisy channel. In the read path, a channel detector recovers channel soft-output values corresponding to the codeword. A local/global interleaver interleaves the channel values, and an EC decoder decodes the interleaved values to recover the original codeword generated in the write path. A de-multiplexer de-multiplexes the user data from the parity bits. Then, a local/global de-interleaver de-interleaves the user data to obtain the original sequence of user data that was originally received at the write path.

Abstract: Data is divided into parts and each part provided to a different processor. Each processor processes the provided data part to produce a partial CRC result. The partial CRC results from each of the different processors are XORed to produce a CRC of the data.

Abstract: A decoder, a method of decoding and systems implementing the same are disclosed. In one example, the method includes calculating syndrome values from input codewords, generating an error location polynomial about the codewords using the syndrome values, determining an error count in the codewords using the error location polynomial, and adjusting power consumption of a circuit in response to the determined error count in the codewords. In one example, a frequency of a clock signal to be provided to a search circuit may be determined based on the error count, and the clock signal may be provided having the determined frequency to a search circuit, such as a Chien search circuit.

Abstract: A device (20) for an adaptive modulation communication system is provided. The device (20) comprises an input device (21) adapted to receive, from a communication channel, data encoded through a FEC code. A FEC decoder (23) connected downstream of the input device (21) is also provided for FEC decoding the received encoded data and providing error information determined by the FEC decoding. The device according to the invention further comprises means for measuring first error information of the encoded data before FEC decoding the received encoded data, and means for measuring second error information determined by the FEC decoder (23). Means (25) for estimating a condition of the communication channel based on both the first error information and the second error information are also provided.

Abstract: An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type.

Abstract: An operating method of a base station for transmitting MAP information in a wireless communication system includes determining a seed value for randomizing MAP information bits, generating a Media Access Control (MAC) control message including the seed value and a Station IDentifier (STID), and transmitting the MAC control message to a mobile station. Hence, the assignment A-MAP IE can be transmitted more safely.

Abstract: A DTV transmitter includes a pre-processor pre-processing enhanced data, a data formatter generating enhanced data packets including the pre-processed data and inserting known data place holders to the data packets, and a multiplexer multiplexing the enhanced data packets with main data packets. It further includes an RS encoder which RS-codes the multiplexed data packets, and a data interleaves which interleaves the RS-coded data packets. The RS encoder adds systematic RS parity data to each main data packet and adds non-systematic RS parity place holders to each enhanced data packet. The RS encoder adds the RS parity place holders such that the RS parity place holders are placed after the enhanced data within each interleaved enhanced data packet.

Abstract: According to an embodiment, an error correction decoder carries out iterative decoding for data coded using an irregular LDPC code. The decoder includes a likelihood control unit. The likelihood control unit is configured to carry out weighting using first extrinsic value weights when a first condition including a condition that a code word cannot be obtained even when number of times the iterative decoding has been carried out is greater than a first iterative times, in order to increase absolute value of a extrinsic value from a check node not satisfying a parity check to a variable node, wherein the first extrinsic value weights are equal to each other or become larger in descending order of column weights of the variable nodes, and a maximum of the first extrinsic value weights is not equal to a minimum of the first extrinsic value weights.

Abstract: A method of operating a semiconductor memory device according to an aspect of the present disclosure includes performing a program loop, including a program operation and a program verification operation, in order to store input data in selected memory cells, performing a first error bit check operation for comparing the number of error bits of data not identical with the input data, with the number of correctable error bits, if the number of error bits is equal to or smaller than the number of correctable error bits, performing a second error bit check operation for comparing the number of error bits with the reference number of bits for replacement determination, and if the number of error bits is greater than the reference number of bits for replacement determination, updating failed column address information by adding the column address of a memory cell, having the error bits, to the failed column address information.

Abstract: Embodiments of the present invention generally relate to binary block transmission codes for high-speed network transmissions. More specifically, embodiments of the present invention relate to bounded-disparity run-length-limited forward error correction codes and methods of constructing and utilizing same. In one embodiment, a method for generating binary block bounded-disparity run-length-limited forward error correction transmission codes comprises selecting an existing base code, deriving a sub-code from the existing base code, having properties indicated by disparity bound, run-length limit and minimum distance, ascertaining a plurality of codewords and control characters from within the sub-code, encoding Messages to be transmitted with at least one codeword from the plurality of codewords, transmitting codewords from a transmitter to a receiver, and decoding the codewords into Messages.

Abstract: A method for a decoding device to decode a codeword matrix of a product code includes: generating a first extended parity check matrix for a vertical code; decoding a horizontal codeword of a plurality of rows in the codeword matrix to thus perform a first decoding process; generating a second extended parity check matrix by removing a column corresponding to a row of the first decoding-succeeded horizontal codeword from the first extended parity check matrix; and decoding the first decoding-failed horizontal codeword by using the second extended parity check matrix to thus perform a second decoding process. Therefore, the simple and reliable product code decoding method is provided.

Abstract: An embodiment of the present invention provides a wireless station (STA), comprising a transceiver operable for communicating in a wireless network, wherein the transceiver is adapted to use signaling that enables the wireless station to communicate necessary information including a desired modulation coding scheme (MCS).

Abstract: There is provided a method of encoding and decoding data using an error control code having a codebook G. The codebook G is a sub-codebook of a codebook P. Each codeword g in the sub-codebook G has an autocorrelation amplitude that is different from and higher than each correlation amplitude between g and each of the other codewords in the sub-codebook G. In one specific embodiment in which the codebook P is that of a Reed-Muller code, using G instead of P reduces the likelihood of the presence of more than one maximum correlation amplitude when computing the non-coherent decision metric during decoding.

Abstract: Systems, methods, and other embodiments associated with decoder based data recovery are described. According to one embodiment, an apparatus includes a decoder configured to perform a decoding process on codewords to verify that the codewords meet coding constraints. The decoder includes a recovery unit configured to store recovery instructions for performing a modified decoding process. The recovery unit is further configured to execute the stored recovery instructions when a decoded codeword fails to meet the coding constraints.

Abstract: A data transfer method transfers data encoded with a loss correction code by using a protocol having no error correction function. The method includes acquiring a data size of transfer target data; acquiring a relationship between a code length of the loss correction code and a transfer time for the acquired data size of the transfer target data; determining an optimum code length of the loss correction code for encoding the transfer target data based on the acquired relationship between the code length and the transfer time for the acquired data size; and encoding the target data with the loss correction code having the optimum code length.

Abstract: Disclosed is an apparatus having a detector for an iterative LDPC-coded MIMO-OFDM system, where the detector is configured to use a structured irregular LDPC code in conjunction with a belief propagation algorithm. Also disclosed is an apparatus having a detector for a structured irregular LDPC-coded MIMO-OFDM system, where the detector is configured to use an iterative Recursive Least Squares-based data detection and channel estimation technique. Corresponding methods and computer program products are also disclosed.

Abstract: Apparatus and method for processing a physical layer protocol convergence (PLCP) header. In one embodiment, a wireless device includes a PLCP header processor. The PLCP header processor is configured to: process a physical layer header, process a check value based on the physical layer header, and process an error correction code based on the physical layer header and the check value. A concatenation of the physical layer header, check value, and error correction code the PLCP header processor is configured to process consists of a number of information bits that is an integer multiple of a number of information bits per symbol used to encode the PLCP header.

Abstract: A 3D video generation device may be operable to encode a plurality of regions of a captured 3D video frame. The plurality of regions may be associated with different depths. The encoding may apply varying error protection to the plurality of regions based on the associated different depths. The 3D video generation device may identify one or more regions of interest from the plurality of regions. Different levels of error protection may be applied to the region(s) of interest and to other region(s). The error protection may comprise a forward error correction (FEC). A higher level of the error protection may comprise an error-correcting code that is longer than an error-correcting code which is utilized for providing a lower level of the error protection.

Abstract: A method of generating a parity check matrix for iterative decoding of a linear block code includes: determining a set of parity check vectors for the linear block code; ordering according to Hamming weight non-zero parity check vectors of the set; selecting a criterion for generating the parity check matrix; and building the parity check matrix by incrementally selecting according to the criterion a parity check vector for each consecutive row of the parity check matrix, wherein the parity check vector is selected from the ordered non-zero parity check vectors remaining in the set.

Abstract: In one aspect, a sub-packet error correction method includes receiving a data packet, segregating the data packet into sub-packets, and encoding the sub-packets using an erasure code for transmission over a network, and receiving the encoded sub-packets, decoding the sub-packets, and combining the decoded sub-packets to reconstruct the data packet. In some embodiments, the data packet is received at a first proxy server for transmission over a lossy network, the encoded sub-packets received at a second proxy server over the lossy network.

Abstract: Provided is a method for transmitting data in a communication or broadcasting system using a linear block code by generating a codeword by encoding input information data bits, interleaving the codeword; outputting modulation signal-constituting bits by bit-mapping the interleaved codeword using a bit-mapping table predetermined depending on a modulation scheme and a coding rate, outputting a modulation signal by modulating the modulation signal-constituting bits and transmitting the modulation signal via a transmit antenna.

Abstract: Formulaic flexible collision-free memory accessing for parallel turbo decoding with quadratic polynomial permutation (QPP) interleave. A means is presented by which any desired number of parallel implemented turbo decoding processors can be employed to perform turbo decoding that has been performed using a QPP interleave. This approach is presented to allow an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) to perform decoding of a turbo coded signal while still using a selected embodiment of a QPP interleave. In addition, a collision-free memory mapping, (MOD,C,W) provides more freedom for selecting the particular quadratic polynomial permutation (QPP) interleave (?) that satisfies a parallel turbo decoding implementation with any desired number of parallel implemented turbo decoding processors.

Abstract: Low-Density Parity-Check (LDPC) codes offer error correction at rates approaching the link channel capacity and reliable and efficient information transfer over bandwidth or return-channel constrained links with data-corrupting noise present. They also offer performance approaching channel capacity exponentially fast in terms of the code length, linear processing complexity, and parallelism that scales with code length. They also offer challenges relating to decoding complexity and error floors limiting achievable bit-error rates.

Abstract: A digital broadcasting system which is robust against an error when mobile service data is transmitted and a method of processing data are disclosed. The mobile service data is subjected to an additional coding process and the coded mobile service data is transmitted. Accordingly, it is possible to cope with a serious channel variation while applying robustness to the mobile service data.

Abstract: A transmission system carrying out sending and receiving of OTU frames has a first transmission device carrying out the sending of an OTU frame, and a second transmission device carrying out the receiving of the OTU frame. The first transmission device calculates BIP-8 for an objective calculation range preset in the OTU frame, inserts the calculation result into the OTU frame, and sends the same. The second transmission device calculates BIP-8 from the received OTU frame for the same objective calculation range as the first transmission device, compares the calculation result with the BIP-8 sent from the first transmission device, and detects any presence of transmission error. The calculation range is set in terms of one of an area including OPU only and an area at least including an arbitrary byte of OTU/ODU overhead.

Abstract: Methods and systems for transmitting and receiving data include reverse concatenated encoding and decoding. Reverse concatenated decoding includes inner decoding the encoded stream with an inner decoder that uses a low-complexity linear-block code to produce an inner-decoder output stream, outer decoding the inner-decoder output stream with an outer decoder that uses a low-density parity-check code to produce an information stream, and iterating extrinsic bit reliabilities from the outer decoding for use in subsequent inner decoding to improve decoding performance.

Abstract: Apparatus and methods store stream-based error recovery data for a memory array, such as a NAND flash array. Conventionally, data is block coded per industry specification and stored in the memory array. Within the limits of the block code, this technique provides for correction of errors. By applying a stream-based inner code, that is, concatenating the outer block code with an outer code, the error correction can be further enhanced, enhancing the reliability of the device. This can also permit a relatively small-geometry device to be used in a legacy application.

Abstract: Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

Abstract: A transmitter/receiver system for high data transfer in a wireless communication system includes a physical layer processor that comprises an FEC coder, a demultiplexer and a plurality of modem processors. The FEC coder applies error correction codes to the high data rate signal. Thereafter, the demultiplexer distributes portions of the coded high data rate signal to the modem processors. Each modem processor processes its respective portion of the coded signal for transmission in an independent channel.

Abstract: Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.

Abstract: Transmitters and receivers deal with streams of data, wherein the receiver is expected to begin using received data before receiving all of the data. Concurrent streams are sent and FEC coding is used with the streams and done as an aggregate. The transmitter performs FEC operations over the plurality of streams, wherein source blocks from at least two streams logically associated into a jumbo source block and FEC processing is performed to generate one or more jumbo repair block from the jumbo source block. Each of the source blocks comprises one or more source symbols from their respective stream. The jumbo source symbols can be of constant size and are suitably aligned along size boundaries that make processing efficient. Each source symbol need not be the same size, and the number of source symbols from each stream in a jumbo source block need not be the same value across streams.

Abstract: A sequence of symbol operations (a “schedule representation”) within a data storage device, wherein the operations are those used to process encoding or decoding operations of a forward error correction code (an “FEC code”) upon an arbitrary block of data of a given size (where size can be measured in numbers of symbols). The method is such that the schedule representation can be used to direct the processing of these operations upon a block of data in a way that is computationally efficient. Preferably, the same method can be applied to represent schedules derived from multiple different algorithms for the encoding or decoding of a code or for multiple different codes.