Abstract: A pre-decoded tail-biting convolutional code (TBCC) decoder and a decoding method thereof are provided. The decoder includes a pre-decoder, a storage module, and a control module. The pre-decoder receives a current state, a neighboring state, and a current path status corresponding to sequential data encoded in TBCC, generates predicted decoded bits, and determines whether states corresponding to minimum path metrics of neighboring stages are in continuity according to the current state, the neighboring state, and a current path status. The storage module is connected to the pre-decoder and stores the predicted decoded bits. The control module is connected to the storage module and the pre-decoder. In addition, the control module selects to output the decoded bits from the storage module when the continuity between the states corresponding to the minimum path metrics of the neighboring stages reaches a truncation length.

Abstract: A method, apparatus and program. The method comprises: receiving a signal comprising a sequence of encoded symbols, each corresponding to one of a plurality of possible states; for each symbol in the sequence, determining a set of state metrics each representing a probability that the respective symbol corresponds to each of the plurality of states; and decoding the signal by processing runs of recursions, using runs of forward recursions and runs of reverse recursions. The decoding comprises performing a plurality of repeated iterations over the sequence, and for each iteration: dividing the sequence into a plurality of smaller windows, processing the windows using separate runs of recursions, and performing an associated warm-up run of recursions for each window.

Abstract: The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.

Abstract: One embodiment of the present invention relates to a method of detecting potential performance degradation caused by neighboring identical scrambling codes. The method includes detecting an existence of identical scrambling codes in received signals from different cell at the user equipment, and selectively eliminating one or more signals from consideration in processing of received signals based upon the detection. The invention also includes a receiver configured to detect potential performance degradation caused by neighboring identical scrambling codes. The receiver includes a detection component configured to detect an existence of identical scrambling codes in received signals from different base stations at the user equipment, and an elimination component configured to selectively eliminate one or more signals from consideration in processing of received signals based upon the detection by the detection component.

Abstract: Methods and devices are disclosed for encoding and decoding convolutional codes in a communication system. In various embodiments of the disclosure, a codeword comprises message data and parity data. A convolutional codeword is generated by multiplying the message data and the parity data with a convolutional polynomial. The convolutional codeword may be decoded by a convolutional code decoder that uses the convolutional polynomial and a maximum likelihood divisor to obtain a maximum likelihood message from the convolutional codeword.

Abstract: According to an embodiment, an information processing apparatus includes: a receiving unit that receives a fragment packet; an extracting unit that extracts checksum information of which packet has not been subjected to the fragmentation process, and causes the checksum information to be stored in a checksum storage unit; a calculating unit that performs a checksum calculation on each of the plurality of received fragment packets, integrates a calculation result of each fragment packet, and causes an integrated calculation result to be stored in a calculation result storage unit; and a determining unit that determines whether or not there is an error in a packet obtained as a result of combining based on the integrated calculation result stored and the checksum information stored.

Abstract: An error correction method corrects and replaces erroneous digital signal samples (having N companded bits) in a receiver after ascertaining by parity check that a sample is erroneous. The method chooses M MSBs where M is less than or equal to N, and produces M test samples, each test sample being obtained by inverting a single bit from the M bits, keeping other bits unaltered. Each test sample is expanded and passed through a selected low pass filter (e.g., 15 kHz) to obtain a filtered output and a differential value between the test sample and its filtered output. The test sample producing the least differential value is chosen to replace the erroneous signal sample. The technique is applicable in NICAM demodulators receiving 14 bit sample signals (at 32 kHz) companded to (N) 10 bits from which (M) 6 MSB parity encoded bits are chosen for producing test samples.

Abstract: Embodiments of the present invention provide a video data transmission processing method, a video data sending processing method, an apparatus, and a network system. The data transmission processing method includes: receiving a source stream sent from a source transmission network to a target transmission network; performing, according to respective packet loss rates of the source transmission network and the target transmission network as well as error tolerance aid information corresponding to the source stream, error tolerance coding processing on the source stream to obtain an error tolerance stream; and sending the obtained error tolerance stream to the target transmission network.

Abstract: Methods for data transmission management used in a transmitter are provided. The method comprises the steps of: encoding M uncoded packets into N coded packets with Q-packet error correction capability using concatenated encoding, where M?N, and Q?1; sequentially transmitting a set or all of the N coded packets to the at least one receiver; receiving at least one feedback information from the at least one receiver, wherein the at least one feedback information comprises at least one ACK or NACK information for indicating decoding statuses of the transmitted coded packets, each of the transmitted coded packets having one of the decoding statuses corresponding thereto; and determining whether to perform a retransmission procedure to retransmit a dedicated packet to the at least one receiver according to collected ACK/NACK included in the feedback information.

Abstract: A method of encoding data using low density parity check (LDPC) code defined by a m×n parity check matrix is disclosed. More specifically, the method includes encoding input source data using the parity check matrix, wherein the parity check matrix comprises a plurality of z×z sub-matrices of which row weights and column weights are ‘0’ or ‘1’.

Abstract: A method of transmitting data using a Convolutional Turbo Code (CTC) encoder by a transmitting end in a mobile communication system includes providing first encoded bits by encoding input data bits inputted to two input ports of the CTC encoder, interleaving the input data bits using 4 CTC interleaver parameters (P0, P1, P2, and P3) corresponding to a size of the input data bits, providing second encoded bits by encoding the interleaved input data bits, and transmitting the input data bits, the first encoded bits, and the second encoded bits.

Abstract: Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit.

Abstract: A method and apparatus for applying Forward Error Correction (FEC) in 66b systems. For a user data, the apparatus uses a method comprising the steps of generating one or more data blocks using a 66b code format and the user data; generating one or more FEC parity blocks using the 66b code format, wherein the parity is calculated over the data blocks; and generating an FEC codeword using the data blocks and the FEC parity blocks.

Abstract: A method of encoding/decoding data for storage in and retrieval from a flash memory device, can be provided by generating a first error correction code on a combination of first user data to be stored in a first logical unit of storage in the flash memory device and padding data that is derived from second user data and an associated second error correction code stored in a second logical unit of storage in the flash memory device that is directly adjacent to the first logical unit of storage. The first user data and the first error correction code can be stored in the first logical unit of storage.

Abstract: A min-sum processing unit executes, on input data, check node processing for each row of a check matrix and variable node processing for each column of the check matrix. When the decoded result involves an error, a detection unit detects a bit of a low degree of reliability from the decoded result. An identifying unit identifies a row and a column of a low degree of reliability in the check matrix on the basis of the bit of the low degree of reliability detected. The min-sum processing unit executes, on the decoded result, check node processing on the row identified as well as variable node processing on the column identified.

Abstract: Systems, methods, and other embodiments associated with LDPC decoder architectures are described. According to one embodiment, an apparatus includes a super-parity-check matrix that corresponds to at least a portion of a low density parity check (LDPC) code matrix. The super-parity-check matrix is coupled to a high throughput LDPC decoder and a low throughput LDPC decoder, The super-parity-check matrix includes n parity check matrices, each including x rows corresponding to x check node processing elements and y columns corresponding to y bit node processing elements. Thus, the super-parity-check matrix comprises nx rows and ny columns. The numbers n, x, and y are selected so that ny codeword can be processed in single time unit by the high throughput decoder and y codeword bits can be processed in a single time unit by the low throughput decoder.

Abstract: This disclosure relates to message encoding. Once claim recites an apparatus comprising: electronic memory for buffering identifying data associated with an entity or client; and a multi-purpose electronic processor programmed for: modifying the identifying data with a random or pseudo-random signal; error correction encoding the modified identifying data; and transforming a plural-bit message with the error correction encoded, modified identifying data to produce a key for use with message encoding. Of course, other claims and combinations are provided as well.

Abstract: An apparatus and a method are provided for encoding and decoding in a broadcasting/communication system using a Low Density Parity Check (LDPC) code. A weight-1 position sequence conversion procedure is performed on an initial parity check matrix. Shortening is applied on an information word. A codeword is generated by LDPC encoding the information word using a parity check matrix generated by performing the weight-1 position sequence conversion procedure. Puncturing is then applied to the codeword.

Abstract: The present invention discloses a method and system for detecting the frame boundary of a data stream received in Forward Error Correction layer in the Ethernet. The present invention can increase the speed of frame boundary detection and the speed of frame synchronization without adding any overheads of hardware.

Abstract: In one embodiment, a coding method that uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving.

Abstract: Methods and apparatuses are provided for achieving maximum diversity gain through channel coding based on a Low-Density Parity-Check (LDPC) code in a multiple antenna communication system. A method includes determining a parity-check matrix; generating a codeword using the parity-check matrix; puncturing a part of an information word; dividing a parity into a plurality of partial parities based on a number of transmit antennas; transmitting an unpunctured part of the information word and a partial parity over a first antenna; and transmitting at least one other partial parity over at least one other transmit antenna.

Abstract: A string of K initial symbols is encoded with a code of the parity check type. The K initial symbols belong to a Galois field of order q strictly greater than 2. The code is defined by code characteristics representable by a graph (GRH) comprising N?K first nodes (NCi), each node satisfying a parity check equation defined on the Galois field of order q, N packets of intermediate nodes (NITi) and NI second nodes (NSSi), each intermediate node being linked to a single first node and to several second nodes by way of a connection scheme. The string of K initial symbols is encoded by using the said code characteristics and a string of N encoded symbols is obtained, respectively subdivided into NI sub-symbols belonging respectively to mathematical sets whose orders are less than q, according to a subdivision scheme representative of the connection scheme (H).

Abstract: An error correction code block including dual-syndrome generators, which may process a plurality of successive code word without latency, is configured to calculate syndrome values of a corresponding even numbered codeword among the plurality of code words by using one of the dual-syndrome generators, and is configured to calculate syndrome values of a corresponding odd numbered codeword among the plurality of code words by using the other of the dual-syndrome generators.

Abstract: The embodiments of the present invention provide a method of constructing parity-check matrix of LDPC code. The method comprises the following steps of: constructing a MB×NB base matrix B for an LDPC code with code rate R and code length N, wherein MB=M/K, NB=N/K, M=N (1?R), K is the expansion factor of the base matrix, K??, and ? is the set of the common factors of M and N; and replacing the elements of the base matrix B with a K×K matrix, and expanding the base matrix B into a parity-check matrix H with size of M×N for the encoding or decoding of the LDPC code. An encoding method and apparatus of LDPC code are also provided by the embodiments of the present invention. The technical solutions provided by the embodiments of the present invention can construct LDPC codes with good performance, solve the storage problem of the parity-check matrix, and effectively reduce the implementation complexity of the encoding apparatus.

Abstract: Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data.

Abstract: A semiconductor storage device, a method of controlling the same, and an error correction system allow reduction in power consumption and circuit scale without detriment to error correction capability. An error correction code (ECC) circuit of a solid state drive (SSD) performs first error correction on read data using a first error correction code (Hamming code), and further performs second error correction on the result of the first error correction using a second error correction code (BHC code). Furthermore, the ECC circuit performs third error correction on the result of the second error correction using a third error correction code (RS code).

Abstract: Methods and apparatus are provided for controlling decoding in a receiver. A codeword is received and decoded. It is determined whether the decoding is a decoding success or a decoding failure. A number of unreliable bits of the codeword is determined when the decoding is the decoding failure. Iterative decoding is performed when the number of unreliable bits is less than a first threshold value.

Abstract: The embodiments of the invention disclose a method and a device for decoding an RS code, the method comprising: receiving bit reliability information of the RS code output by a channel, performing a hard decision on the bit reliability information to obtain a hard-decision result value sequence; determining a type of an error of the hard-decision result value sequence according to an initial check array corresponding to an encoding mode of the RS code; according to preset corresponding relationships between types of errors of the hard-decision result value sequence and error-correcting modes capable of correcting the errors, determining an error-correcting mode corresponding to the type of the error of the hard-decision result value sequence, and performing a bit error correction on the hard-decision result value sequence according to the determined error-correcting mode; outputting the hard-decision result value sequence after the bit error correction as a decoding result.

Abstract: In one embodiment, the present patent application comprises a method and apparatus to generate low rate protographs from high rate protographs, comprising copying a base graph; permuting end points of edges of a same type in copies of the base graph to produce a permuted graph; and pruning systematic input nodes in the permuted graph and the edges connected to them. In another embodiment, the present patent application comprises a method and apparatus to generate high-rate codes from low-rate codes, comprising puncturing a subset of codeword bits, wherein the step of puncturing a subset of codeword bits comprises regular-irregular puncturing the subset of codeword bits, random puncturing variable nodes, or progressive node puncturing variable nodes to obtain a desired code from a preceding code.

Abstract: In a battery management system, error detection data is generated for various configuration parameters used by the battery management system. The error detection data is compared against corresponding error detection data previously generated during production or development of a battery pack or battery pack application. Based on the comparison, an appropriate action can be taken.

Abstract: The embodiments include an error correction processing unit and an error correction history recording unit. The error correction processing unit performs an error correction process based on data read from a non-volatile semiconductor memory and a second-step error correction code corresponding to the data. The error correction history recording unit records error correction history indicating whether first error correction is successful through the first error correction process, in association with unit data. When error correction history of target unit data to be read indicates that correction is not successful, the second error correction process is executed without executing the first error correction process.

Abstract: Techniques to support low density parity check (LDPC) encoding and decoding are described. An apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to encode or decode a packet based on a base parity check matrix and a set of lifting values. In a particular embodiment, the set of lifting values is limited to lifting values that are each a different power of two. The memory is configured to store parameters associated with the base parity check matrix.

Abstract: RLL encoding is performed to generate RLL data, including by: using a first run-length constraint and using a second run-length constraint. G is a maximum number of zeroes between two ones, I is a maximum number of zeroes between two ones in either a first subsequence or a second subsequence where the first subsequence includes odd bits associated with a DC-balanced sequence and the second subsequence includes even bits associated with the DC-balanced sequence, and S is a number of bits per symbol associated with a systematic ECC. The RLL data is encoded using the systematic ECC to obtain ECC data which includes one or more data symbols and one or more parity symbols. The data symbols and the parity symbols are interleaved.

Abstract: An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.

Abstract: A method for data storage in a memory including multiple memory cells arranged in blocks, includes storing first and second pages in respective first and second groups of the memory cells within a given block of the memory. A pattern of respective positions of one or more defective memory cells is identified in the first group. The second page is recovered by applying the pattern identified in the first group to the second group of the memory cells.

Abstract: A combination of repeaters and relays is used to improve the data throughput for user equipment (“UE”) near the cell edge in a LTE network. Amplify-and-forward repeaters and decode-and-forward relays enhance the down-link and up-link, respectively. Relay assistance on the up-link occurs when the evolved Node B (“eNB”) requests a retransmission (HARQ) from the UE at which point the UE and relay transmit simultaneously in a cooperative fashion. The quality of the up-link signal received by the eNB is improved due to a favorable channel through the relay. An analysis shows that relay assistance improves the throughput for a cell-edge user when the average delay per data transport block is allowed to increase.

Abstract: A method of handling a retransmission of a hybrid automatic repeat request scheme for a receiver in a communication system is disclosed. The method comprises receiving a first payload from a transmitter in the communication system, and feeding back a resource index to the transmitter, to indicate a size for a second payload in the next reception, when the receiver is unsuccessful to decode the first payload into a plurality of information bits, wherein the transmitter encodes the plurality of information bits into the first payload by using an error correction code.

Abstract: A computer-implemented system and method for off-line delivery of content through an active screen display are provided. A processor includes an encoding application to assemble and encode digitally-stored content into encoded content, and to interleave the encoded content with a signal conveying a live screen representation. The live screen representation includes output of a user interface for applications executing on the processor. An active screen display is coupled to the processor over a physical display interface connection. The active screen display includes a runtime application to identify the encoded content within the signal on the active screen display and to decode the encoded content into decoded content. The active screen display further includes an offline application to unilaterally display the decoded content on the active screen display without use of the processor and in an absence of the live screen presentation.

Abstract: An encoding apparatus includes a dividing unit that divides an input signal bit sequence into data blocks and an encoding unit that applies error correction encoding to the data blocks to generate code blocks decodable by repetitive decoding calculations for estimating the reliability of signal bits for a plurality of times and a generation unit that generates redundant bits by performing bit calculations between data blocks of each set combining the divided data blocks; and an output unit that outputs the generated code blocks and redundant bits.

Abstract: A method of decoding a block with a Soft Output Viterbi Algorithm (SOVA) using a trellis representation and a sliding window wherein each position of the sliding window has a path determination stage at one end of the sliding window and a symbol decision stage at another end of the sliding window is disclosed. The method comprises determining, for each path determination stage and for each node of the path determination stage, a surviving path (including a surviving path input symbol and a surviving decision stage node) and a concurrent path (including a concurrent path input symbol and a concurrent decision stage node) based on path metrics. A path metric disparity value is calculated and stored for each node.

Abstract: A data processing device includes: an error corrector configured to perform demodulation and error correction on a received signal to output error-corrected data, the received signal transmitting packets which include packet identifiers and are encrypted by broadcast encryption; and a transport stream generator configured to generate a transport stream based on the error-corrected data. The error corrector selects the packets including a set packet identifier, and outputs the selected packets as the error-corrected data.

Abstract: A method for turbo-encoding a block of data including: receiving data bits of the block of data; masking irrelevant data bits by a masking unit, wherein irrelevant data bits are data bits that regardless of their value do not affect a final state of an interleaved convolutional encoder of a turbo encoder; calculating a last state of the interleaved convolutional encoder based on relevant data bits provided by the masking unit; wherein the calculating of the last state of the interleaved convolutional encoder is initialized before receiving the entire block of data; finding an initial state of the interleaved convolutional encoder based on the last state of the interleaved convolutional encoder; wherein the initial state of the interleaved convolutional encoder equals a final state of the interleaved convolutional encoder; initializing the interleaved convolutional encoder to the initial state; and turbo-encoding the interleaved data bits by the interleaved convolutional encoder.

Abstract: A wireless communication infrastructure entity including a transceiver coupled to a controller configured to generate parity bits based on an information word. The controller is also configured to encode the parity bits based on a communication configuration, e.g., symbol information, wherein the encoded parity bits are combined with the information word for transmission by the transceiver. A user terminal in receipt of the information word includes a controller configured to determine the communication configuration based on a set of configuration indicator bits used to encode the parity bits.

Abstract: A method for detecting validity of downlink control information in telecommunication user equipment and a decoder and baseband receiver to perform the method are provided. The object of avoiding falsely detecting payload data and misinterpreting them is achieved by reverse encoding a bit output sequence of a Viterbi decoder; determining hard bits from a soft-bit input sequence of the decoder; determining a bit count of real received bits; comparing the reverse encoded bit stream to the determined hard bit stream and counting the number of mismatches to obtain an error count; comparing a bit error rate which is defined as a quotient of the error count and the bit count against a predefined threshold value; and rejecting the payload as invalid if said bit error rate is above said threshold value, even if a cyclic redundancy check of the payload gives a correct result.

Abstract: The present invention improves communication systems by providing a virtual binary erasure channel over a frame-based data exchange infrastructure, through a combination of time diversity mechanisms with bit-based interleaving agents. The interleaving agents are judiciously positioned in the data processing path to provide benefits to the forward error correction functions of the communication system. The invention thus allows for a significant reduction of the complexity of the error correction facilities of a communication system such as a DVB-SH system, by allowing the efficient use of a low-complexity binary based decoder.

Abstract: A user equipment (UE) comprising at least one component configured to decode a tail-biting convolution code (TBCC) by calculating a plurality of paths that correspond to a plurality of encoder starting states and trace back at least one of the calculated paths per at least one iteration until a trace-back convergence check (TCC) condition fails, wherein the TCC condition fails if a starting state of a first traced back path among the calculated paths is not equal to a starting state of a subsequent traced back path.

Abstract: A digital broadcast transmitting and a method of processing broadcast data in a digital broadcast transmitting system are disclosed. The method includes randomizing mobile service data; RS encoding and CRC encoding the randomized mobile service data to build an RS frame; dividing the built RS frame into L (L>1) number of portions and adding K bytes (K?0) of dummy data to one of the portions; encoding data in the portions at a code rate of 1/H (H>1); first interleaving the encoded data; mapping the first interleaved data into data groups and adding known data sequences and transmission parameters to each of the data groups, deinterleaving data of the data groups; second interleaving the deinterleaved data; and transmitting a transmission frame including the second interleaved data.

Abstract: An apparatus and method for producing error correction code and error correction decoding are provided. The method for producing error correction code includes generating an asymmetric matrix by arranging input data bits in a matrix of a predefined size and adding a zero bit column and/or a zero bit row, each of the column and the row consisting of zero bits, to the matrix; primarily encoding the asymmetric matrix by adding one or more parity bits to each row; and secondarily encoding the primarily encoded matrix by adding one or more parity bits to each column of the encoded matrix.

Abstract: An error code pattern generation circuit includes a first storage unit configured to store at least one bit of an error code, and output error data for a first time period; and a second storage unit configured to store at least one remaining bit of the error code and output the error data for a second time period which is different from the first time period.

Abstract: In an embodiment, a data scramble/descramble circuit for a memory may employ multiple scramble circuits that may provide randomization of data across both rows and columns of a memory array. The first circuit may receive at least a portion of the address of the row, and may produce an output value by logically operating on the portion of the address. The second circuit may receive the output of the first circuit (or a portion thereof) as a seed, and may scramble the data to be written to memory. In one embodiment, a least significant portion of the address may be operated upon by the first circuit (e.g. the least significant byte), which may be most likely to change from row to row as compared to other portions of the address.