Abstract: A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.

Abstract: Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. Variable modulation encoding of LDPC coded symbols is presented. In addition, LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an LDPC variable code rate and/or modulation signal whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. Some embodiments employ a common constellation shape for all of the symbols of the signal sequence, yet individual symbols may be mapped according different mappings of the commonly shaped constellation; such an embodiment may be viewed as generating a LDPC variable mapped signal. In general, any one or more of the code rate, constellation shape, or mapping of the individual symbols of a signal sequence may vary as frequently as on a symbol by symbol basis.

Abstract: A stopping method for an iterative signal processing includes a first step of receiving the state signatures generated by the iterative signal processing. A next step includes accumulating the state signatures into a stopping index variable. A next step includes stopping iterative decoding when the stopping index variable is less than a predetermined threshold.

Abstract: The present disclosure discloses a method and a device for bandwidth self-adapting data ranking protection. The method comprises: performing redundancy protection computation on a data block to be transmitted so as to generate a redundant code of the data block, and setting a priority for the redundant code; determining whether bandwidth occupied by a redundant code with a highest priority is greater than current residual bandwidth; if the bandwidth occupied by the redundant code with the highest priority is not greater than the current residual bandwidth, carrying the redundant code with the highest priority in the current residual bandwidth; otherwise, according to a descending order of the priority, searching in residual redundant codes for a redundant code whose data amount is less than or equal to the current residual bandwidth, and carrying a found redundant code in the current residual bandwidth. The present disclosure improves the error tolerance of a system.

Abstract: The present invention discloses a method for recovering lost media data packets, and the method includes: a stream media server sending and buffering a media data stream; a client receiving and buffering the media data stream, and sending a negative-acknowledge (NACK) message to the stream media server when the client detects that the buffered media data stream has lost media data packets, the stream media server setting forward error correction (FEC) coding redundancy and acquiring the media data packets needing to be recovered from the media data stream buffered in itself, encoding the media data packets needing to be recovered into FEC data according to the FEC coding redundancy, and sending the FEC data to the client; with combination of the received FEC data and the media data stream buffered in the client itself, the client recovering the lost media data packets in the media data stream.

Abstract: A transmitter for broadcasting data in a broadcasting system that improves the decoding quality, if needed, comprises a data input, and an encoder for error correction code encoding the input data words into codewords, a codeword comprising a basic codeword portion and an auxiliary codeword portion, wherein said encoder is adapted for generating said basic codeword portion from an input data word according to a first code and for generating said auxiliary codeword portion from an input data word according to a second code, said basic codeword portion being provided for regular decoding and said auxiliary codeword portion being provided as incremental redundancy if regular decoding of the codeword by use of the basic codeword portion is erroneous. Further, the transmitter comprises a data mapper for mapping the codewords onto frames of a transmitter output data stream, and a transmitter unit for transmitting said transmitter output data stream.

Abstract: A terminal apparatus and a response signal transmitting method wherein the system transmission efficiency can be improved by devising a bundling rule. In a terminal (200), a PDSCH receiving unit (208) receives first and second code words, which comprise code word block (CWB) groups to be mapped to the respective ones of a plurality of downstream unit bands, and detects errors of the CWBs; and an A/N bundling unit (216) transmits, based on a bundling rule in which each CWB is associated with any one of first and second bundling groups, a single bundle of response signals into which the error detection results are bundled for each bundling group. According to the bundling rule, at least one of the first and second bundling groups includes both the CWB belonging to the first code words and the CWB belonging to the second code words.

Abstract: The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another.

Abstract: A digital communication decoding method for low-density parity-check coded messages. The decoding method decodes the low-density parity-check coded messages within a bipartite graph having check nodes and variable nodes. Messages from check nodes are partially hard limited, so that every message which would otherwise have a magnitude at or above a certain level is re-assigned to a maximum magnitude.

Abstract: In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, i a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi?1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi?1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol block Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code.

Abstract: In a communication device that is operative to perform decoding, a log-likelihood ratio (LLR) circuitry operates to calculate LLRs corresponding to every bit location within a received bit sequence. This received bit sequence may include a header and a data portion (both of which may be included within a frame that also includes a preamble). The header is composed of information bits, a duplicate of those information bits (such as may be generated in accordance with repetition encoding), and redundancy bits. The header includes information corresponding to frame or data including frame length, a code type by which the data are encoded, a code rate by which the data are encoded, and a modulation by which symbols of the data are modulated. Once the header has been decoded, then the data corresponding thereto is decoded by a block decoder circuitry to make estimates of that data.

Abstract: A method and a device for communicating data via noisy media in order to improve the protection against errors in the transmission of information via a noisy channel or transmission medium. The method and improved device involve using a new type of structure of the parity matrix for the low density parity check codes technology in the coding and decoding of data, which improves the correction of errors without increasing the complexity of the hardware implementation.

Abstract: There is provided a security communication method between devices to tighten the security of data by changing CRC polynomials and scramble codes in the communication between the devices. The security communication method between devices, which is a communication method between a master device and one or more slave devices, comprises the steps of: a) storing two or more CRC polynomials and two or more scramble codes in each of the master device and the one or more slave devices; b) allocating the two or more CRC polynomials and the two or more scramble codes to each of the one or more slave devices by the master device; and c) performing each data transmission between the master device and the one or more slave device, based on the CRC polynomials and scramble codes allocated in the step b).

Abstract: Some embodiments provide a method for encoding digital video. The method receives a digital video image. The method encodes the digital video image. The method generates error correction information for the encoded digital video image using only data from the encoded digital video image. The method transmits the generated error correction information with the encoded digital video image. In some embodiments, the method determines a level of error protection for the encoded digital video image based on an image type of the encoded digital video image.

Abstract: Some embodiments include apparatus and methods for encoding message information. Such apparatus and methods can include using a parity check matrix of a low-density parity check (LDPC) code to generate a first matrix having an upper triangular sub-matrix. Parity information to encode the message information can be generated based on the first matrix if a total number of rows of the upper triangular sub-matrix is equal to the rank of the parity check matrix. If the total number of rows of the upper triangular sub-matrix is less than the rank of the parity check matrix, then a triangularization operation can be performed on a second sub-matrix of the first matrix to generate a second matrix. Parity information to encode the message information can be generated based on the second matrix. Other embodiments including additional apparatus and methods are described.

Abstract: When decoding a set of symbols to be decoded, several data blocks representative of the set of symbols to be decoded are received by a decoding node of a communications network. The data blocks are encoded using an error correction code enabling a decoding by erasure. The decoding node performs the following steps: first selecting at least one of the data blocks, first determining first erasures, and checking whether the number of the first erasures is below a given threshold. In a case the check is positive, the decoding node performs first decoding by erasure of the set of symbols to be decoded. In a case the check is negative, the decoding node performs second selecting of at least one of the data blocks, second determining second erasures, and second decoding by erasure of the set of symbols to be decoded from the second erasures.

Abstract: Systems and methods are disclosed for communicating signals, by receiving a K-symbol-long input block from a 2m-ary source channel; encoding the input block into a 2m-ary non-binary low-density parity-check (LDPC) codeword of length N; and mapping each 2m-ary symbol to a point in a signal constellation comprised of 2m points, wherein a non-binary LDPC code is used as the component code for forward error correction in a coded modulation scheme capable of achieving optical fiber communication at rates beyond 100 Gb/s.

Abstract: An error correction code (ECC) decoder processing data read from a storage media includes a plurality of processing elements for detecting an error in at least one of a plurality of channel data, wherein the plurality of channel data is received via a plurality of channels, and wherein the plurality of processing elements are driven independently from the plurality of channels

Abstract: A receiver includes: a broadcast receiver receiving a receiver input data stream segmented into frames, wherein basic codeword portions of codewords are mapped onto the frames, a codeword including at least a basic codeword portion generated from an input data word according to a first code; a data demapper demapping the basic codeword portions; a decoder error correction code decoding the codewords into output data words of at least one output data stream in a regular decoding using the basic codeword portion in a codeword; a check unit checking if the regular decoding of a codeword is erroneous; a unicast request unit requesting, if the regular decoding of a codeword is erroneous, an auxiliary codeword portion of the erroneously decoded codeword for incremental redundancy in an additional decoding; a unicast receiver unit receiving an auxiliary codeword portion of the erroneously decoded codeword.

Abstract: An apparatus and method for mapping and demapping signals in a system using a Low Density Parity Check (LDPC) code are provided. In the method, LDPC codeword bits are written column-wise and read row-wise, substreams are generated by demultiplexing the read bits using a demultiplexing scheme, and bits included in each of the substreams are mapped to symbols on a signal constellation. The demultiplexing scheme is determined corresponding to a modulation scheme used in the signal transmitter, a length of the LDPC codeword, and a number of the substreams.

Abstract: A transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased. An encoding part subjects transport data to a block encoding process to form block encoded data. A modulating part modulates the block encoded data to form data symbols; and an arranging (interleaving) part arranges (interleaves) the block encoded data in such a manner that the intra-block encoded data of the encoded blocks, which include their respective single different data symbol, get together, and then supplies the arranged (interleaved) block encoded data to the modulating part. In this way, there can be provided a transmitter apparatus wherein a relatively simple structure is used to suppress burst errors without changing the block sizes of encoded blocks even when the number of modulation multi-values is increased.

Abstract: A readdressing decoder for QC-LDPC decoding including a memory, a controller and parallel processors is provided. The memory stores a QC-LDPC matrix including sub-matrices respectively addressed with a corresponding address. The controller readdresses each of the sub-matrices into divided matrices and defines each of the divided matrices into a first address group and a second address group. The controller further respectively transmits the divided matrices of the first address group and the second address group to the parallel processors to perform correction algorithm.

Abstract: A plurality error correction circuits connected with series includes a calculator circuit corrects the codeword when the determination results of a determining circuit indicate that the error correcting circuit at the present stage is to correct the codeword, and a determining circuit at a subsequent error correction apparatus determines whether the error correcting circuit at the subsequent stage is to correct the codeword when the determination results of the determining circuit indicate that the error correcting circuit at the present stage is not to correct the codeword.

Abstract: According to one embodiment, a Reed-Solomon decoder comprises an analyzer and a calculator. The analyzer analyzes a data frame and calculates a size of a last code word located at an end of a data portion, using information included in a header portion. The calculator calculates correction coefficients, using the size of the last code word, for correcting coefficients of an error locator polynomial and coefficients of an error value polynomial for the last code word in accordance with a difference between a base size of Reed-Solomon code words and the size of the last code word, before error detection for a code word located immediately before the last code word in the data portion begins.

Abstract: The present invention relates to channel decoding and provides ways and means for improved channel decoding of data frames. The frame has been channel encoded and transmitted to a receiver. The frame includes a part with information that is unknown to the receiver and another part with information for which the receiver generates at least one data hypothesis predicting its information content. The receiver performs a hypothesis-based decoding of the received encoded frame, wherein the at least one data hypothesis is used to improve a probability of successful decoding. The invention may advantageously be used to improve decoding of frames containing short control messages with fill bits, e.g. acknowledgement messages.

Abstract: An information processing apparatus includes a first parity production section for producing a first error detection code for detecting an error of data. A second parity production section produces a second error detection code for detecting an error of the data from the first error detection code. A first parity checking section detects an error of the retained data as a first error using the retained first error detection code. A second parity checking section detects an error of the retained data as a second error using the retained second error detection code. A control amount outputting section outputs, when an occurrence rate of a first error is equal to or lower than a first threshold value, a control amount for controlling a power supply voltage or a frequency using a second threshold value as a target value for an occurrence rate of a second error.

Abstract: A method for encoding a data word for writing an encoded data word in N cells of a solid state memory. Each of the N cells can be programmed in one of q nominal levels. The method includes encoding the data word as a codeword of a first codeword type having q symbol values or as a codeword of a second codeword type having (q-d) symbol values, d ? [1, . . . , q?1], depending on a state of the N cells.

Abstract: A method begins by a processing module storing data files utilizing a dispersed storage error coding function that includes a pillar width parameter and a decode threshold parameter. The method continues with the processing module determining whether to adjust the pillar width parameter based one or more memory performance characteristics. When the pillar width parameter is to be decreased, the method continues with the processing module identifying one or more pillars within a memory to delete to produce one or more identified pillars, identifying encoded data slices of one or more of the data files stored in the one or more identified pillars to produce identified encoded data slices, and deleting the identified encoded data slices.

Abstract: An apparatus and method for transmitting a signal using a bit grouping method in a wireless communication system is disclosed. Interleaved subblocks are maintained, and output bit sequences are modulated in due order after bit grouping and bit selection. The bit grouping method is advantageous in that bit reliability is uniformly distributed.

Abstract: A network communication device includes a host interface, which is coupled to communicate with a host processor, having a host memory, so as to receive a work request to execute a transaction in which a plurality of data blocks are to be transferred over a packet network. Processing circuitry is configured to process multiple data packets so as to execute the transaction, each data packet in the transaction containing a portion of the data blocks, and the multiple data packets including at least first and last packets, which respectively contain the first and last data blocks of the transaction. The processing circuitry is configured to compute a transaction signature over the data blocks while processing the data packets so that at least the first data block passes out of the network communication device through one of the interfaces before computation of the transaction signature is completed.

Abstract: A wireless system with Diversity processing is provided having Turbo Codes Decoders for computing orthogonal multipath signals from multiple separate antennas. The invention decodes multipath signals that have arrived at the terminal via different routes after being reflected from buildings, trees or hills. The Turbo Codes Decoder with Diversity processing increases the signal to noise ratio (SNR) more than 6 dB which enables the Wireless system to deliver data rates from up to 600 Mbit/s. Several pipelined decoders are used for iterative decoding of received data. A Sliding Window of Block N data is used for the pipeline operations.

Abstract: A method for enhancing data protection performance is provided. The method is applied to a personal computer that includes/is electronically connected to a memory device, and the memory device includes a Flash memory. The method includes: with regard to data to be written/programmed into the Flash memory of the memory device by the personal computer, generating at least one Error Correction Code (ECC) corresponding to the data, and storing the ECC into a file within the personal computer, wherein the file is stored in a storage of the personal computer; and when it is detected that an uncorrectable error of at least one portion of the data stored in the Flash memory occurs, performing error correction according to the ECC stored in the file, in order to correct the data stored in the Flash memory. An associated personal computer and a storage medium storing an associated driver are further provided.

Abstract: A cost function is obtained. For each of a plurality of groups of check nodes associated with low-density parity-check (LDPC) encoded data, the cost function is evaluated using information associated with a variable node and/or information associated with a check node. One of the groups of check nodes is selecting based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of check nodes.

Abstract: A method of processing broadcast data in a broadcast transmitting system includes randomizing mobile service data bytes; generating a Reed-Solomon (RS) frame; dividing the RS frame into RS frame portions; converting data bytes of the RS frame portions into data bits; encoding each converted data bit and outputting data symbols corresponding to the encoded data bits; interleaving the data symbols; converting the interleaved data symbols into data bytes; forming data groups including mobile service data corresponding to the converted data bytes, each of the data groups including known data sequences, signaling information, non-systematic RS parity data place holders and MPEG header data place holders; removing the non-systematic RS parity data place holders in the data groups and replacing the MPEG header data place holders in the data groups with MPEG header data to output mobile service data packets; and randomizing the MPEG header data in the mobile service data packets.

Abstract: A wireless communication device includes a transmitter configured to transmit a transport block with a sequence of bits wherein A is the number of bits, a first CRC coder configured to generate a first block of CRC parity bits on a transport block and to associates the first block of CRC parity bits with the transport block, wherein a number of CRC parity bits in the first block is L, a segmenting entity configured to segment the transport block into multiple code blocks after associating when A+L is larger than 6144, a second CRC coder configured to generate a second block of CRC parity bits on each code block and to associate a second block of CRC parity bits with each code block, and a channel encoder configured to encode each of the code blocks including the associated second block of CRC parity bits if A+L>6144.

Abstract: Provided is an error correction method for an optical communication system that transmits a transmission frame formed of information data added with an overhead and an error correction code, the error correction method including adjusting a size of an FEC redundant area of an FEC frame for storing client signals of different signal types in accordance with the client signals so that transmission rates of the FEC frame for the respective client signals have an approximately N-multiple relationship (N is a positive natural number). With this, it is possible to obtain an error correction method and device capable of providing a high-quality and high-speed optical communication system without performance degradation caused by jitter or the like and with the common use of circuits having a reduced circuit scale.

Abstract: This invention concerns packet recovery for real-time (live) multi-media communication over packet-switched networks like the Internet. Such communication includes video, audio, data or any combination thereof. The invention comprises forward error correction (FEC) algorithms addressing both random and burst packet loss and errors, and that can be adjusted to tradeoff the recoverability of missing packets and the latency incurred.

Abstract: A method for controlling an elementary parity node of a decoder for decoding non-binary LDPC codes or a code decoder using at least one non-binary parity constraint, and to the corresponding elementary parity node. The elementary parity node receives first and second input lists (U1,U2) having nm elements sorted in ascending or descending order, nm being greater than 1, and gives an output list (Uout) of nm, elements sorted in said ascending or descending order, nm, being greater than 1, each element of the output list (Uout) being the result of a computing operation ? between an element of the first input list (U1) and an element of the second input list (U2). A limited number of candidates is selected for each element of the output list to be generated so as to reduce the number of operations to be carried out in the elementary parity node.

Abstract: A digital receiving system, and a method of processing data are disclosed. The digital receiving system includes a receiving unit, a known sequence detector, and a channel equalizer. The receiving unit receives a broadcast signal including mobile service data and main service data. The known sequence detector detects known data linearly inserted in a data group. The channel equalizer performs channel-equalizing on the received mobile service data using the detected known data.

Abstract: A system and method for achieving higher data rates in physical layer devices. Costs imposed by large data rate increases represented by generational increases in Ethernet standards activities are avoided through physical layer device modifications that enable marginal increases in data bandwidth. Building-block reuse can be promoted through the selective use of clocking rate increase, increase in coding efficiency, and bit reuse.

Abstract: A method constructs a family of low-density-parity-check (LDPC) codes. The method includes identifying a code rate for an LDPC code in the family, identifying a protograph for the LDPC code, and constructing a base matrix for the LDPC code. The base matrix is constructed by replacing each zero in the protograph with a ‘?1’, selecting a corresponding value for an absolute shift for each one in the protograph based on constraining a number of relative shifts per column of the LDPC code to one and increasing a size of a smallest cycle in a graph of the LDPC code, and replacing each one in the protograph with the corresponding value.

Abstract: The invention relates to low density parity check decoding. A method for decoding an encoded data block is described. Encoded data block comprising data sub-blocks are stored. Decoding is performed in a pipelined manner using an irregular, block-structured parity check matrix, where at least two data sub-block matrices of the parity check matrix are read from and written in each of a plurality of clock cycles. The reading and writing of the data sub-blocks is evenly distributed between at least two area of a memory. The decoding is performed with shift values which eliminate cycles at or below a predetermined threshold length. An apparatus, computer program product and device are also described.

Abstract: A method and a circuit for generating cyclic redundancy checks. The method calculates a plurality of cyclic redundancy checks for a transport block with a plurality of information bits. At least one cyclic redundancy check among the plurality of cyclic redundancy checks is calculated based on a subset of information bits, and at least one information bit among the plurality of information bits is not within said subset of the information bits. In addition, a transport block cyclic redundancy check may be calculated based on all the information bits.

Abstract: Bose-Chaudhuri-Hocquenghem (BCH) decoder architectures which execute a plurality of different algorithms to calculate an error location polynomial. The multiple algorithms may be implemented in a storage controller for increased throughput per gate count. Codewords needing up to a threshold number of corrections may be processed via a first algorithm while those with a greater number of corrections may be processed via the second algorithm. In embodiments, the Peterson-Gorenstein-Zierler (PGZ) algorithm and the Berlekamp-Massey algorithm (BMA) are executed either serially or in parallel to increase throughput of the decoder.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: The present invention relates to a method for optimizing the FEC scheme comprising the steps of (a) receiving a batch of data packets designated for transmission; (b) choosing a number of divisors having no common denominators in accordance with the said batch of data packets; (c) organizing into blocks said batch of data packets a number of times in accordance with the number of divisors using said divisors; and (d) creating a FEC packet for each of said blocks.

Abstract: A computer implemented method for generating soft bit metric information of telecommunications systems employing differential encoding of data.

Abstract: A method may be provided to detect and correct data errors in a data system where a data message has been encoded with outer parity bits based on the data message using an outer encoding technique to provide an outer codeword and with inner parity bits based on the outer codeword using an inner encoding technique different than the outer encoding technique to provide an inner codeword. The method may include using the inner parity bits and an inner decoding technique corresponding to the inner encoding technique to perform inner decoding of the inner codeword. Responsive to performing inner decoding of the inner codeword without error, the data message may be extracted from a result of inner decoding the inner codeword without using the outer parity bits to decode the result of inner decoding the inner codeword. Related systems are also discussed.

Abstract: A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, comprising the steps of: generating tail input bits at each of two or more constituent encoders, including deriving the tail input bits from each of the two or more constituent encoders separately from a contents of shift registers within each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; puncturing one or more tail output bits such that 1/R output tail bits are transmitted for each of a plurality of trellis branches, wherein R is a turbo code rate employed by the turbo encoder during an information bit transmission. In yet another variation, the step of puncturing the tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits, only if they are sent from an output branch of one of the two or more constituent encoders that are used during information bit transmission.

Abstract: A process for generating a number representative of an analogue data source (ADS) in which during enrolment a distinctive characteristic of the ADS is measured to obtain physical data (PD). Part of the PD is used to generate a physical value (PV) representative of the ADS. An error correction algorithm (ECA) is applied to the PV to generate error correction data (ECD), which is transformed, using another part of the PD, to generate transform data. During subsequent regeneration of the PV, the distinctive characteristic is re-measured to generate a new set of PD, and a PV is generated using the same part of the PD physical data as was used during enrolment. ECD is generated by transforming the transform data, using the same part of the PD as was used to transform the ECD during enrolment. The ECA uses the regenerated ECD to correct errors in the PV representative of the ADS.