Quantum Well Patents (Class 257/14)
  • Patent number: 9696317
    Abstract: Novel Mn2+-doped quantum dots are provided. These Mn2+-doped quantum dots exhibit excellent temperature sensitivity in both organic solvents and water-based solutions. Methods of preparing the Mn2+-doped quantum dots are provided. The Mn2+-doped quantum dots may be prepared via a stepwise procedure using air-stable and inexpensive chemicals. The use of air-stable chemicals can significantly reduce the cost of synthesis, chemical storage, and the risk associated with handling flammable chemicals. Methods of temperature sensing using Mn2+-doped quantum dots are provided. The stepwise procedure provides the ability to tune the temperature-sensing properties to satisfy specific needs for temperature sensing applications. Water solubility may be achieved by passivating the Mn2+-doped quantum dots, allowing the Mn2+-doped quantum dots to probe the fluctuations of local temperature in biological environments.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: July 4, 2017
    Assignee: The Trustees of Princeton University
    Inventors: Haw Yang, Chih-Hao Hsia
  • Patent number: 9698566
    Abstract: An optical module includes: a semiconductor laser emitting laser light; an optical device having a butt joint interface; an optical amplifier amplifying the laser light passed through the optical device; an equivalent resonator length adjustor inserted between the optical amplifier and the optical device; a wavelength spectrum measuring device measuring a wavelength of light output from the optical amplifier; and a refractive index adjustment circuit controlling a current applied to the equivalent resonator length adjustor based on a result of measurement performed by the wavelength spectrum measuring device to adjust a refractive index of the equivalent resonator length adjustor. Parasitic oscillation light in a plurality of Fabry-Perot modes is generated as the butt joint interface is one of reflection ends.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: July 4, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventor: Kazuhisa Takagi
  • Patent number: 9691802
    Abstract: Provided is an image-acquisition device including a first image-acquisition surface including a photoelectric conversion film capable of subjecting incident light to photoelectric conversion while transmitting some of the incident light; a second image-acquisition surface including a photoelectric conversion layer that subjects the incident light transmitted by the first image-acquisition surface to photoelectric conversion; and a polarizing filter that is disposed between the two image-acquisition surfaces and that extracts polarization information from the incident light transmitted by the first image-acquisition surface.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: June 27, 2017
    Assignee: OLYMPUS CORPORATION
    Inventors: Masao Sambongi, Kosei Tamiya
  • Patent number: 9691033
    Abstract: A quantum computer comprises of at least one qubit formed from holes created with acceptor atoms (10) in crystalline silicon (12) and a pair of gates (14, 16) located above the acceptor atoms (10) to apply direct electric field and alternating electric field for switching, manipulating the qubit such that quantum information resulting from being manipulated is stored from decoherence.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: June 27, 2017
    Assignee: Newsouth Innovations Pty Limited
    Inventors: Sven Rogge, Joseph Salfi, Jan Andries Mol
  • Patent number: 9691857
    Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
  • Patent number: 9684129
    Abstract: In a waveguide device, unnecessary optical power is appropriately terminated. According to an embodiment of the present invention, the waveguide device has a termination structure filled with a light blocking material to terminate light from a waveguide end. In the termination structure, a cladding and a core are removed to form a groove on an optical waveguide. The groove is filled with a material (light blocking material) that attenuates the intensity of light. Thus, light input to the termination structure is attenuated by the light blocking material, suppressing crosstalk which possibly effects on other optical devices. Thus, such a termination structure can restrain crosstalk occurred in optical devices integrated in the same substrate and can also suppress crosstalk which possibly effects on any other optical device connected directly to the substrate.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: June 20, 2017
    Assignees: NTT Electronics Corporation, Nippon Telegraph and Telephone Corporation
    Inventors: Takanori Ishikawa, Tomoyo Shibazaki, Mitsuru Nagano, Masahiro Yanagisawa, Hiroshi Terui, Mikitaka Itoh
  • Patent number: 9680057
    Abstract: In various embodiments, light-emitting devices incorporate graded layers with compositional offsets at one or both end points of the graded layer to promote formation of two-dimensional carrier gases and polarization doping, thereby enhancing device performance.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: June 13, 2017
    Assignee: CRYSTAL IS, INC.
    Inventors: Craig Moe, James R. Grandusky, Shawn R. Gibb, Leo J. Schowalter, Kosuke Sato, Tomohiro Morishita
  • Patent number: 9679929
    Abstract: A binary image sensor includes a plurality of unit pixels on a substrate having a surface on which light is incident. At least one quantum dot is disposed on the surface of a substrate. A column sense amplifier circuit is configured to detect binary information of a selected unit pixel among the plurality of unit pixels from a voltage or a current detected from the selected unit pixel, and a processing unit is configured to process binary information of the respective unit pixels to generate pixel image information. Related devices and methods of operation are also discussed.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: June 13, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: GwideokRyan Lee, SangChul Sul, Myungwon Lee, Min-ho Kim, Taechan Kim, Taeseok Oh, KwangHyun Lee, Taeyon Lee, Younggu Jin
  • Patent number: 9646971
    Abstract: Semiconductor devices and fabricating methods thereof are provided. A semiconductor device may include a substrate, a metal layer on the substrate, a seed layer on the metal layer, a nanowire including a pillar shape on the seed layer, a dielectric film conformally covering the nanowire, and an electrode film on the dielectric film.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: May 9, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hyun Im, Han-Jin Lim, Jin-Won Ma, Kong-Soo Lee, Ki-Vin Im
  • Patent number: 9645082
    Abstract: A ballistic carrier spectral sensor includes a photon absorption region to generate photo-generated carriers from incident light; a first potential barrier region adjacent the photon absorption region and having an adjustable height defining a minimum energy of the photo-generated carriers required to pass therethrough; a second potential barrier region having an adjustable height defining a minimum energy of the photo-generated carriers required to pass therethrough; a spillage well region disposed between the first potential barrier region and the second potential barrier region and configured to collect photo-generated carriers having an energy lower than that required to pass through the second potential barrier region; and a collection region adjacent the second potential barrier region and configured to collect carriers that cross the second potential barrier region.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: May 9, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Diego Gallardo, James Andrew Robert Dimmock, Matthias Kauer, Valerie Berryman-Bousquet
  • Patent number: 9644077
    Abstract: A method for manufacturing a quantum dot thin film includes applying a tensile force to a substrate to elongate the substrate, coating a quantum dot particle on the substrate to form a quantum dot thin film, replacing a ligand of the quantum dot particle, and removing the tensile force from the substrate. The method may reduce a crack in a quantum dot thin film.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: May 9, 2017
    Assignee: Korea Institute of Machinery & Materials
    Inventors: Hyung-Cheoul Shim, So-Hee Jeong, Won-Seok Chang
  • Patent number: 9634183
    Abstract: A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: April 25, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Remigijus Gaska, Jinwei Yang, Michael Shur, Alexander Dobrinsky
  • Patent number: 9574135
    Abstract: Light-emitting materials are made from a porous light-emitting semiconductor having quantum dots (QDs) disposed within the pores. According to some embodiments, the QDs have diameters that are essentially equal in size to the width of the pores. The QDs are formed in the pores by exposing the porous semiconductor to gaseous QD precursor compounds, which react within the pores to yield QDs. According to certain embodiments, the pore size limits the size of the QDs produced by the gas-phase reactions. The QDs absorb light emitted by the light-emitting semiconductor material and reemit light at a longer wavelength than the absorbed light, thereby “down-converting” light from the semiconductor material.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: February 21, 2017
    Assignee: Nanoco Technologies Ltd.
    Inventors: Nigel Pickett, Nathalie Gresty
  • Patent number: 9570644
    Abstract: Systems and methods for the conversion of energy of high-energy photons into electricity which utilize a series of materials with differing atomic charges to take advantage of the emission of a large multiplicity of electrons by a single high-energy photon via a cascade of Auger electron emissions. In one embodiment, a high-energy photon converter preferably includes a linearly layered nanometric-scaled wafer made up of layers of a first material sandwiched between layers of a second material having an atomic charge number differing from the atomic charge number of the first material. In other embodiments, the nanometric-scaled layers are configured in a tubular or shell-like configuration and/or include layers of a third insulator material.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: February 14, 2017
    Assignee: TRI ALPHA ENERGY, INC.
    Inventors: Michl W. Binderbauer, Toshiki Tajima
  • Patent number: 9570502
    Abstract: Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described.
    Type: Grant
    Filed: June 20, 2016
    Date of Patent: February 14, 2017
    Assignee: InVisage Technologies, Inc.
    Inventors: Edward Hartley Sargent, Jason Paul Clifford, Gerasimos Konstantatos, Ian Howard, Ethan J. D. Klem, Larissa Levina
  • Patent number: 9553183
    Abstract: A normally-off compound semiconductor transistor includes a heterostructure body and a gate stack on the heterostructure body. The heterostructure body includes a source, a drain spaced apart from the source, and a channel for connecting the source and the drain. The channel includes a first two-dimensional charge carrier gas of a first polarity arising in the heterostructure body due to piezoelectric effects. The gate stack controls the channel in a region of the heterostructure body under the gate stack. The gate stack includes at least one III-nitride material which gives rise to a second two-dimensional charge carrier gas of a second polarity opposite the first polarity in the gate stack or in the heterostructure body under the gate stack due to piezoelectric effects. The second two-dimensional charge carrier gas counter-balances polarization charges in the first two-dimensional charge carrier gas so that the channel is disrupted under the gate stack.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: January 24, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Gilberto Curatola
  • Patent number: 9543365
    Abstract: The present invention provides a touch panel, including a lower substrate, an organic light-emitting component, disposed on the lower substrate, a nano silver sensing layer, disposed on the organic light emitting component, and an upper substrate, disposed on the nano silver sensing layer.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: January 10, 2017
    Assignee: TPK Touch Solutions Inc
    Inventors: Chen-Yu Liu, Li-Wei Kung, Hsi-Chien Lin
  • Patent number: 9530936
    Abstract: An LED having vertical topology and a method of making the same is capable of improving a luminous efficiency and reliability, and is also capable of achieving mass productivity. The method includes forming a semiconductor layer on a substrate; forming a first electrode on the semiconductor layer; forming a supporting layer on the first electrode; generating an acoustic stress wave at the interface between the substrate and semiconductor layer, thereby separating the substrate from the semiconductor layer; and forming a second electrode on the semiconductor layer exposed by the separation of the substrate.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: December 27, 2016
    Assignees: LG Electronics Inc., LG Innotek Co., Ltd.
    Inventors: Jun Ho Jang, Jae Wan Choi, Duk Kyu Bae, Hyun Kyong Cho, Jong Kook Park, Sun Jung Kim, Jeong Soo Lee
  • Patent number: 9530873
    Abstract: A quantum computing device that includes a plurality of semiconductor adiabatic qubits is described herein. The qubits are programmed with local biases and coupling terms between qubits that represent a problem of interest. The qubits are initialized by way of a tuneable parameter, a local tunnel coupling within each qubit, such that the qubits remain in a ground energy state, and that initial state is represented by the qubits being in a superposition of |0> and |1> states. The parameter is altered over time adiabatically or such that relaxation mechanisms maintain a large fraction of ground state occupation through decreasing the tunnel coupling barrier within each qubit with the appropriate schedule. The final state when tunnel coupling is effectively zero represents the solution state to the problem represented in the |0> and |1> basis, which can be accurately read at each qubit location.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: December 27, 2016
    Assignee: Sandia Corporation
    Inventors: Malcolm S. Carroll, Wayne Witzel, Noah Tobias Jacobson, Anand Ganti, Andrew J. Landahl, Michael Lilly, Khoi Thi Nguyen, Nathaniel Bishop, Stephen M. Carr, Ezra Bussmann, Erik Nielsen, James Ewers Levy, Robin J. Blume-Kohout, Rajib Rahman
  • Patent number: 9524809
    Abstract: A dielectric composite material is provided for switch control by optical stimulus. The material includes a plurality of photo-conductive particulates; and a transparent binder for containing the plurality of particulates to form a photo-conductive pigment based matrix. The pigment based matrix is disposed on to overlap first and second separate electrodes to produce an electrical junction. Capacitance of the pigment based matrix changes from a first value absent the optical stimulus to a second value in response to illumination at a specific electromagnetic frequency and intensity by the optical stimulus.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: December 20, 2016
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Kevin A. Boulais, Simin Feng, Pearl Rayms-Keller, Michael S. Lowry, Francesco Santiago
  • Patent number: 9520496
    Abstract: A semiconductor structure and formation thereof. The semiconductor structure has a first semiconductor layer with a first lattice structure and a second epitaxial semiconductor layer that is lattice-matched with the first semiconductor layer. At least two source/drain regions, which have a second lattice structure, penetrate the second semiconductor layer and contact the first semiconductor layer. A portion of the second semiconductor layer is between the source/drain regions and has a degree of uniaxial strain that is based, at least in part, on a difference between the first lattice structure and the second lattice structure.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: December 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Guy M. Cohen
  • Patent number: 9505621
    Abstract: A method for producing carbon nanotubes having specific lengths, said method comprising: producing carbon nanotubes having at least two types of zones along their lengths, wherein each zone type has a characteristic structure that confers specific properties; and processing said carbon nanotubes to selectively attack one zone type more aggressively than another zone type.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: November 29, 2016
    Assignee: NanoLab, Inc.
    Inventors: Nolan Nicholas, David Carnahan
  • Patent number: 9509280
    Abstract: A technique relates to a microwave device. A qubit is connected to a first end of a first coupling capacitor and a first end of a second coupling capacitor. A resonator is connected to a second end of the first coupling capacitor and a second end of the second coupling capacitor. The resonator includes a fundamental resonance mode. A filter is connected to both the qubit and the first end of the first or second coupling capacitor.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Baleegh Abdo, Jerry M. Chow, Jay M. Gambetta, Hanhee Paik
  • Patent number: 9496454
    Abstract: A vertical solid state lighting (SSL) device is disclosed. In one embodiment, the SSL device includes a light emitting structure formed on a growth substrate. Individual SSL devices can include a embedded contact formed on the light emitting structure and a metal substrate plated at a side at least proximate to the embedded contact. The plated substrate has a sufficient thickness to support the light emitting structure without bowing.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: November 15, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Odnoblyudov, Scott D. Schellhammer
  • Patent number: 9472727
    Abstract: A vertical structure light-emitting device includes a conductive support, a light-emitting semiconductor structure disposed on the conductive support structure, the semiconductor structure having a first semiconductor surface, a side semiconductor surface and a second semiconductor surface, a first electrode electrically connected to the first-type semiconductor layer, a second electrode electrically connected to the second-type semiconductor layer, wherein the second electrode has a first electrode surface, a side electrode surface and a second electrode surface, wherein the first electrode surface, relative to the second electrode surface, is proximate to the semiconductor structure; and wherein the second electrode surface is opposite to the first electrode surface, and a passivation layer disposed on the side semiconductor surface and the second semiconductor surface.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: October 18, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Jong Lam Lee, In-kwon Jeong, Myung Cheol Yoo
  • Patent number: 9470826
    Abstract: A color filter of display panel for converting dual band white backlight to light with three-primary colors. The color filter includes a plurality of first filtering parts, a plurality of second filtering parts, and a plurality of quantum dot blocks. The first filtering parts have a first primary color and allow light having a first wavelength corresponding to the first primary color to pass therethrough. The second filtering parts have a second primary color and selectively allow light having a second wavelength corresponding to the second primary color to pass therethrough. The quantum dot block converting light having a wavelength smaller than a third wavelength corresponding to a third primary color to light having the second wavelength.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: October 18, 2016
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Shih-Pin Tseng, Jung-An Cheng
  • Patent number: 9450150
    Abstract: A nitride semiconductor light-emitting element including a high concentration silicon-doped layer doped with silicon at a high concentration of 2×1019 atoms/cm3, and a dislocation reduction layer for laterally bending a threading dislocation on the high concentration silicon-doped layer.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: September 20, 2016
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Satoshi Komada
  • Patent number: 9444430
    Abstract: A technique relates to a microwave device. A qubit is connected to a first end of a first coupling capacitor and a first end of a second coupling capacitor. A resonator is connected to a second end of the first coupling capacitor and a second end of the second coupling capacitor. The resonator includes a fundamental resonance mode. A filter is connected to both the qubit and the first end of the first or second coupling capacitor.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: September 13, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Baleegh Abdo, Jerry M. Chow, Jay M. Gambetta, Hanhee Paik
  • Patent number: 9437774
    Abstract: A method of fabricating a light emitting diode, which includes an n-type contact layer and a light generating structure adjacent to the n-type contact layer, is provided. The light generating structure includes a set of quantum wells. The contact layer and light generating structure can be configured so that a difference between an energy of the n-type contact layer and an electron ground state energy of a quantum well is greater than an energy of a polar optical phonon in a material of the light generating structure. Additionally, the light generating structure can be configured so that its width is comparable to a mean free path for emission of a polar optical phonon by an electron injected into the light generating structure.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: September 6, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Maxim S. Shatalov, Michael Shur, Alexander Dobrinsky
  • Patent number: 9431556
    Abstract: A dilute nitrogen alloy of InNxSb1-x epilayers strained to an epitaxial substrate useful for Long Wavelength Infrared (LWIR) Focal Plane Arrays, and method of fabricating. Strained materials of composition InNxSb1-x exhibiting increased Auger lifetimes and improved absorption properties.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: August 30, 2016
    Assignee: THE UNIVERSITY OF HOUSTON SYSTEM
    Inventors: Alexandre Freundlich, Lekhnath Bhusal
  • Patent number: 9423560
    Abstract: A device includes a passive photonic layer located over a substrate and including at least one passive photonic element configured to propagate an optical signal therein. An electronic layer located between said substrate and said passive photonic layer includes at least one electronic device configured to propagate an electrical signal therein. An active photonic layer located over said passive photonic layer includes an active photonic device optically coupled to said passive photonic element and configured to convert between said electrical signal and said optical signal.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: August 23, 2016
    Assignee: Alcatel Lucent
    Inventors: Long Chen, Pietro Bernasconi, Po Dong, Liming Zhang, Young-Kai Chen
  • Patent number: 9419194
    Abstract: A light emitting diode includes an active region configured to emit light, a composite electrical contact layer, and a transparent electron blocking hole transport layer (TEBHTL). The composite electrical contact layer includes two materials. At least one of the two materials is a metal configured to reflect a portion of the emitted light. The TEBHTL is arranged between the composite electrical contact layer and the active region. The TEBHTL has a thickness that extends at least a majority of a distance between the active region and the composite electrical contact layer. The TEBHTL has a band-gap greater than a band-gap of light emitting portions of the active region. The band-gap of the TEBHTL decreases as a function of distance from the active region to the composite electrical contact layer over a majority of the thickness of the TEBHTL.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: August 16, 2016
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: John E. Northrup, Christopher L. Chua
  • Patent number: 9419174
    Abstract: Quantum dot light emitting diodes (QD-LEDs) are formed that are transparent and emit light from the top and bottom faces. At least one electrode of the QD-LEDs is a dielectric/metal/dielectric layered structure, where the first dielectric comprises metal oxide nanoparticles or polymer-nanoparticle blends and is 10 to 40 nm in thickness, the metal layer is 5 to 25 nm in thickness, and the second dielectric layer is a nanoparticulate, polymer-nanoparticle blend or continuous layer of 30 to 200 nm in thickness and is situated distal to the light emitting layer of the QD-LED.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: August 16, 2016
    Assignee: UNIVERSITY OF FLORIDA RESEARCH FOUNDATION, INC.
    Inventors: Ying Zheng, Weiran Cao, Jiangeng Xue, Paul H. Holloway
  • Patent number: 9406799
    Abstract: At least one method, apparatus and system disclosed involves semiconductor base structure adapted for accepting at least one of a NMOS device and a PMOS device. A substrate is formed. A strained relaxed layer is formed on the substrate. A first tensile strained layer is formed on the strained relaxed layer. A first compressive strain layer is formed on the first tensile strained layer.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Deepak Kumar Nayak
  • Patent number: 9406845
    Abstract: A nitride semiconductor structure including a substrate, a first type nitride semiconductor layer disposed on the substrate, an active layer disposed between the substrate and the first type nitride semiconductor layer and a second type nitride semiconductor layer disposed between the substrate and the active layer is provided. The active layer includes a first multiple quantum well structure including a plurality of first quantum well layers and a plurality of first barrier layers staggered with each other, and a second multiple quantum well structure including a plurality of second quantum well layers and a plurality of second barrier layers staggered with each other. A second type dopant is doped into at least one of the second barrier layers, and a concentration of the second dopant in the second barrier layer is higher than that of the second dopant in the second type nitride semiconductor layer.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: August 2, 2016
    Assignee: PlayNitride Inc.
    Inventors: Yen-Lin Lai, Jyun-De Wu
  • Patent number: 9401452
    Abstract: A light emitting device includes a p-side heterostructure having a short period superlattice (SPSL) formed of alternating layers of AlxhighGa1-xhighN doped with a p-type dopant and AlxlowGa1-xlowN doped with the p-type dopant, where xlow?xhigh?0.9. Each layer of the SPSL has a thickness of less than or equal to about six bi-layers of AlGaN.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 26, 2016
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: John E. Northrup, Bowen Cheng, Christopher L. Chua, Thomas Wunderer, Noble M. Johnson, Zhihong Yang
  • Patent number: 9400957
    Abstract: A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material. At least one electrode is provided for selectively modifying an electronic state of the controllably quantum mechanically coupled dangling bonds. By providing at least one additional electron within the controllably quantum mechanically coupled dangling bonds with the proviso that there exists at least one unoccupied dangling bond for each one additional electron present, the inventive device is operable at least to 293 degrees Kelvin and is largely immune to stray electrostatic perturbations. Room temperature operable quantum cellular automata and qubits are constructed therefrom.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: July 26, 2016
    Assignees: National Research Council of Canada, The Governors of the University of Alberta
    Inventors: Gino A. Dilabio, Robert A. Wolkow, Jason L. Pitters, Paul G. Piva
  • Patent number: 9397188
    Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: July 19, 2016
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Robert Chau, Benjamin Chu-Kung, Gilbert Dewey, Jack Kavalieros, Matthew Metz, Niloy Mukherjee, Ravi Pillarisetty, Marko Radosavljevic
  • Patent number: 9385276
    Abstract: Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: July 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Anton deVilliers, Erik Byers, Scott E. Sills
  • Patent number: 9379271
    Abstract: A method of making and a photodetector comprising a substrate; a p-type or n-type layer; first and second region each having polarizations, a first interface therebetween, the magnitudes and directions of the first and second polarizations being such that a scalar projection of second polarization on the growth direction relative to the scalar projection of the first polarization projected onto the growth direction is sufficient to create a first interface charge; and a third region suitable for forming one of an n-metal or p-metal contact thereon having a third polarization, a second interface between the second and third regions, the third polarization having a scalar projection on the growth direction that, relative to scalar projection of the second polarization onto the growth direction, is sufficient to create a second interface charge; the first and second interface charges creating an electrostatic potential barrier to carriers defining a predetermined wavelength range.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: June 28, 2016
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventors: Paul Shen, Lee Ellen Rodak, Chad Stephen Gallinat, Anand Venktesh Sampath, Michael Wraback
  • Patent number: 9373502
    Abstract: Embodiments described herein relate to a structure for III-V devices on silicon. A Group IV substrate is provided and a III-V structure may be formed thereon. The III-V structure generally comprises one or more buffer layers and a channel layer disposed on the one or more buffer layers. The one or more buffer layers may be selected to provide optimal microelectronic device properties, such as minimal defects, reduced charge accumulation, and reduced current leakage.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: June 21, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Xinyu Bao, Errol Antonio C. Sanchez
  • Patent number: 9373736
    Abstract: Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: June 21, 2016
    Assignee: InVisage Technologies, Inc.
    Inventors: Edward Hartley Sargent, Jason Paul Clifford, Gerasimos Konstantatos, Ian Howard, Ethan J. D. Klem, Larissa Levina
  • Patent number: 9373750
    Abstract: The present invention provides a Group III nitride semiconductor light-emitting device which exhibits improved light emission efficiency. The light-emitting layer has a MQW structure in which a plurality of layer units are repeatedly deposited, each layer unit comprising a well layer, a capping layer, and a barrier layer sequentially deposited. The well layer is formed of InGaN, the capping layer has a structure in which a GaN layer and an AlGaN layer are deposited in this order on the well layer, and the barrier layer is formed of AlGaN. The AlGaN layer has a higher Al composition ratio than that of the barrier layer. The AlGaN layer in the former portion has a lower Al composition ratio than that of the AlGaN layer in the latter portion when the light-emitting layer is divided into a former portion at the n-cladding layer side and a latter portion at the p-cladding layer side in a thickness direction.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: June 21, 2016
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Koji Okuno
  • Patent number: 9362451
    Abstract: A light emitting diode is disclosed. The disclosed light emitting diode includes a light emitting structure including a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer. The first-conductivity-type semiconductor layer, active layer, and second-conductivity-type semiconductor layer are disposed to be adjacent to one another in a same direction. The active layer includes well and barrier layers alternately stacked at least one time. The well layer has a narrower energy bandgap than the barrier layer. The light emitting diode also includes a mask layer disposed in the first-conductivity-type semiconductor layer, a first electrode disposed on the first-conductivity-type semiconductor layer, and a second electrode disposed on the second-conductivity-type semiconductor layer. The first-conductivity-type semiconductor layer is formed with at least one recess portion.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: June 7, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Myung Hoon Jung, Hyun Chul Lim, Sul Hee Kim, Rak Jun Choi
  • Patent number: 9349910
    Abstract: A light emitting device comprising a staggered composition quantum well (QW) has a step-function-like profile in the QW, which provides higher radiative efficiency and optical gain by providing improved electron-hole wavefunction overlap. The staggered QW includes adjacent layers having distinctly different compositions. The staggered QW has adjacent layers Xn, wherein X is a quantum well component and in one quantum well layer n is a material composition selected for emission at a first target light regime, and in at least one other quantum well layer n is a distinctly different composition for emission at a different target light regime. X may be an In-content layer and the multiple Xn-containing layers provide a step function In-content profile.
    Type: Grant
    Filed: January 30, 2014
    Date of Patent: May 24, 2016
    Assignee: Lehigh University
    Inventors: Nelson Tansu, Ronald A. Arif, Yik Khoon Ee, Hongping Zhao
  • Patent number: 9343619
    Abstract: The present invention provides a Group III nitride semiconductor light-emitting device exhibiting high light efficiency achieved by relaxing a piezoelectric field generated in a light-emitting layer without deteriorating the crystal quality of the light-emitting layer, and a method for producing the same. The light-emitting device has a light-emitting layer in which layer units are repeatedly deposited. Each layer unit comprises an AlGaN layer, an n-type InGaN layer, an InGaN layer, a GaN layer, and an AlGaN layer which are deposited in this order on the n-side superlattice layer. The n-type InGaN layer is doped with Si at a Si concentration of 1×1017/cm3 to 3×1018/cm3.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: May 17, 2016
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Koji Okuno
  • Patent number: 9337617
    Abstract: A tunable semiconductor laser having, in one embodiment, a higher bias voltage end, a lower bias voltage end, and an optically active gain region comprising a band-gap configured to emit light at an emission wavelength that is tunable when an electric field is generated across the optically active gain region by applying a bias voltage thereto, an electron quantum well (QW) layer positioned closer to the higher bias voltage end than the lower voltage bias end, and a hole QW layer positioned closer to the lower bias voltage end than the higher bias voltage end and comprising a type-II band alignment with the electron QW layer such that the band-gap is determined by an energy difference between a ground electron state in the electron QW layer and a ground hole state in the hole QW layer, wherein the emission wavelength is redshifted upon an increase in a bias voltage applied to the optically active gain region.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: May 10, 2016
    Assignee: The Board of Regents of the University of Oklahoma
    Inventors: Rui Q. Yang, Zhaobing Tian, Lu Li, Michael B. Santos, Matthew B. Johnson, Yuchao Jiang
  • Patent number: 9318659
    Abstract: A nitride semiconductor light emitting element includes a light emitting layer. The light emitting layer includes an InxGa1-xN well layer (0<x?1) having a principal surface that is an m-plane. A profile in a depth direction (depth profile) of an In composition ratio x in the InxGa1-xN well layer has a plurality of peaks. Values of the In composition ratios x at the respective plurality of peaks are different from one another.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: April 19, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Akira Inoue, Shunji Yoshida, Toshiya Yokogawa
  • Patent number: 9312428
    Abstract: A light emitting heterostructure including a partially relaxed semiconductor layer is provided. The partially relaxed semiconductor layer can be included as a sublayer of a contact semiconductor layer of the light emitting heterostructure. A dislocation blocking structure also can be included adjacent to the partially relaxed semiconductor layer.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: April 12, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 9310285
    Abstract: An Integrated Circuit (IC) chip with a lab-on-a-chip, a method of manufacturing the lab-on-a-chip and a method of using the lab-on-a-chip for fluid flow analysis in physical systems through combination with computer modeling. The lab-on-a-chip includes cavities in a channel layer and a capping layer, preferably transparent, covering the cavities. Gates control two dimensional (2D) lattice structures acting as heaters, light sources and/or sensors in the cavities, or fluid channels. The gates and two dimensional (2D) lattice structures may be at the cavity bottoms or on the capping layer. Wiring connects the gates and the 2D lattice structures externally.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: April 12, 2016
    Assignee: International Business Machines Corporation
    Inventors: Phaedon Avouris, Michael Engel, Claudius Feger, Ronaldo Giro, Rodrigo Ferreira, Mathias Steiner