Quantum Well Patents (Class 257/14)
  • Patent number: 9287446
    Abstract: A nanostructure semiconductor light emitting device includes a base layer, an insulating layer, a plurality of light emitting nanostructures, and a contact electrode. The base layer is formed of a first conductivity-type semiconductor material. The insulating layer is disposed on the base layer. Each light emitting nanostructure is disposed in a respective opening of a plurality of openings in the base layer, and includes a nanocore formed of the first conductivity-type semiconductor material, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on a surface of the nanocore. The contact electrode is spaced apart from the insulating layer and is disposed on a portion of the second conductivity-type semiconductor layer. A tip portion of the light emitting nanostructure has crystal planes different from those on side surfaces of the light emitting nanostructure.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: March 15, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Geon Wook Yoo, Kyung Wook Hwang, Yong Min Kim, Sung Hyun Sim
  • Patent number: 9287412
    Abstract: This invention describes a field-effect transistor in which the channel is formed in an array of quantum dots. In one embodiment the quantum dots are cladded with a thin layer serving as an energy barrier. The quantum dot channel (QDC) may consist of one or more layers of cladded dots. These dots are realized on a single or polycrystalline substrate. When QDC FETs are realized on polycrystalline or nanocrystalline thin films they may yield higher mobility than in conventional nano- or microcrystalline thin films. These FETs can be used as thin film transistors (TFTs) in a variety of applications. In another embodiment QDC-FETs are combined with: (a) coupled quantum well SWS channels, (b) quantum dot gate 3-state like FETs, and (c) quantum dot gate nonvolatile memories.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: March 15, 2016
    Inventor: Faquir Chand Jain
  • Patent number: 9281060
    Abstract: A device is disclosed, comprising: a first layer including a first molecular network having a first 2D lattice structure, a second layer including a second molecular network having a second 2D lattice structure, wherein the first layer and the second layer are arranged at a distance from each other such that the first and the second molecular network interact electronically via molecular orbital interactions, and a rotation device implemented to rotate the first layer relative to the second layer by a rotation angle, wherein an electrical resistance between the first molecular network and the second molecular network changes as a function of the rotation angle.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: March 8, 2016
    Assignee: International Business Machines Corporation
    Inventors: Urs T. Duerig, Armin W. Knoll, Elad Koren, Emanuel Loertscher
  • Patent number: 9276144
    Abstract: A quantum cascade detector includes a semiconductor substrate, and an active layer formed by laminating unit laminate structures each having an absorption region with a first barrier layer to a second well layer and a transport region with a third barrier layer to an n-th well layer. A second absorption well layer has a layer thickness ½ or less of that of a first absorption well layer thickest in one period, and a coupling barrier layer has a layer thickness smaller than that of an exit barrier layer thickest in one period. The unit laminate structure has a detection lower level arising from a ground level in the first well layer, a detection upper level generated by coupling an excitation level in the first well layer and a ground level in the second well layer, and a transport level structure for electrons.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: March 1, 2016
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Kazuue Fujita, Toru Hirohata, Tadataka Edamura, Tatsuo Dougakiuchi
  • Patent number: 9269689
    Abstract: An integrated circuit package comprising an enclosure including a dielectric housing, a first electrical contact, and a second electrical contact. The dielectric housing, the first electrical contact, and the second electrical contact are configured to form a contact side of the enclosure. In addition, the first and second electrical contacts are sized to be substantially alignment insensitive for electro-mechanical connection to corresponding contacts of an end-use equipment. The enclosure encapsulates an integrated circuit die which is electrically coupled to the first and second electrical contacts. The alignment insensitive first and second electrical contacts may be electro-mechanically connected to corresponding contacts of an end-use equipment (e.g., a printer). Further, the integrated circuit package may be hosted by a peripheral device (e.g., a printer cartridge).
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: February 23, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Jeff A. Gordon, Steven Hass, Hal Kurkowski, Scott Jones
  • Patent number: 9264645
    Abstract: An optical sensor apparatus includes a package having a window; a sensor chip having an array of light receiving devices and a pixel electrode connected to each light receiving device, the sensor chip having an incidence surface that faces the window of the package; and a read-out circuit disposed under the sensor chip, the read-out circuit having a read-out electrode electrically connected to each pixel electrode of the sensor chip. The sensor chip and the read-out circuit are housed in the package. In plan view from the sensor chip, the read-out circuit is overlapped by the sensor chip, and the read-out circuit has no portion extending off the sensor chip.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: February 16, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, INC.
    Inventors: Hiroshi Inada, Masaki Migita, Yasuhiro Iguchi
  • Patent number: 9263586
    Abstract: The present disclosure provides a quantum well fin field effect transistor (QWFinFET). The QWFinFET includes a semiconductor fin over a substrate and a combo quantum well (QW) structure over the semiconductor fin. The combo QW structure includes a QW structure over a top portion of the semiconductor fin and a middle portion of the semiconductor fin. The semiconductor fin and the QW comprise different semiconductor materials. The QWFinFET also includes a gate stack over the combo QW structure.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Yung-Ta Li
  • Patent number: 9240518
    Abstract: A light emitting diode device is provided, which comprises a silicon-based substrate, a buffer layer, a super lattice structure layer, a nano-structure layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer. The buffer layer is formed on the silicon-based substrate, the super lattice structure layer is formed on the buffer layer, the nano-structure layer is formed on the super lattice structure layer, a first semiconductor layer is formed on the nano-structure layer, and the light emitting layer is formed between the first semiconductor layer and the second semiconductor layer. The super lattice layer and the nano-structure can release the stress within the light emitting diode device, and reduce the epitaxy defect, so that the internal quantum effect and the external quantum effect can be increased.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: January 19, 2016
    Assignee: National Chiao Tung University
    Inventors: Chia-Yu Lee, Da-Wei Lin, An-Jye Tzou, Hao-Chung Kuo
  • Patent number: 9235811
    Abstract: Embodiments are directed to engineering a structure, comprising: measuring energy eigenstates of a Hamiltonian, predicting a time evolution of a combination of two energy eigenstates based on the measurement, and creating an entangled quantum state for two coefficients of the two energy eigenstates such that an associated wavefunction is encouraged to undergo the predicted time evolution.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: January 12, 2016
    Assignee: RAYTHEON COMPANY
    Inventor: Steven M. Stoltz
  • Patent number: 9231223
    Abstract: The present invention provides of a three-dimensional bicontinuous heterostructure, a method of producing same, and the application of this structure towards the realization of photodetecting and photovoltaic devices working in the visible and the near-infrared. The three-dimensional bicontinuous heterostructure includes two interpenetrating layers which are spatially continuous, they are include only protrusions or peninsulas, and no islands. The method of producing the three-dimensional biocontinuous heterostructure relies on forming an essentially planar continuous bottom layer of a first material; forming a layer of this first material on top of the bottom layer which is textured to produce protrusions for subsequent interpenetration with a second material, coating this second material onto this structure; and forming a final coating with the second material that ensures that only the second material is contacted by subsequent layer.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: January 5, 2016
    Assignee: InVisage Technologies, Inc.
    Inventors: Edward Sargent, Steven Ashworth McDonald, Shiguo Zhang, Larissa Levina, Gerasimos Konstantatos, Paul Cyr
  • Patent number: 9230804
    Abstract: A semiconductor device includes a first non-flat non-polar nitride semiconductor layer, a first structure layer on at least a portion of the surface of the first non-flat non-polar nitride semiconductor layer and a first non-polar nitride semiconductor layer on the first non-flat non-polar nitride semiconductor layer and the first structure layer. The first non-flat non-polar nitride semiconductor layer includes a plurality of solid particles.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 5, 2016
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SNU R&DB FOUNDATION
    Inventors: Sangmoon Lee, Euijoon Yoon, Jinsub Park, Sung Hyun Park
  • Patent number: 9231056
    Abstract: A semiconductor device includes a drift layer having a structure wherein a plurality of quantum dot layers each including a quantum dot containing InxGa1-xN (0?x?1) and a burying layer burying the quantum dot and containing n-type Inx(GayAl1-y)1-xN (0?x?1, 0?y?1) are stacked.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: January 5, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Naoya Okamoto
  • Patent number: 9224907
    Abstract: A vertical structure light-emitting device includes a conductive support, a light-emitting semiconductor structure disposed on the conductive support structure, the semiconductor structure having a first semiconductor surface, a side semiconductor surface and a second semiconductor surface, a first electrode electrically connected to the first-type semiconductor layer, a second electrode electrically connected to the second-type semiconductor layer, wherein the second electrode has a first electrode surface, a side electrode surface and a second electrode surface, wherein the first electrode surface, relative to the second electrode surface, is proximate to the semiconductor structure; and wherein the second electrode surface is opposite to the first electrode surface, and a passivation layer disposed on the side semiconductor surface and the second semiconductor surface.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: December 29, 2015
    Assignee: LG Innotek Co., Ltd.
    Inventors: Jong Lam Lee, In-kwon Jeong, Myung Cheol Yoo
  • Patent number: 9224920
    Abstract: A quantum rod includes a core of ZnS semiconductor particle having a rod shape; and a transition metal with which the core is doped and which is biased at one side of a length direction of the core.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: December 29, 2015
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kyung-Seok Jeong, Gee-Sung Chae, Jin-Wuk Kim, Sung-hee Cho
  • Patent number: 9219190
    Abstract: A single photon source die includes a first semiconductor layer, a plurality of columnar structures formed on the first semiconductor layer, a second semiconductor layer formed on the columnar structures. Each columnar structure includes a bottom layer, a single photon point layer and a connecting layer. The single photon point layer includes a plurality of single photon points.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: December 22, 2015
    Assignee: ADVANCED OPTOELECTRONIC TECHNOLOGY, INC.
    Inventors: Ching-Hsueh Chiu, Ya-Wen Lin, Po-Min Tu, Shih-Cheng Huang
  • Patent number: 9213945
    Abstract: A quantum device is provided that includes controllably quantum mechanically coupled dangling bonds extending from a surface of a semiconductor material. Each of the controllably quantum mechanically coupled dangling bonds has a separation of at least one atom of the semiconductor material. At least one electrode is provided for selectively modifying an electronic state of the controllably quantum mechanically coupled dangling bonds. By providing at least one additional electron within the controllably quantum mechanically coupled dangling bonds with the proviso that there exists at least one unoccupied dangling bond for each one additional electron present, the inventive device is operable at least to 293 degrees Kelvin and is largely immune to stray electrostatic perturbations. Room temperature operable quantum cellular automata and qubits are constructed thereform.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: December 15, 2015
    Assignees: National Research Council of Canada, The Governors of The University of Alberta
    Inventors: Gino A. Dilabio, Robert A. Wolkow, Jason L. Pitters, Paul G. Piva
  • Patent number: 9202979
    Abstract: There is provided a method of fabricating a vertical light emitting diode which includes forming a light emitting diode structure. Forming the light emitting diode structure includes: forming a first material layer of a first conductivity type, forming a second material layer of a second conductivity type, forming a light emitting layer between the first material layer and the second material layer, and forming a plurality of generally ordered photonic nanostructures at a surface of the first material layer through which light generated from the light emitting layer is emitted for enhancing light extraction efficiency of the vertical light emitting diode. In particular, forming a plurality of generally ordered photonic nanostructures includes forming a self-assembled template including generally ordered nanoparticles on the surface of the first material layer to function as a mask for forming the photonic nanostructures at said surface of the first material layer.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: December 1, 2015
    Assignee: Agency for Science, Technology and Research
    Inventors: Sivashankar Krishnamoorthy, Krishna Kumar Manippady, Surani Bin Dolmanan, Kaixin Vivian Lin, Siew Lang Teo, Sudhiranjan Tripathy
  • Patent number: 9166363
    Abstract: Structures and methodologies to obtain lasing in indirect gap semiconductors such as Ge and Si are provided and involves excitonic transitions in the active layer comprising of at least one indirect gap layer. Excitonic density is increased at a given injection current level by increasing their binding energy by the use of quantum wells, wires, and dots with and without strain. Excitons are formed by holes and electrons in two different layers that are either adjacent or separated by a thin barrier layer, where at least one layer confining electrons and holes is comprised of indirect gap semiconductor such as Si and Ge, resulting in high optical gain and lasing using optical and electrical injection pumping.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: October 20, 2015
    Inventor: Faquir C. Jain
  • Patent number: 9153731
    Abstract: A tight confinement nanocrystal comprises a homogeneous center region having a first composition and a smoothly varying region having a second composition wherein a confining potential barrier monotonically increases and then monotonically decreases as the smoothly varying region extends from the surface of the homogeneous center region to an outer surface of the nanocrystal. A method of producing the nanocrystal comprises forming a first solution by combining a solvent and at most two nanocrystal precursors; heating the first solution to a nucleation temperature; adding to the first solution, a second solution having a solvent, at least one additional and different precursor to form the homogeneous center region and at most an initial portion of the smoothly varying region; and lowering the solution temperature to a growth temperature to complete growth of the smoothly varying region.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: October 6, 2015
    Assignee: The Research Foundation for the State University of New York
    Inventor: Keith Kahen
  • Patent number: 9121823
    Abstract: Disclosed are solid-state nanopore devices having pores of nanometer-scale thickness, which ultrathin (e.g., less than 10 nm thick) pores enable devices having improved resolution. Also provided are methods of fabricating such devices and of using such devices. The invention also provides nanometer-thick membranes and related methods of fabricating such membranes, which membranes are useful in high resolution microscopy applications. Further disclosed are devices for detection of analytes—including miRNA—that may be small in size and may also be present in only small quantities.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: September 1, 2015
    Assignee: The Trustees Of The University Of Pennsylvania
    Inventors: Marija Drndic, Meni Wanunu, Tali Dadosh
  • Patent number: 9111875
    Abstract: According to one embodiment, a pattern formation method includes forming a layer above an underlying layer. The layer includes a block copolymer. The method further includes forming a first phase including a first polymer and a second phase including a second polymer in the layer by phase-separating the block copolymer, and selectively removing the first phase by dry etching the layer using an etching gas including carbon monoxide.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: August 18, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yamamoto, Tsubasa Imamura, Hisataka Hayashi, Mitsuhiro Omura
  • Patent number: 9099593
    Abstract: The present disclosure involves an illumination apparatus. The illumination apparatus includes an n-doped semiconductor compound layer, a p-doped semiconductor compound layer spaced apart from the n-doped semiconductor compound layer, and a multiple-quantum-well (MQW) disposed between the first semiconductor compound layer and the second semiconductor compound layer. The MQW includes a plurality of alternating first and second layers. The first layers of the MQW have substantially uniform thicknesses. The second layers have graded thicknesses with respect to distances from the p-doped semiconductor compound layer. A subset of the second layers located most adjacent to the p-doped semiconductor compound layer is doped with a p-type dopant. The doped second layers have graded doping concentration levels that vary with respect to distances from the p-doped semiconductor layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: August 4, 2015
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Zhen-Yu Li, Hon-Way Lin, Chung-Pao Lin, Hsing-Kuo Hsia, Hao-Chung Kuo
  • Patent number: 9099407
    Abstract: A method for making bowl shaped metal nanostructure includes providing a metal layer located on a substrate. The metal layer has a top surface away from the substrate. A pattern mask layer is located on the top surface of the metal layer, wherein portion of the top surface of the metal layer is covered by the pattern mask layer. A plurality of flaws is formed in the pattern mask layer by annealing above substructure. After annealing, the substructure is etched by physical etching gas and reactive etching gas, to form the bowl shaped metal nanostructure.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: August 4, 2015
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Zhen-Dong Zhu, Qun-Qing Li, Ben-Feng Bai, Shou-Shan Fan
  • Patent number: 9076912
    Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure includes a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. One well layer is disposed between every two barrier layers. The barrier layer is made of AlxInyGa1-x-yN (0<x<1, 0<y<1, 0<x+y<1) while the well layer is made of InzGa1-zN (0<z<1). Thereby quaternary composition is adjusted for lattice match between the barrier layers and the well layers. Thus crystal defect caused by lattice mismatch is improved.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: July 7, 2015
    Assignee: Genesis Photonics Inc.
    Inventors: Yen-Lin Lai, Shen-Jie Wang
  • Patent number: 9070815
    Abstract: A photonic device is provided. The photonic device includes: a semiconductor layer including first and second regions; an insulating layer covering the semiconductor layer; and first and second plugs extending to pass through the insulating layer and electrically connected to the corresponding first and second regions. The first plug is in a rectifying contact with the first region, and the second plug is in an ohmic contact with the second region.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: June 30, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang-hyun Lee, Dong-jae Shin, Ho-chul Ji
  • Patent number: 9065004
    Abstract: In general, according to one embodiment, a semiconductor light emitting element includes: a first semiconductor layer; a second semiconductor layer; a light emitting layer. The light emitting layer includes a well layer with a thickness of t1 (nanometers). The well layer includes InxGa1-xN having an In composition ratio x higher than 0 and lower than 1. The first semiconductor layer has a tensile strain of not less than 0.02 percent and not more than 0.25 percent in a plane perpendicular to a stacking direction. A peak wavelength ?p (nanometers) of light satisfies a relationship of ?p=a1+a2×(x+(t1?3.0)×a3). The a1 is not less than 359 and not more than 363. The a2 is not less than 534 and not more than 550. The a3 is not less than 0.0205 and not more than 0.0235.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: June 23, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoharu Sugiyama, Shigeya Kimura, Hisashi Yoshida, Toshiki Hikosaka, Jumpei Tajima, Hajime Nago, Shinya Nunoue
  • Patent number: 9064067
    Abstract: Disclosed are systems and methods for improving quantum computation simulation execution time by “growing” sets of small quantum gates into larger ones. Two approaches are described. In the first approach, sub-strings may be replaced by a single representative that may be used multiple times throughout the quantum circuit. In the second approach, nearby gates may be coalesced in an iterative fashion, to thereby build larger and larger gates. Results may be cached for re-use. Both of these approaches have proven effective and have gained typical simulation speed-ups of 1-2 orders of magnitude.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: June 23, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: David B. Wecker
  • Patent number: 9054036
    Abstract: According to one embodiment, a nitride semiconductor device includes a stacked body and a functional layer. The stacked body includes an AlGaN layer of AlxGa1-xN (0<x?1), a first Si-containing layer, a first GaN layer, a second Si-containing layer, and a second GaN layer. The first Si-containing layer contacts an upper surface of the AlGaN layer. The first Si-containing layer contains Si at a concentration not less than 7×1019/cm3 and not more than 4×1020/cm3. The first GaN layer is provided on the first Si-containing layer. The first GaN layer includes a protrusion having an oblique surface tilted with respect to the upper surface. The second Si-containing layer is provided on the first GaN layer. The second Si-containing layer contains Si. The second GaN layer is provided on the second Si-containing layer. The functional layer is provided on the stacked body. The functional layer includes a nitride semiconductor.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: June 9, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Hikosaka, Yoshiyuki Harada, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 9054246
    Abstract: Various embodiment include optical and optoelectronic devices and methods of making same. Under one aspect, an optical device includes an integrated circuit having an array of conductive regions, and an optically sensitive material over at least a portion of the integrated circuit and in electrical communication with at least one conductive region of the array of conductive regions. Under another aspect, a film includes a network of fused nanocrystals, the nanocrystals having a core and an outer surface, wherein the core of at least a portion of the fused nanocrystals is in direct physical contact and electrical communication with the core of at least one adjacent fused nanocrystal, and wherein the film has substantially no defect states in the regions where the cores of the nanocrystals are fused. Additional devices and methods are described.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: June 9, 2015
    Assignee: InVisage Technologies, Inc.
    Inventors: Edward Hartley Sargent, Jason Paul Clifford, Gerasimos Konstantatos, Ian Howard, Ethan J. D. Klem, Larissa Levina
  • Patent number: 9053959
    Abstract: Semiconductor light converting constructions are disclosed. The semiconductor light converting construction includes a first semiconductor layer for absorbing at least a portion of light at a first wavelength; a semiconductor potential well for converting at least a portion of the light absorbed at the first wavelength to light at a longer second wavelength; and a second semiconductor layer that is capable of absorbing at least a portion of light at the first wavelength. The first semiconductor layer has a maximum first index of refraction at the second wavelength. The second semiconductor layer has a second index of refraction at the second wavelength that is greater than the maximum first index of refraction.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: June 9, 2015
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Michael A. Haase, Jun-Ying Zhang, Thomas J. Miller
  • Patent number: 9048347
    Abstract: An epitaxial structure is provided. The epitaxial structure comprises a substrate, a carbon nanotube layer and an epitaxial layer stacked in that order. The substrate has an epitaxial growth surface and defines a plurality of first grooves and first bulges on the epitaxial growth surface. The carbon nanotube layer covers the epitaxial growth surface, wherein a first part of the carbon nanotube layer is attached on top surface of the first bulges, and a second part of the carbon nanotube layer is attached on bottom surface and side surface of the first grooves. The epitaxial layer is formed on the epitaxial growth surface, and the carbon nanotube layer is sandwiched between the epitaxial layer and the substrate.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: June 2, 2015
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 9048364
    Abstract: A nitride semiconductor structure and a semiconductor light emitting device including the same are revealed. The nitride semiconductor structure mainly includes a stress control layer disposed between a light emitting layer and a p-type carrier blocking layer. The p-type carrier blocking layer is made from AlxGa1?xN (0<x<1) while the stress control layer is made from AlxInyGa1?x?yN (0<x<1, 0<y<1, 0<x+y<1). The light emitting layer has a multiple quantum well structure formed by a plurality of well layers and barrier layers stacked alternately. There is one well layer disposed between the two barrier layers. Thereby the stress control layer not only improves crystal quality degradation caused by lattice mismatch between the p-type carrier blocking layer and the light emitting layer but also reduces effects of compressive stress on the well layer caused by material differences.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: June 2, 2015
    Assignee: Genesis Photonics Inc.
    Inventors: Chi-Feng Huang, Ching-Liang Lin, Shen-Jie Wang, Jyun-De Wu, Yu-Chu Li, Chun-Chieh Lee
  • Patent number: 9040327
    Abstract: A method for fabricating AlxGa1-xN-cladding-free nonpolar III-nitride based laser diodes or light emitting diodes. Due to the absence of polarization fields in the nonpolar crystal planes, these nonpolar devices have thick quantum wells that function as an optical waveguide to effectively confine the optical mode to the active region and eliminate the need for Al-containing waveguide cladding layers.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: May 26, 2015
    Assignee: The Regents of the University of California
    Inventors: Daniel F. Feezell, Mathew C. Schmidt, Kwang-Choong Kim, Robert M. Farrell, Daniel A. Cohen, James S. Speck, Steven P. DenBaars, Shuji Nakamura
  • Publication number: 20150136229
    Abstract: A composite particle including a core member including a rare earth ion which shows an upconversion effect and a retaining material which retains the rare earth ion, and a semiconductor member covering a part or all of the surface of the core member, wherein the retaining material includes a semiconductor material having a band gap greater than energy difference necessary for a second step excitation in the rare earth ion to occur, or an insulating material, and the semiconductor member includes a semiconductor material having a band gap smaller than the energy difference between a first excited state and a ground state of the rare earth ion.
    Type: Application
    Filed: July 23, 2012
    Publication date: May 21, 2015
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Hiroyuki Suto
  • Publication number: 20150137073
    Abstract: A method of forming nanowire devices. The method includes forming a stressor layer circumferentially surrounding a semiconductor nanowire. The method is performed such that, due to the stressor layer, the nanowire is subjected to at least one of radial and longitudinal strain to enhance carrier mobility in the nanowire. Radial and longitudinal strain components can be used separately or together and can each be made tensile or compressive, allowing formulation of desired strain characteristics for enhanced conductivity in the nanowire of a given device.
    Type: Application
    Filed: January 14, 2015
    Publication date: May 21, 2015
    Inventors: Bernd W. Gotsmann, Siegfried F. Karg, Heike E. Riel
  • Publication number: 20150137072
    Abstract: A mask for forming a semiconductor layer and a semiconductor device manufactured using the same. The mask for forming a semiconductor layer includes oblique openings. Since a semiconductor layer is formed through one or more openings, it is possible to suppress generation of threading dislocation in a vertical direction from a growth surface of a heterogeneous substrate. The oblique openings are formed by stacking a growth blocking layer on the substrate, followed by dry etching the growth blocking layer, with the substrate disposed in a tilted state.
    Type: Application
    Filed: November 14, 2014
    Publication date: May 21, 2015
    Inventors: Dong-Seon LEE, Dongju SEO, Junyoub LEE, Dukjo KONG, Chang Mo KANG
  • Patent number: 9024294
    Abstract: There are disclosed a group III nitride nanorod light emitting device and a method of manufacturing thereof. The group III nitride nanorod light emitting device includes a substrate, an insulating film formed on the substrate, and including a plurality of openings exposing parts of the substrate and having different diameters, and first conductive group III nitride nanorods having different diameters, respectively formed in the plurality of openings, wherein each of the first conductive group III nitride nanorods has an active layer and a second conductive semiconductor layer sequentially formed on a surface thereof.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: May 5, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han Kyu Seong, Hun Jae Chung, Jung Ja Yang, Cheol Soo Sone
  • Patent number: 9018618
    Abstract: There is provided a semiconductor light emitting device including: an n-type semiconductor layer; a p-type semiconductor layer; and an active layer disposed between the n-type semiconductor layer and the p-type semiconductor layer, and including a plurality of alternately stacked quantum barrier layers and quantum well layers, wherein at least a portion of the plurality of quantum well layers has different thicknesses, wherein a thickness of a first quantum well layer most adjacent to the p-type semiconductor layer is less than a thickness of a second quantum well layer adjacent thereto and greater than a thickness of a third quantum well layer, other than the first and second quantum well layers.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: April 28, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Hyun Lee, Ki Ho Park, Suk Ho Yoon, Sang Heon Han, Jae Sung Hyun
  • Patent number: 9018619
    Abstract: A solid state light emitting device according to the present invention comprises an emitter structure having an active region of semiconductor material and a pair of oppositely doped layers of semiconductor material on opposite sides of said active region. The active region emits light at a first wavelength in response to an electrical bias across said doped layers. A quantum well structure is included that is integral to the emitter structure and has a plurality of layers having a composition and thickness such that the quantum well structure absorbs at least some of the light emitted from the active region and re-emits light of at least one different wavelength of light from said first wavelength.
    Type: Grant
    Filed: October 9, 2006
    Date of Patent: April 28, 2015
    Assignee: Cree, Inc.
    Inventor: Adam W. Saxler
  • Patent number: 9018626
    Abstract: Disclosed herein are a ZnO film structure and a method of forming the same. Dislocation density of a ZnO film grown through epitaxial lateral overgrowth (ELOG) is minimized. In order to block a chemical reaction between the ZnO film and a mask layer at the time of performing the ELOG, a material of the mask layer is AlF3, NaF2, SrF, or MgF2. Therefore, the chemical reaction between ZnO and the mask layer is blocked and a transfer of dislocation from a substrate is also blocked.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: April 28, 2015
    Assignee: Gwangju Institute of Science and Technology
    Inventors: Seong-Ju Park, Yong Seok Choi, Jang-Won Kang, Byeong Hyeok Kim
  • Publication number: 20150108427
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate comprising a groove. A buffer layer is formed on a surface of the groove. The buffer layer comprising at least one material chosen from AIN, GaN or AlxGa1-xN, where x is between zero and one. An epitaxially grown semiconductor material is disposed over the buffer layer, at least a portion of the epitaxially grown semiconductor material having a cubic crystalline phase structure. Methods of forming the semiconductor devices are also taught.
    Type: Application
    Filed: March 15, 2013
    Publication date: April 23, 2015
    Inventors: Steven R.J. Brueck, Seung-Chang Lee, Christian Wetzel, Theeradetch Detchprohm, Christoph Stark
  • Patent number: 9012887
    Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: April 21, 2015
    Assignee: Qunano AB
    Inventors: Lars Samuelson, Jonas Ohlsson, Thomas Mårtensson, Patrik Svensson
  • Patent number: 9012921
    Abstract: A light emitting device comprises a first layer of an n-type semiconductor material, a second layer of a p-type semiconductor material, and an active layer between the first layer and the second layer. A light coupling layer is disposed adjacent to one of the first layer and the second layer. In some cases, the light coupling layer is formed by roughening a buffer layer of the light emitting device. The light emitting device includes an electrode in electrical communication with one of the first layer and the second layer through a portion of the light coupling layer.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chao-Kun Lin, Li Yan, Chih-Wei Chuang
  • Patent number: 9012885
    Abstract: A semiconductor chip includes a semiconductor body with a semiconductor layer sequence. An active region intended for generating radiation is arranged between an n-conductive multilayer structure and a p-conductive semiconductor layer. A doping profile is formed in the n-conductive multilayer structure which includes at least one doping peak.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: April 21, 2015
    Assignee: Osram Opto Semiconductors GmbH
    Inventors: Matthias Peter, Tobias Meyer, Alexander Walter, Tetsuya Taki, Juergen Off, Rainer Butendeich, Joachim Hertkorn
  • Patent number: 9015215
    Abstract: Quantum annealing may include applying and gradually removing disorder terms to qubits of a quantum processor, for example superconducting flux qubits of a superconducting quantum processor. A problem Hamiltonian may be established by applying control signals to the qubits, an evolution Hamiltonian established by applying disorder terms, and annealing by gradually removing the disorder terms. Change in persistent current in the qubits may be compensated. Multipliers may mediate coupling between various qubits and a global signal line, for example by applying respective scaling factors. Two global signal lines may be arranged in an interdigitated pattern to couple to respective qubits of a communicatively coupled pair of qubits. Pairs of qubits may be communicatively isolated and used to measure a response of one another to defined signals.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: April 21, 2015
    Assignee: D-Wave Systems, Inc.
    Inventors: Andrew J. Berkley, Richard G. Harris, Mohammad Amin
  • Patent number: 9012888
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first layer of n-type and a second layer of p-type including a nitride semiconductor, a light emitting unit provided between the first and second layers, a first stacked structure provided between the first layer and the light emitting unit, and a second stacked structure provided between the first layer and the first stacked structure. The light emitting unit includes barrier layers and a well layer provided between the barrier layers. The first stacked structure includes third layers including a nitride semiconductor, and fourth layers stacked with the third layers and including GaInN. The fourth layers have a thinner thickness than the well layer. The second stacked structure includes fifth layers including a nitride semiconductor, and sixth layers stacked with the fifth layers and including GaInN. The sixth layers have a thinner thickness than the well layer.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: April 21, 2015
    Assignee: Kabushiki kaisha Toshiba
    Inventors: Mitsuhiro Kushibe, Yasuo Ohba, Hiroshi Katsuno, Kei Kaneko, Shinji Yamada
  • Publication number: 20150102286
    Abstract: An III-nitride quantum well structure includes a GaN base, an InGaN layer and an InGaN covering layer. The GaN base includes a GaN buffering layer, a GaN post extending from the GaN buffering layer, and a GaN pyramid gradually expanding from the GaN post to form a mounting surface. The InGaN layer includes first and second coupling faces. The first coupling face is coupled with the mounting surface. The GaN covering layer includes first and second coupling faces. The first coupling face of the GaN covering layer is coupled with the second coupling face of the InGaN layer.
    Type: Application
    Filed: October 24, 2014
    Publication date: April 16, 2015
    Inventors: I-Kai LO, Yu-Chi HSU, Cheng-Hung SHIH, Wen-Yuan PANG, Ming-Chi CHOU
  • Patent number: 9006709
    Abstract: According to one embodiment, a semiconductor light emitting element includes a first semiconductor layer of an n-type, a second semiconductor layer of a p-type, and a light emitting unit. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer includes a nitride semiconductor. The light emitting unit is provided between the first semiconductor layer and the second semiconductor layer. The light emitting unit includes a plurality of well layers stacked alternately with a plurality of barrier layers. The well layers include a first p-side well layer most proximal to the second semiconductor layer, and a second p-side well layer second most proximal to the second semiconductor layer. A localization energy of excitons of the first p-side well layer is smaller than a localization energy of excitons of the second p-side well layer.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Hajime Nago, Shinya Nunoue
  • Patent number: 9006708
    Abstract: A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of In0.52Al0.48As on an InP substrate, where the In0.52Al0.48As is lattice matched to InP, followed by an AlAsxSb1-x buffer layer on the In0.52Al0.48As layer, an AlAsxSb1-x spacer layer on the AlAsxSb1-x buffer layer, a GaSb quantum well layer on the AlAsxSb1-x spacer layer, an AlAsxSb1-x barrier layer on the GaSb quantum well layer, an In0.2Al0.8Sb etch-stop layer on the AlAsxSb1-x barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: April 14, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Brian R. Bennett, Theresa F. Chick, Mario G. Ancona, John Bradley Boos
  • Patent number: RE45517
    Abstract: A vertical geometry light emitting diode is disclosed that is capable of emitting light in the red, green, blue, violet and ultraviolet portions of the electromagnetic spectrum. The light emitting diode includes a conductive silicon carbide substrate, an InGaN quantum well, a conductive buffer layer between the substrate and the quantum well, a respective undoped gallium nitride layer on each surface of the quantum well, and ohmic contacts in a vertical geometry orientation.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: May 19, 2015
    Assignee: Cree, Inc.
    Inventors: Kathleen Marie Doverspike, John Adam Edmond, Hua-shuang Kong, Heidi Marie Dieringer, David B. Slater, Jr.