Quantum Well Patents (Class 257/14)
  • Publication number: 20140339502
    Abstract: A vertical stack including a p-doped GaN portion, a multi-quantum-well including indium gallium nitride layers, and an n-doped transparent conductive material portion is formed on an insulator substrate. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a surface of the p-doped GaN portion. A selective low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material on the physically exposed surfaces of the p-doped GaN portion, thereby forming an elemental semiconductor material portion. The selective low temperature epitaxy process can be performed at a temperature lower than 600° C., thereby limiting diffusion of materials within the multi-quantum well and avoiding segregation of indium within the multi-quantum well. The light-emitting diode can generate a radiation of a wide range including blue and green lights in the visible wavelength range.
    Type: Application
    Filed: May 20, 2013
    Publication date: November 20, 2014
    Applicant: International Business Machines Corporation
    Inventors: Anirban Basu, Wilfried Haensch, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Publication number: 20140339503
    Abstract: A vertical stack including a p-doped GaN portion, a multi-quantum-well, and an n-doped GaN portion is formed on an insulator substrate. The p-doped GaN portion may be formed above, or below, the multi-quantum-well. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a top surface of the p-doped GaN portion. A selective low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material on the physically exposed surfaces of the p-doped GaN portion, thereby forming an elemental semiconductor material portion. Metallization is performed on a portion of the elemental semiconductor material portions to form an electrical contact structure that provides effective electrical contact to the p-doped GaN portion through the elemental semiconductor material portion.
    Type: Application
    Filed: May 20, 2013
    Publication date: November 20, 2014
    Applicant: International Business Machines Corporation
    Inventors: Anirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi
  • Patent number: 8890115
    Abstract: Vapor-liquid-solid growth of nanowires is tailored to achieve complex one-dimensional material geometries using phase diagrams determined for nanoscale materials. Segmented one-dimensional nanowires having constant composition display locally variable electronic band structures that are determined by the diameter of the nanowires. The unique electrical and optical properties of the segmented nanowires are exploited to form electronic and optoelectronic devices. Using gold-germanium as a model system, in situ transmission electron microscopy establishes, for nanometer-sized Au—Ge alloy drops at the tips of Ge nanowires (NWs), the parts of the phase diagram that determine their temperature-dependent equilibrium composition. The nanoscale phase diagram is then used to determine the exchange of material between the NW and the drop. The phase diagram for the nanoscale drop deviates significantly from that of the bulk alloy.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: November 18, 2014
    Assignee: Brookhaven Science Associates, LLC
    Inventors: Eli Anguelova Sutter, Peter Werner Sutter
  • Patent number: 8890113
    Abstract: A light-emitting device epitaxially-grown on a GaAs substrate which contains an active region composed of AlxGa1-xAs alloy or of related superlattices of this materials system is disclosed. This active region either includes tensile-strained GaP-rich insertions aimed to increase the forbidden gap of the active region targeting the bright red, orange, yellow, or green spectral ranges, or is confined by regions with GaP-rich insertions aimed to increase the barrier height for electrons in the conduction band preventing the leakage of the nonequilibrium carriers outside of the light-generation region.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: November 18, 2014
    Inventors: Nikolay Ledentsov, James Lott, Vitaly Shchukin
  • Patent number: 8883266
    Abstract: A method of fabricating quantum confinements is provided. The method includes depositing, using a deposition apparatus, a material layer on a substrate, where the depositing includes irradiating the layer, before a cycle, during a cycle, and/or after a cycle of the deposition to alter nucleation of quantum confinements in the material layer to control a size and/or a shape of the quantum confinements. The quantum confinements can include quantum wells, nanowires, or quantum dots. The irradiation can be in-situ or ex-situ with respect to the deposition apparatus. The irradiation can include irradiation by photons, electrons, or ions. The deposition is can include atomic layer deposition, chemical vapor deposition, MOCVD, molecular beam epitaxy, evaporation, sputtering, or pulsed-laser deposition.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: November 11, 2014
    Assignees: The Board of Trustees of the Leland Stanford Junior University, Honda Patents & Technologies North America, LLC
    Inventors: Timothy P. Holme, Andrei Iancu, Hee Joon Jung, Michael C Langston, Munekazu Motoyama, Friedrich B. Prinz, Takane Usui, Hitoshi Iwadate, Neil Dasgupta, Cheng-Chieh Chao
  • Patent number: 8884265
    Abstract: An InGaAs n-channel quantum well heterostructure for use in a complementary transistor having a Sb-based p-channel. The heterostructure includes a buffer layer having a lattice constant intermediate that of the n- and p-channel materials and which is configured to accommodate the strain produced by a lattice-constant mismatch between the n-channel and p-channel materials.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: November 11, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Brian R. Bennett, John Bradley Boos, Theresa F. Chick, James G. Champlain
  • Patent number: 8878161
    Abstract: A strain-balanced quantum well tunnel junction (SB-QWTJ) device. QW structures are formed from alternating quantum well and barrier layers situated between n++ and p++ layers in a tunnel junction formed on a substrate. The quantum well layers exhibit a compressive strain with respect to the substrate, while the barrier layers exhibit a tensile strain. The composition and layer thicknesses of the quantum well and barrier layers are configured so that the compressive and tensile strains in the structure are balanced.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: November 4, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Matthew Lumb, Michael K. Yakes, María González, Christopher Bailey, Robert J. Walters
  • Patent number: 8878160
    Abstract: A device includes a semiconductor structure comprising a III-phosphide light emitting layer disposed between an n-type region and a p-type region. A transparent, conductive oxide is disposed in direct contact with the n-type region. In some embodiments, a total thickness of semiconductor material between the light emitting layer and the transparent, conductive oxide is less than one micron.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: November 4, 2014
    Assignee: Koninklijke Philips N.V.
    Inventors: Frédéric Georges Michel Dupont, John Edward Epler
  • Patent number: 8878243
    Abstract: Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: November 4, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 8878232
    Abstract: An MQW-structure light-emitting layer is formed by alternately stacking InGaN well layers and AlGaN barrier layers. Each well layer and each barrier layer are formed so as to satisfy the following relations: 12.9??2.8x+100y?37 and 0.65?y?0.86, or to satisfy the following relations: 162.9?7.1x+10z?216.1 and 3.1?z?9.2, here x represents the Al compositional ratio (mol %) of the barrier layer, and y represents the difference in bandgap energy (eV) between the barrier layer and the well layer, and z represents the In compositional ratio (mol %) of the well layer.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: November 4, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Ryo Nakamura
  • Publication number: 20140319461
    Abstract: A single-walled carbon nanotube-based planar photodetector includes a substrate; a first electrode and a second electrode disposed on the substrate and spaced apart from each other; a plurality of single-walled carbon nanotubes, each of the plurality of single-walled carbon nanotubes contacting the first electrode and the second electrode; and an adsorbent attached to a surface of at least one of the plurality of single-walled carbon nanotubes, wherein the adsorbent is capable of doping the at least one of the plurality of single-walled carbon nanotubes by photo-excitation.
    Type: Application
    Filed: April 26, 2013
    Publication date: October 30, 2014
    Applicants: THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY, SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-jun PARK, Steve PARK, Zhenan BAO
  • Publication number: 20140319459
    Abstract: Methods for fabricating self-aligned heterostructures and semiconductor arrangements using silicon nanowires are described.
    Type: Application
    Filed: July 11, 2014
    Publication date: October 30, 2014
    Inventors: Andrew P. HOMYK, Michael D. HENRY, Axel SCHERER, Sameer WALAVALKAR
  • Patent number: 8872232
    Abstract: There is embodied a high-reliability high-voltage resistance compound semiconductor device capable of improving the speed of device operation, being high in avalanche resistance, being resistant to surges, eliminating the need to connect any external diodes when applied to, for example, an inverter circuit, and achieving stable operation even if holes are produced, in addition to alleviating the concentration of electric fields on a gate electrode and thereby realizing a further improvement in voltage resistance. A gate electrode is formed so as to fill an electrode recess formed in a structure of stacked compound semiconductors with an electrode material through a gate insulation film, and a field plate recess formed in the structure of stacked compound semiconductors is filled with a p-type semiconductor, thereby forming a field plate the p-type semiconductor layer of which has contact with the structure of stacked compound semiconductors.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: October 28, 2014
    Assignee: Fujitsu Limited
    Inventor: Tadahiro Imada
  • Publication number: 20140312301
    Abstract: Described is a method for producing a semiconductor device (100), in which at least one column-shaped or wall-shaped semiconductor device (10, 20) extending in a main direction (z) is formed on a substrate (30), wherein at least two sections (11, 13, 21, 23) of a first crystal type and one section (12, 22) of a second crystal type therebetween are formed in an active region (40), each section with a respective predetermined height (h1, h2), wherein the first and second crystal types have different lattice constants and each of the sections of the first crystal type has a lattice strain which depends on the lattice constants in the section of the second crystal type.
    Type: Application
    Filed: November 9, 2012
    Publication date: October 23, 2014
    Applicant: Forschungsverbund Berlin e.V.
    Inventors: Oliver Brandt, Lutz Geelhaar, Vladimir Kaganer, Martin Woelz
  • Publication number: 20140312302
    Abstract: The present invention is based on a unique design of a novel structure, which incorporates two quantum dots of a different bandgap separated by a tunneling barrier. Upconversion is expected to occur by the sequential absorption of two photons. In broad terms, the first photon excites an electron-hole pair via intraband absorption in the lower bandgap dot, leaving a confined hole and a relatively delocalized electron. The second absorbed photon can lead, either directly or indirectly, to further excitation of the hole, enabling it to then cross the barrier layer. This, in turn, is followed by radiative recombination with the delocalized electron.
    Type: Application
    Filed: April 22, 2014
    Publication date: October 23, 2014
    Inventors: Dan ORON, Zvi DEUTSCH, Lior NEEMAN
  • Patent number: 8866127
    Abstract: A nitride semiconductor light-emitting element uses a non-polar plane as its growing plane. A GaN/InGaN multi-quantum well active layer includes an Si-doped layer which is arranged in an InyGa1-yN (where 0<y<1) well layer, between the InyGa1-yN (where 0<y<1) well layer and a GaN barrier layer, or in a region of the GaN barrier layer that is located closer to the InyGa1-yN (where 0<y<1) well layer. A concentration of Si at one interface of the GaN barrier layer on a growing direction side is either zero or lower than a concentration of Si in the Si-doped layer.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: October 21, 2014
    Assignee: Panasonic Corporation
    Inventors: Kunimasa Takahashi, Ryou Kato, Shunji Yoshida, Toshiya Yokogawa
  • Patent number: 8866126
    Abstract: An epitaxial structure for a III-Nitride based optical device, comprising an active layer with anisotropic strain on an underlying layer, where a lattice constant and strain in the underlying layer are partially or fully relaxed in at least one direction due to a presence of misfit dislocations, so that the anisotropic strain in the active layer is modulated by the underlying layer.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: October 21, 2014
    Assignee: The Regents of the University of California
    Inventors: Hiroaki Ohta, Feng Wu, Anurag Tyagi, Arpan Chakraborty, James S. Speck, Steven P. DenBaars, Shuji Nakamura, Erin C. Young
  • Patent number: 8866125
    Abstract: Various embodiments provide materials and methods for integrating exemplary heterostructure field-effect transistor (HFET) driver circuit or thyristor driver circuit with LED structures to reduce or eliminate resistance and/or inductance associated with their conventional connections.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: October 21, 2014
    Assignee: STC.UNM
    Inventor: Stephen D. Hersee
  • Publication number: 20140306180
    Abstract: There are provided an electronic device including a first electrode, a second electrode and a photoelectric conversion layer sandwiched between the first electrode and the second electrode, the first electrode including an amorphous oxide composed of at least a quaternary compound of indium, gallium and/or aluminum, zinc and oxygen, and a difference between a work function value of the second electrode and a work function value of the first electrode being 0.4 eV or more; and a method of producing an electrode for the electronic device.
    Type: Application
    Filed: April 9, 2014
    Publication date: October 16, 2014
    Applicant: Sony Corporation
    Inventors: Toshiki MORIWAKI, Toru UDAKA
  • Patent number: 8859354
    Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a quantum well layer on the semiconductor substrate. The method also includes forming a potential energy barrier layer on the semiconductor substrate, and forming an isolation structure to isolate different transistor regions. Further, the method includes patterning the transistor region to form trenches by removing portions of the quantum well layer and the potential energy barrier layer corresponding to a source region and a drain region, and filling trenches with a semiconductor material to form a source and a drain. Further, the method also includes forming a gate structure on a portion of the quantum well layer and the potential energy barrier layer corresponding to a gate region.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Manufacturing International Corp
    Inventor: Deyuan Xiao
  • Publication number: 20140299741
    Abstract: An apparatus comprises a graphene film; a first arrangement of quantum dots of a first type located in contact with the graphene film as a first monolayer; a second arrangement of quantum dots of a second type located in contact with the graphene film as a second monolayer; an input voltage source connected to an end of the graphene film; and an output voltage probe connected to the graphene film between the first arrangement of quantum dots and the second arrangement of quantum dots.
    Type: Application
    Filed: April 5, 2013
    Publication date: October 9, 2014
    Inventor: Alan Colli
  • Patent number: 8853668
    Abstract: A light emitting device comprises a first layer having an n-type Group III-V semiconductor, a second layer adjacent to the first layer, the second layer comprising an active material that generates light upon the recombination of electrons and holes. The active material in some cases has one or more V-pits at a density between about 1 V-pit/?m2 and 30 V-pits/?m2. The light emitting device includes a third layer adjacent to the second layer, the third layer comprising a p-type Group III-V semiconductor.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: October 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jeff Ramer, Steve Ting
  • Patent number: 8853672
    Abstract: A gallium nitride substrate includes a plurality of physical level differences in a surface thereof. All the physical level differences existing in the surface have a dimension of not more than 4 ?m. A relationship of (H?L)/H×100?80 is satisfied in all the physical level differences, where H represents a higher value of cathodoluminescence emission intensities of a wavelength corresponding to a bandgap of the gallium nitride substrate, and L represents a lower value of the cathodoluminescence emission intensities, the cathodoluminescence emission intensities being measured in an upper step and a lower step of the physical level difference.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: October 7, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventor: Shunsuke Yamamoto
  • Patent number: 8853670
    Abstract: In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12 with a front surface 10a having a specific plane orientation. Accordingly, a high-resistivity layer is prevented from being formed at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Consequently, it is possible to improve the emission intensity of the semiconductor device 100.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: October 7, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Keiji Ishibashi
  • Publication number: 20140291613
    Abstract: A multiple quantum well structure including a plurality of well-barrier pairs arranged along a direction is provided. Each of the well-barrier pairs includes a barrier layer and a well layer adjacent to the barrier layer. The barrier layers and the well layers of the well-barrier pairs are disposed alternately. A ratio of a thickness of the well layer in the direction to a thickness of the barrier layer in the direction in each well-barrier pair is a well-barrier thickness ratio, and the well-barrier thickness ratios of a part of the well-barrier pairs gradually increase along the direction.
    Type: Application
    Filed: March 27, 2013
    Publication date: October 2, 2014
    Applicant: Genesis Photonics Inc.
    Inventors: Ching-Liang Lin, Shen-Jie Wang, Yen-Lin Lai
  • Patent number: 8847201
    Abstract: Provided are quantum dots having a gradual composition gradient shell structure which have an improved luminous efficiency and optical stability, and a method of manufacturing the quantum dots in a short amount of time at low cost. In the method, the quantum dots can be manufactured in a short amount of time at low cost using a reactivity difference between semiconductor precursors, unlike in uneconomical and inefficient conventional methods where shells are formed after forming cores and performing cleaning and redispersion processes. Also, formation of the cores is followed by formation of shells having a composition gradient.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: September 30, 2014
    Assignee: SNU R&DB Foundation
    Inventors: Kookheon Char, Seong Hoon Lee, Wan Ki Bae, Hyuck Hur
  • Patent number: 8847200
    Abstract: A memory cell is provided, the memory cell including a steering element having a vertically-oriented p-i-n junction, and a carbon nanotube fabric. The steering element and the carbon nanotube fabric are arranged electrically in series, and the entire memory cell is formed above a substrate. Other aspects are also provided.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: September 30, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Scott Brad Herner, Roy E. Scheuerlein
  • Publication number: 20140264272
    Abstract: A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials.
    Type: Application
    Filed: May 27, 2014
    Publication date: September 18, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Anthony J. Lochtefeld
  • Publication number: 20140264271
    Abstract: A ferroelectric memory device includes a memory layer, made of a silicon-based ferroelectric memory material. The silicon-based ferroelectric memory material includes a mesoporous silica film with nanopores and atomic polar structures on inner walls of the nanopores. The atomic polar structures are formed by asymmetrically bonding metal ions to silicon-oxygen atoms on the inner walls, and the silicon-based ferroelectric memory material includes semiconductor quantum dots, metal quantum dots and metal-semiconductor alloy quantum dots.
    Type: Application
    Filed: March 18, 2013
    Publication date: September 18, 2014
    Applicant: NATIONAL APPLIED RESEARCH LABORATORIES
    Inventors: Jia-Min Shieh, Wen-Hsien Huang, Yu-Chung Lien, Chang-Hong Shen, Fu-Ming Pan, Hao-Chung Kuo
  • Publication number: 20140264270
    Abstract: This invention relates to multiband detector and multiband image sensing devices, and their manufacturing technologies. The innovative detector (or image sensing) provides significant broadband capability covering the wavelengths from within ultra-violet (UV) to long-Infrared, and it is achieved in a single element. More particularly, this invention is related to the multiband or dual band detectors, which can not only detect the broad spectrum wavelengths ranges from within as low as UV to the wavelengths as high as 25 ?m, but also band selection capability. This invention is also related to the multiband detector arrays or image sensing device for multicolor imaging, sensing, and advanced communication.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: BANPIL PHOTONICS, INC.
    Inventor: Achyut Dutta
  • Publication number: 20140264258
    Abstract: Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Moonsub Shim, Nuri Oh, You Zhai, Sooji Nam, Peter Trefonas, Kishori Deshpande, Jake Joo
  • Patent number: 8835904
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a p-type layer, and a light emitting unit provided between the n-type layer and the p-type layer and including barrier layers and well layers. At least one of the barrier layers includes first and second portion layers. The first portion layer is disposed on a side of the n-type layer. The second portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the first portion layer. At least one of the well layers includes third and fourth portion layers. The third portion layer is disposed on a side of the n-type layer. The fourth portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the third portion layer.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Hikosaka, Koichi Tachibana, Hajime Nago, Shinya Nunoue
  • Patent number: 8835901
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer, a light emitting part, and a multilayered structural body. The light emitting part is provided between the first and second semiconductor layers and includes barrier layers and well layers alternately stacked. The multilayered structural body is provided between the first semiconductor layer and the light emitting part and includes high energy layers and low energy layers alternately stacked. An average In composition ratio on a side of the second semiconductor is higher than that on a side of the first semiconductor in the multilayered structural body. An average In composition ratio on a side of the second semiconductor is higher than that on a side of the first semiconductor in the light emitting part.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
  • Patent number: 8836446
    Abstract: A wave amplitude modulator for modulating a transmitted electromagnetic wave includes one or multiple self-gated capacitively coupled pair(s) of electron layers such as semiconductor or semimetal layers. Two electrical contacts are placed to each layer of electrons of the self-gated pair(s), and a power source is electrically connected to them. The power source, by varying the voltage applied between layers of electrons, tunes the electron density thereof, thereby adjusting the optical conductivity thereof, and the change in the optical conductivity of the layers of electrons causes an amplitude modulation of the transmitted electromagnetic wave passing through the capacitively coupled layers of electrons.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: September 16, 2014
    Assignee: University of Notre Dame du Lac
    Inventors: Berardi Sensale-Rodriguez, Huili (Grace) Xing, Rusen Yan, Michelle M. Kelly, Tian Fang, Debdeep Jena, Lei Liu
  • Publication number: 20140252316
    Abstract: Described are ZnxCd1-xSySe1-y/ZnSzSe1-z core/shell nanocrystals, CdTe/CdS/ZnS core/shell/shell nanocrystals, optionally ally doped Zn(S,Se,Te) nano- and quantum wires, and SnS quantum sheets or ribbons, methods for making the same, and their use in biomedical and photonic applications, such as sensors for analytes in cells and preparation of field effect transistors.
    Type: Application
    Filed: October 3, 2012
    Publication date: September 11, 2014
    Inventors: Hao Yan, Zhengtao Deng, Yan Liu
  • Publication number: 20140252312
    Abstract: A strain-balanced quantum well tunnel junction (SB-QWTJ) device. QW structures are formed from alternating quantum well and barrier layers situated between n++ and p++ layers in a tunnel junction formed on a substrate. The quantum well layers exhibit a compressive strain with respect to the substrate, while the barrier layers exhibit a tensile strain. The composition and layer thicknesses of the quantum well and barrier layers are configured so that the compressive and tensile strains in the structure are balanced.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 11, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Matthew Lumb, Michael K. Yakes, Marla González, Christopher Bailey, Robert J. Walters
  • Patent number: 8828764
    Abstract: Implementations and techniques for coupled asymmetric quantum confinement structures are generally disclosed.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: September 9, 2014
    Assignee: University of Seoul Industry Cooperation Foundation
    Inventor: Doyeol Ahn
  • Patent number: 8822977
    Abstract: A photodetector and a method of manufacturing the photodetector are provided, in which variation in sensitivity is suppressed over the near-infrared region from the short wavelength side including 1.3 ?m to the long wavelength side. The photodetector includes, on an InP substrate, an absorption layer of a type II multiple quantum well structure comprising a repeated structure of a GaAsSb layer and an InGaAs layer, and has sensitivity in the near-infrared region including wavelengths of 1.3 ?m and 2.0 ?m. The ratio of the sensitivity at the wavelength of 1.3 ?m to the sensitivity at the wavelength of 2.0 ?m is not smaller than 0.5 but not larger than 1.6.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: September 2, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Takashi Ishizuka, Kei Fujii, Hideaki Nakahata, Youichi Nagai, Hiroshi Inada, Yasuhiro Iguchi
  • Patent number: 8822975
    Abstract: A method of manufacturing a semiconductor laser having an end face window structure, by growing over a substrate a nitride type Group III-V compound semiconductor layer including an active layer including a nitride type Group III-V compound semiconductor containing at least In and Ga, the method includes the steps of: forming a mask including an insulating film over the substrate, at least in the vicinity of the position of forming the end face window structure; and growing the nitride type Group III-V compound semiconductor layer including the active layer over a part, not covered with the mask, of the substrate.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: September 2, 2014
    Assignee: Sony Corporation
    Inventors: Masaru Kuramoto, Eiji Nakayama, Yoshitsugu Ohizumi
  • Patent number: 8816325
    Abstract: A quantum bit computing architecture includes a plurality of single spin memory donor atoms embedded in a semiconductor layer, a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, wherein a first voltage applied across at least one pair of the aligned quantum dot and donor atom controls a donor-quantum dot coupling. A method of performing quantum computing in a scalable architecture quantum computing apparatus includes arranging a pattern of single spin memory donor atoms in a semiconductor layer, forming a plurality of quantum dots arranged with the semiconductor layer and aligned with the donor atoms, applying a first voltage across at least one aligned pair of a quantum dot and donor atom to control a donor-quantum dot coupling, and applying a second voltage between one or more quantum dots to control a Heisenberg exchange J coupling between quantum dots and to cause transport of a single spin polarized electron between quantum dots.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: August 26, 2014
    Assignee: The Regents of the University of California
    Inventors: Thomas Schenkel, Cheuk Chi Lo, Christoph Weis, Stephen Lyon, Alexei Tyryshkin, Jeffrey Bokor
  • Patent number: 8816320
    Abstract: A GaN-containing semiconductor light emitting device includes: an n-type semiconductor layer formed of GaN-containing semiconductor, an active layer formed on the n-type semiconductor layer, formed of GaN-containing semiconductor, and having a multiple quantum well structure including a plurality of barrier layers and well layers stacked alternately, and a p-type semiconductor layer formed on the active layer and formed of GaN-containing semiconductor, wherein: the barrier layers comprise: a first barrier layer disposed nearest to the n-type semiconductor layer among the barrier layers and formed of a GaN/AlGaN layer, and second barrier layers disposed nearer to the p-type semiconductor layer than the first barrier layer and including an InGaN/GaN layer which has a layered structure of a InGaN sublayer and a GaN sublayer; and the well layers are each formed of an InGaN layer having a narrower band gap than that in the InGaN sublayer.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: August 26, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Sho Iwayama, Masahiko Moteki
  • Patent number: 8816324
    Abstract: Disclosed is a semiconductor device (10) which comprises a glass substrate (12), a lower electrode layer (14), an n-type doped polycrystalline silicon semiconductor layer (16), a low-temperature insulating film (20) in which openings (22, 23) that serve as nuclei for growth of a nanowire (32) are formed, the nanowire (32) that is grown over the low-temperature insulating film (20) and has a core-shell structure, an insulating layer (50) that surrounds the nanowire (32), and an upper electrode layer (52). The nanowire (32) comprises an n-type GaAs core layer and a p-type GaAs shell layer. Alternatively, the nanowire can be formed as a nanowire having a quantum well structure, and InAs that can allow reduction of the process temperature can be used for the nanowire.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: August 26, 2014
    Assignees: National University Corporation Hokkaido University, Sharp Kabushiki Kaisha
    Inventors: Takashi Fukui, Katsuhiro Tomioka, Junichi Motohisa, Shinjiroh Hara
  • Patent number: 8816319
    Abstract: An optical device has a gallium and nitrogen containing substrate including a surface region and a strain control region, the strain control region being configured to maintain a quantum well region within a predetermined strain state. The device also has a plurality of quantum well regions overlying the strain control region.
    Type: Grant
    Filed: November 3, 2011
    Date of Patent: August 26, 2014
    Assignee: Soraa Laser Diode, Inc.
    Inventors: James W. Raring, Christiane Poblenz
  • Publication number: 20140231749
    Abstract: Disclosed are a nano particle, a nano particle complex and a method of fabricating the nano particle. The nano particle includes a compound semiconductor having a first metal element and a second metal element. The property of the nano particle is readily controlled depending on the composition of the first and second metal elements.
    Type: Application
    Filed: July 16, 2012
    Publication date: August 21, 2014
    Applicants: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, LG INNOTEK CO., LTD.
    Inventors: Yu Won Lee, Gwang Hei Choi, Jin Kyu Lee, Yun Ku Jung
  • Patent number: 8809843
    Abstract: A photoelectrode, methods of making and using, including systems for water-splitting are provided. The photoelectrode can be a semiconductive material having a photocatalyst such as nickel or nickel-molybdenum coated on the material.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: August 19, 2014
    Assignee: California Institute of Technology
    Inventors: James R. McKone, Harry B. Gray, Nathan S. Lewis, Bruce Brunschwig, Emily L. Warren, Shannon W. Boettcher, Matthew J. Bierman
  • Patent number: 8809834
    Abstract: Apparatuses capable of and techniques for detecting long wavelength radiation are provided.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: August 19, 2014
    Assignee: University of Seoul Industry Cooperation Foundation
    Inventor: Doyeol Ahn
  • Patent number: 8809867
    Abstract: Lateral epitaxial overgrowth of non-polar III-nitride seed layers reduces threading dislocations in the non-polar III-nitride thin films. First, a thin patterned dielectric mask is applied to the seed layer. Second, a selective epitaxial regrowth is performed to achieve a lateral overgrowth based on the patterned mask. Upon regrowth, the non-polar III-nitride films initially grow vertically through openings in the dielectric mask before laterally overgrowing the mask in directions perpendicular to the vertical growth direction. Threading dislocations are reduced in the overgrown regions by (1) the mask blocking the propagation of dislocations vertically into the growing film and (2) the bending of dislocations through the transition from vertical to lateral growth.
    Type: Grant
    Filed: September 10, 2007
    Date of Patent: August 19, 2014
    Assignee: The Regents of the University of California
    Inventors: Michael D. Craven, Steven P. Denbaars, James S. Speck, Shuji Nakamura
  • Publication number: 20140225063
    Abstract: A photodetector includes one or more photodiodes and a signal processing circuit. Each photodiode includes a transparent first electrode, a second electrode, and a heterojunction interposed between the first electrode and the second electrode. Each heterojunction includes a quantum dot layer and a fullerene layer disposed directly on the quantum dot layer. The signal processing circuit is in signal communication each the second electrode. The photodetector may be responsive to wavelengths in the infrared, visible, and/or ultraviolet ranges. The quantum dot layer may be treated with a chemistry that increases the charge carrier mobility of the quantum dot layer.
    Type: Application
    Filed: April 16, 2014
    Publication date: August 14, 2014
    Applicant: Research Triangle Institute
    Inventors: ETHAN KLEM, JOHN LEWIS
  • Patent number: 8802517
    Abstract: A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: August 12, 2014
    Assignee: Intel Corporation
    Inventors: Suman Datta, Mantu K. Hudait, Mark L. Doczy, Jack T. Kavalieros, Majumdar Amian, Justin K. Brask, Been-Yih Jin, Matthew V. Metz, Robert S. Chau
  • Patent number: 8803127
    Abstract: In at least one embodiment, an infrared (IR) sensor comprising a thermopile is provided. The thermopile comprises a substrate and an absorber. The absorber is positioned above the substrate and a gap is formed between the absorber and the substrate. The absorber receives IR from a scene and generates an electrical output indicative of a temperature of the scene. The absorber is formed of a super lattice quantum well structure such that the absorber is thermally isolated from the substrate. In another embodiment, a method for forming an infrared (IR) detector is provided. The method comprises forming a substrate and forming an absorber with a plurality of alternating first and second layers with a super lattice quantum well structure. The method further comprises positioning the absorber about the substrate such that a gap is formed to cause the absorber to be suspended about the substrate.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: August 12, 2014
    Assignee: UD Holdings, LLC
    Inventor: David Kryskowski