Quantum Well Patents (Class 257/14)
  • Publication number: 20140217284
    Abstract: Photodetectors, methods of fabricating the same, and methods using the same to detect radiation are described. A photodetector can include a first electrode, a light sensitizing layer, an electron blocking/tunneling layer, and a second electrode. Infrared-to-visible upconversion devices, methods of fabricating the same, and methods using the same to detect radiation are also described. An Infrared-to-visible upconversion device can include a photodetector and an OLED coupled to the photodetector.
    Type: Application
    Filed: July 2, 2012
    Publication date: August 7, 2014
    Applicants: NANOHOLDINGS, LLC, University of Florida Research Foundation, Inc.
    Inventors: Franky So, Do Young Kim, Jae Woong Lee, Bhabendra K. Pradhan
  • Publication number: 20140217363
    Abstract: A semiconductor device including a heterostructure having at least one low-resistivity p-type GaSb quantum well is provided. The heterostructure includes a layer of In0.52Al0.48As on an InP substrate, where the In0.52Al0.48As is lattice matched to InP, followed by an AlAsxSb1-x buffer layer on the In0.52Al0.48As layer, an AlAsxSb1-x spacer layer on the AlAsxSb1-x buffer layer, a GaSb quantum well layer on the AlAsxSb1-x spacer layer, an AlAsxSb1-x barrier layer on the GaSb quantum well layer, an In0.2Al0.8Sb etch-stop layer on the AlAsxSb1-x barrier layer, and an InAs cap. The semiconductor device is suitable for use in low-power electronic devices such as field-effect transistors.
    Type: Application
    Filed: May 16, 2013
    Publication date: August 7, 2014
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Brian R. Bennett, Theresa F. Chick, Mario G. Ancona, John Bradley Boos
  • Publication number: 20140217362
    Abstract: The present invention discloses a method for manufacturing a semiconductor device, which comprises: forming a plurality of fins on a substrate, which extend along a first direction and have rhombus-like cross-sections; forming a gate stack structure on each fin, which traverses the plurality of fins and extends along a second direction; wherein a portion in each fin that is under the gate stack structure forms a channel region of the device, and portions in each fin that are at both sides of the gate stack structure along the first direction form source and drain regions. The semiconductor device and its manufacturing method according to the present invention use rhombus-like fins to improve the gate control capability to effectively suppress the short channel effect, moreover, an epitaxial quantum well is used therein to better limit the carriers, thus improving the device drive capability.
    Type: Application
    Filed: October 12, 2012
    Publication date: August 7, 2014
    Inventors: Xiaolong Ma, Huaxiang Yin, Sen Xu, Huilong Zhu
  • Publication number: 20140209789
    Abstract: The present invention relates to a mixed multi-spectrum light-sensing pixel group, a light-sensing device, and a light-sensing system. The mixed multi-spectrum light-sensing pixel group includes at least one chemical coating light-sensing pixel and at least one semiconductor light-sensing pixel. In the present invention, the chemical coating light-sensing pixel and the semiconductor light-sensing pixel are combined to generate a mixed multi-spectrum light-sensing pixel, numerous color signals and other spectral signals may be simultaneously obtained, energy of incident photons can be maximally utilized, and the theoretical upper limit of photoelectric conversion efficiency is achieved or approximately achieved; colors may be completely reconstructed, and meanwhile images of other spectrums including an ultraviolet image, a near-infrared image, and a far-infrared image are obtained.
    Type: Application
    Filed: June 24, 2011
    Publication date: July 31, 2014
    Inventor: Xiaoping Hu
  • Patent number: 8791505
    Abstract: A semiconductor device includes: a second nitride semiconductor layer formed on a first nitride semiconductor layer, and having a larger band gap than the first nitride semiconductor layer; and an electrode filling a recess formed in the first and second nitride semiconductor layers. The first nitride semiconductor layer has a two-dimensional electron gas layer immediately below the second nitride semiconductor layer. The electrode and the second nitride semiconductor layer are in contact with each other at a first contact interface. The electrode and a portion of the first nitride semiconductor layer corresponding to the two-dimensional electron gas layer are in contact with each other at a second contact interface connected below the first contact interface. The first contact interface is formed such that a width of the recess increases upward. The second contact interface is more steeply inclined than the first contact interface.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: July 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Yusuke Kinoshita, Satoshi Tamura, Yoshiharu Anda, Tetsuzo Ueda
  • Publication number: 20140203242
    Abstract: In the nitride semiconductor device of the present invention, an active layer 12 is sandwiched between a p-type nitride semiconductor layer 11 and an n-type nitride semiconductor layer 13. The active layer 12 has, at least, a barrier layer 2a having an n-type impurity; a well layer 1a made of a nitride semiconductor that includes In; and a barrier layer 2c that has a p-type impurity, or that has been grown without being doped. An appropriate injection of carriers into the active layer 12 becomes possible by arranging the barrier layer 2c nearest to the p-type layer side.
    Type: Application
    Filed: March 20, 2014
    Publication date: July 24, 2014
    Applicant: NICHIA CORPORATION
    Inventor: Tokuya KOZAKI
  • Publication number: 20140206096
    Abstract: Nanocrystals having an indium-based core and methods for making them and using them to construct core-shell nanocrystals are described. These core-shell nanocrystals are highly stable and provide higher quantum yields than known nanocrystals of similar composition, and they provide special advantages for certain applications because of their small size.
    Type: Application
    Filed: January 31, 2014
    Publication date: July 24, 2014
    Applicant: LIFE TECHNOLOGIES CORPORATION
    Inventors: Joseph BARTEL, Yongfen Chen, Eric Tulsky, Joseph Treadway
  • Patent number: 8785904
    Abstract: A light emitting device with reduced forward voltage Vf by utilizing the excellent lateral conduction of two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG) structure and, more specifically, by improving the vertical conduction of 2DEG and 2DHG structure by means of vertical conductive passages formed in 2DEG and 2DHG structure. The conductive passages are formed via discontinuities in 2DEG and 2DHG structure. The discontinuities can be in the form of openings by etching 2DEG or 2DHG structure, or in the form of voids by growing 2DEG or 2DHG structure on a rough surface via epitaxy facet control. The discontinuities can be formed by vertical displacement of 2DEG structure. A method is provided for manufacturing a light emitting device with reduced forward voltage same.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: July 22, 2014
    Assignee: InvenLux Corporation
    Inventors: Jianping Zhang, Hongmei Wang, Chunhui Yan
  • Patent number: 8784703
    Abstract: A method of making a colloidal solution of high confinement semiconductor nanocrystals includes: forming a first solution by combining a solvent, growth ligands, and at most one semiconductor precursor; heating the first solution to the nucleation temperature; and adding to the first solution, a second solution having a solvent, growth ligands, and at least one additional and different precursor than that in the first solution to form a crude solution of nanocrystals having a compact homogenous semiconductor region. The method further includes: waiting 0.5 to 20 seconds and adding to the crude solution a third solution having a solvent, growth ligands, and at least one additional and different precursor than those in the first and second solutions; and lowering the growth temperature to enable the formation of a gradient alloy region around the compact homogenous semiconductor region, resulting in the formation of a colloidal solution of high confinement semiconductor nanocrystals.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: July 22, 2014
    Assignee: Eastman Kodak Company
    Inventors: Keith Brian Kahen, Matthew Holland, Sudeep Pallikkara Kuttiatoor
  • Patent number: 8785906
    Abstract: An area illumination inorganic electro-luminescent device including a substrate; and an array of one or more commonly addressed, light-emitting elements. Each commonly-addressed, light-emitting element includes a first electrode layer formed over the substrate, one or more light-emitting layers formed over the first electrode layer and a second electrode layer formed over the light-emitting layer. The light-emitting layers include multiple core/shell quantum dot emitters formed in a common polycrystalline semiconductor matrix, and a number of different core/shell quantum dot emitters emit light with a spectral power distribution having a peak and a FWHM bandwidth, such that the peak wavelengths differ by an amount less than or equal to the average FWHM bandwidth of the different core/shell quantum dot emitters within the range of 460 to 670 nm.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: July 22, 2014
    Assignee: Eastman Kodak Company
    Inventors: Michael E. Miller, Paul J. Kane, Ronald S. Cok
  • Patent number: 8779412
    Abstract: There is provided a semiconductor light emitting device including: first and second conductivity type semiconductor layers; and an active layer disposed between the first and second conductivity type semiconductor layers and having a structure in which a plurality of quantum barrier layers and a plurality of quantum well layers are alternately disposed, wherein at least one of the plurality of quantum well layers includes a first region in which band gap energy is reduced through a first slope and a second region in which band gap energy is reduced through a second slope different from the first slope. The influence of polarization is minimized by adjusting the shape of the band gap of the quantum well layer, crystallinity and internal quantum efficiency can be enhanced.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: July 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Heon Han, Do Young Rhee, Jong Hyun Lee, Jin Young Lim, Young Sun Kim
  • Patent number: 8778780
    Abstract: Techniques for fabricating metal devices, such as vertical light-emitting diode (VLED) devices, power devices, laser diodes, and vertical cavity surface emitting laser devices, are provided. Devices produced accordingly may benefit from greater yields and enhanced performance over conventional metal devices, such as higher brightness of the light-emitting diode and increased thermal conductivity. Moreover, the invention discloses techniques in the fabrication arts that are applicable to GaN-based electronic devices in cases where there is a high heat dissipation rate of the metal devices that have an original non- (or low) thermally conductive and/or non- (or low) electrically conductive carrier substrate that has been removed.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: July 15, 2014
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventors: Trung-Tri Doan, Chen-Fu Chu, Hao-Chun Cheng, Feng-Hsu Fan
  • Patent number: 8772758
    Abstract: A method for fabricating a III-nitride based semiconductor device, including (a) growing one or more buffer layers on or above a semi-polar or non-polar GaN substrate, wherein the buffer layers are semi-polar or non-polar III-nitride buffer layers; and (b) doping the buffer layers so that a number of crystal defects in III-nitride device layers formed on or above the doped buffer layers is not higher than a number of crystal defects in III-nitride device layers formed on or above one or more undoped buffer layers. The doping can reduce or prevent formation of misfit dislocation lines and additional threading dislocations. The thickness and/or composition of the buffer layers can be such that the buffer layers have a thickness near or greater than their critical thickness for relaxation. In addition, one or more (AlInGaN) or III-nitride device layers can be formed on or above the buffer layers.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: July 8, 2014
    Assignee: The Regents of the University of California
    Inventors: Matthew T. Hardy, Po Shan Hsu, Steven P. DenBaars, James S. Speck, Shuji Nakamura
  • Patent number: 8772757
    Abstract: Light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 360 nm with wall plug efficiencies of at least than 4% are provided. Wall plug efficiencies may be at least 5% or at least 6%. Light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 345 nm with wall plug efficiencies of at least than 2% are also provided. Light emitting devices and methods of fabricating light emitting devices that emit at wavelengths less than 330 nm with wall plug efficiencies of at least than 0.4% are provided. Light emitting devices and methods of fabricating light emitting devices having a peak output wavelength of not greater than 360 nm and an output power of at least 5 mW, having a peak output wavelength of 345 nm or less and an output power of at least 3 mW and/or a peak output wavelength of 330 nm or less and an output power of at least 0.3 mW at a current density of less than about 0.35 ?A/?m2 are also provided.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: July 8, 2014
    Assignee: Cree, Inc.
    Inventors: David Todd Emerson, Michael John Bergmann, Amber Abare, Kevin Haberern
  • Publication number: 20140183443
    Abstract: Engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems and methods are disclosed herein. In several embodiments, for example, an engineered substrate can be manufactured by forming a shear strength enhancement material at a front surface of a donor substrate and implanting ions a depth into the donor substrate through the shear strength enhancement material. The ion implantation can form a doped portion in the donor substrate that defines an epitaxial formation structure. The method can further include transferring the epitaxial formation structure from the donor substrate to a front surface of a handle substrate. The shear strength enhancement material can be positioned between the epitaxial formation structure and the front surface of the handle substrate and bridge defects in the front surface of the handle substrate.
    Type: Application
    Filed: January 2, 2013
    Publication date: July 3, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Belford T. Coursey, F. Daniel Gealy, George E. Beck
  • Patent number: 8765505
    Abstract: The present invention relates to a multi-luminous element and a method for manufacturing the same. The present invention provides the multi-luminous element comprising: a buffer layer disposed on a substrate; a first type semiconductor layer disposed on the buffer layer; a first active layer which is disposed on the first type semiconductor layer and is patterned to expose a part of the first type semiconductor layer; a second active layer disposed on the first type semiconductor layer which is exposed by the first active layer; and a second type semiconductor layer disposed on the first active layer and the second active layer, the first and second active layers being repeatedly disposed in the horizontal direction, and the method for manufacturing the same.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: July 1, 2014
    Assignee: Korea Photonics Technology Institute
    Inventors: Seong Ran Jeon, Jae Bum Kim, Seung Jae Lee
  • Publication number: 20140175287
    Abstract: Methods and systems for electromagnetic detection are disclosed, including providing an optical antenna enhanced detector comprising: a micro photodetector, wherein the micro photodetector comprises: a substrate; a bottom contacting layer atop the substrate; one or more active regions atop the bottom contacting layer; and a top contacting layer atop the one or more active regions; and an optical antenna integrated with the micro photodetector, wherein the optical antenna is configured to concentrate incident electromagnetic waves onto the micro photodetector; and exposing the optical antenna enhanced detector to electromagnetic waves. Other embodiments are described and claimed.
    Type: Application
    Filed: December 23, 2013
    Publication date: June 26, 2014
    Inventor: Jarrod Vaillancourt
  • Patent number: 8759813
    Abstract: An Al0.95Ga0.05N:Mg (25 nm) single electron barrier can stop electrons having energy levels lower than the barrier height. Meanwhile, a 5-layer Al0.95Ga0.05N (4 nm)/Al0.77Ga0.23N (2 nm) MQB has quantum-mechanical effects so as to stop electrons having energy levels higher than the barrier height. Thus, electrons having energy levels higher than the barrier height can be blocked by making use of multiquantum MQB effects upon electrons. The present inventors found that the use of an MQB allows blocking of electrons having higher energy levels than those blocked using an SQB. In particular, for InAlGaN-based ultraviolet elements, AlGaN having the composition similar to that of AlN is used; however, it is difficult to realize a barrier having the barrier height exceeding that of AlN. Therefore, MQB effects are very important.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: June 24, 2014
    Assignee: RIKEN
    Inventor: Hideki Hirayama
  • Patent number: 8759812
    Abstract: According to an embodiment, a semiconductor light emitting device is configured to emit light by energy relaxation of an electron between subbands of a plurality of quantum wells. The device includes an active layer and at least a pair of cladding layers. The active layer is provided in a stripe shape extending in a direction parallel to an emission direction of the light, and includes the plurality of quantum wells; and the active layer emits the light with a wavelength of 10 ?m or more. Each of the cladding layers is provided both on and under the active layer respectively and have a lower refractive index than the active layer. At least one portion of the cladding layers contains a material having a different lattice constant from the active layer and has a lower optical absorption at a wavelength of the light than the other portion.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeyuki Takagi, Hidehiko Yabuhara
  • Patent number: 8759815
    Abstract: The disclosure relates to a nitride based semiconductor light emitting device with improved luminescence efficiency by increasing a recombination rate of electrons and holes contributing to luminescence, which results from matching the spatial distribution of electron and hole wave functions. The nitride based semiconductor light emitting device according to the present invention includes an n-type nitride layer, an active layer formed on the n-type nitride layer, and a p-type nitride layer formed on the active layer. At this stage, a strain control layer, and the at least one layer has a larger energy bandgap than a quantum well layer in the active layer. The strain control layer is disposed in an area where the quantum well layer of the active layer is formed. Moreover, an energy bandgap of the strain control layer is less than that of quantum barrier of the active layer.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: June 24, 2014
    Assignee: Korea Photonics Technology Institute
    Inventors: Seong Ran Jeon, Young Ho Song, Jae Bum Kim, Young Woo Kim, Woo Young Cheon, Jin Hong Kim
  • Patent number: 8755240
    Abstract: An optical memory device and a method of recording/reproducing information by using the optical memory device. The optical memory device includes a substrate; a first barrier layer formed on the substrate; a quantum well layer; a second barrier layer; a quantum dot layer; and a third barrier layer. The quantum well layer has an energy band gap which is wider than that of the quantum dot layer, and the second barrier layer has an energy band gap which is wider than that of the quantum well layer, so that electrons in excitons which are generated in the quantum dot layer by light of a certain wavelength are captured by the quantum well layer to record information, and then, recorded information may be erased or reproduced by irradiating light of a certain wavelength to the optical memory device.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Cheol Bae, Joo-Ho Kim, Jin-Kyung Lee
  • Patent number: 8749054
    Abstract: A monolithic power switch provides a semiconductor layer, a three dimensional FET formed in the semiconductor layer to modulate currents through the semiconductor layer, and a toroidal inductor with a ceramic magnetic core formed on the semiconductor layer around the FET and having a first winding connected to the FET.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: June 10, 2014
    Inventor: L. Pierre de Rochemont
  • Patent number: 8748868
    Abstract: For a nitride semiconductor light emitting device, a c-axis vector of hexagonal GaN of a support substrate is inclined to an X-axis direction with respect to a normal axis Nx normal to a primary surface. In a semiconductor region an active layer, a first gallium nitride-based semiconductor layer, an electron block layer, and a second gallium nitride-based semiconductor layer are arranged along the normal axis on the primary surface of the support substrate. A p-type cladding layer is comprised of AlGaN, and the electron block layer is comprised of AlGaN. The electron block layer is subject to tensile strain in the X-axis direction. The first gallium nitride-based semiconductor layer is subject to compressive strain in the X-axis direction. The misfit dislocation density at an interface is smaller than that at an interface. A barrier to electrons at the interface is raised by piezoelectric polarization.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: June 10, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Kyono, Yohei Enya, Katsushi Akita, Masaki Ueno, Yusuke Yoshizumi, Takamichi Sumitomo
  • Patent number: 8748865
    Abstract: Disclosed are a light emitting device, a method of manufacturing the light emitting device, a light emitting device package and a lighting system. The light emitting device includes a first conductive semiconductor layer; an active layer including a quantum well and a quantum barrier and disposed on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer. The active layer includes a first quantum well adjacent to the second conductive semiconductor layer, a second quantum well adjacent to the first quantum well, and a first quantum barrier between the first quantum well and the second quantum well. A recombination rate of electron-hole in the second quantum well is higher than the recombination rate of the electron-hole in the first quantum well, and the first quantum well has an energy level higher than the energy level of the second quantum well.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: June 10, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Jong Hak Won, Jong Ho Na, Jae In Yoon, Hoon ki Hong, Se Hwan Sim
  • Publication number: 20140152377
    Abstract: Disclosed herein are nanoscale devices comprising one or more ferroelectric nanoshells characterized as having an extreme curvature in at least one spatial dimension. Also disclosed are ferroelectric field effect transistors and metal ferroelectric metal capacitors comprising one or more ferroelectric nanoshells. Methods for controlling spontaneous ferroelectric polarization in nanoshell devices are also disclosed.
    Type: Application
    Filed: February 10, 2014
    Publication date: June 5, 2014
    Applicant: Drexel University
    Inventors: Jonathan E. Spanier, Stephen S. Nonnenmann, Oren David Leaffer
  • Patent number: 8735867
    Abstract: There are disclosed a group III nitride nanorod light emitting device and a method of manufacturing thereof. The group III nitride nanorod light emitting device includes a substrate, an insulating film formed on the substrate, and including a plurality of openings exposing parts of the substrate and having different diameters, and first conductive group III nitride nanorods having different diameters, respectively formed in the plurality of openings, wherein each of the first conductive group III nitride nanorods has an active layer and a second conductive semiconductor layer sequentially formed on a surface thereof.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: May 27, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han Kyu Seong, Hun Jae Chung, Jung Ja Yang, Cheol Soo Sone
  • Patent number: 8735925
    Abstract: Certain embodiments provide a semiconductor light emitting device including: a first metal layer; a stack film including a p-type nitride semiconductor layer, an active layer, and an n-type nitride semiconductor layer; an n-electrode; a second metal layer; and a protection film protecting an outer circumferential region of the upper face of the n-type nitride semiconductor layer, side faces of the stack film, a region of an upper face of the second metal layer other than a region in contact with the p-type nitride semiconductor layer, and a region of an upper face of the first metal layer other than a region in contact with the second metal layer. Concavities and convexities are formed in a region of the upper face of the n-type nitride semiconductor layer, the region being outside the region in which the n-electrode is provided and being outside the regions covered with the protection film.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kotaro Zaima, Toru Gotoda, Toshiyuki Oka, Shinya Nunoue
  • Patent number: 8735193
    Abstract: A light-emitting diode includes a substrate, a lower cladding layer, an active layer having a quantum well of a thirty percent concentration of indium on the lower cladding layer, and an upper cladding layer. A method of manufacturing light-emitting diodes includes forming a lower cladding layer on a substrate, forming an active layer on the lower cladding layer such that the active layer has a quantum well of thirty percent indium, forming an upper cladding layer on the active layer, and forming a metal cap on the upper cladding layer.
    Type: Grant
    Filed: January 6, 2012
    Date of Patent: May 27, 2014
    Assignee: Phoseon Technology, Inc.
    Inventor: Jules Braddell
  • Patent number: 8735868
    Abstract: A semiconductor optical modulator includes a first n-type semiconductor region, a first p-type semiconductor region, an i-type semiconductor region, a second p-type semiconductor region, and a second n-type semiconductor region that constitute a stacked layer structure. The stacked layer structure includes a first cladding layer, a second cladding layer, and a core layer disposed between the first and second cladding layer. The first n-type semiconductor region and the first p-type semiconductor region form a first p-n junction disposed in an intermediate region between the first and second cladding layer. The second p-type semiconductor region and the second n-type semiconductor region form a second p-n junction disposed in the intermediate region or the second cladding layer. The intermediate region, the first n-type semiconductor region, and the second n-type semiconductor region include the core layer, the first cladding layer, and part or all of the second cladding layer, respectively.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 27, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Naoya Kono
  • Patent number: 8729559
    Abstract: A relaxed epitaxial AlxInyGa(1-x-y)N layer on a substrate having a semipolar surface orientation includes a plurality of misfit dislocations in portions of the thickness of the epitaxial layer to reduce bi-axial strain to a relaxed state.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: May 20, 2014
    Assignee: Soraa, Inc.
    Inventors: Mike Krames, Mark D'Evelyn, Rajeev Pakalapati, Alex Alexander, Derrick Kamber
  • Patent number: 8728841
    Abstract: A nitride semiconductor light emitting device, and a method of manufacturing the same are disclosed. The nitride semiconductor light emitting device includes a substrate, an n-type nitride semiconductor layer disposed on the substrate and including a plurality of V-shaped pits in a top surface thereof, an active layer disposed on the n-type nitride semiconductor layer and including depressions conforming to the shape of the plurality of V-shaped pits, and a p-type nitride semiconductor layer disposed on the active layer and including a plurality of protrusions on a top surface thereof. Since the plurality of V-shaped pits are formed in the top surface of the n-type nitride semiconductor layer, the protrusions can be formed on the p-type nitride semiconductor layer as an in-situ process. Accordingly, the resistance to ESD, and light extraction efficiency are enhanced.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: May 20, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong Tak Oh, Yong Chun Kim
  • Patent number: 8729525
    Abstract: The present application relates to an opto-electronic device. The opto-electronic device includes an n-cladding layer, a p-cladding layer and a multi-quantum well structure. The multi-quantum well structure is located between the p-cladding layer and the n-cladding layer, and includes a plurality of barrier layers, a plurality of well layers and a barrier tuning layer. The barrier tuning layer is made by doping the barrier layer adjacent to the p-cladding layer with an impurity therein for changing an energy barrier thereof to improve the light extraction efficiency of the opto-electronic device.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: May 20, 2014
    Assignee: Epistar Corporation
    Inventors: Jui-Yi Chu, Cheng-Ta Kuo, Yu-Pin Hsu, Chun-Kai Wang, Hsin-Hsien Wu, Yi-Chieh Lin
  • Patent number: 8729562
    Abstract: There are provided a high current semiconductor device that has low on-resistance, high mobility, and good pinch-off characteristics and in which a kink phenomenon is not easily caused even if a drain voltage is increased, and a method for producing the semiconductor device. The semiconductor device of the present invention includes a GaN-based layered body 15 having an opening 28, a regrown layer 27 including a channel, a gate electrode G, a source electrode S, and a drain electrode D. The regrown layer 27 includes an electron transit layer 22 and an electron supply layer 26. The GaN-based layered body includes a p-type GaN layer 6 whose end surface is covered by the regrown layer in the opening, and a p-side electrode 11 that is in ohmic contact with the p-type GaN layer is disposed.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: May 20, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masaya Okada, Makoto Kiyama
  • Patent number: 8723159
    Abstract: A method for reducing dislocations or other defects in a light emitting device, such as light emitting diode (LED), by in-situ introducing nanoparticles into at least one of a defect-controlling layer, an n-type layer, a p-type layer, and a quantum well of the light emitting device. A light emitting device is provided, and nanoparticles are dispensed in-situ in at least one of a defect-controlling layer, an n-type layer, a p-type layer, and a quantum well of the light emitting device.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: May 13, 2014
    Assignee: InvenLux Corporation
    Inventors: Jianping Zhang, Hongmei Wang, Chunhui Yan
  • Patent number: 8723160
    Abstract: A light emitting diode (LED) die includes a first-type semiconductor layer, a multiple quantum well (MQW) layer and a second-type semiconductor layer. The light emitting diode (LED) die also includes a peripheral electrode on the first-type semiconductor layer located proximate to an outer periphery of the first-type semiconductor layer configured to spread current across the first-type semiconductor layer. A method for fabricating the light emitting diode (LED) die includes the step of forming an electrode on the outer periphery of the first-type semiconductor layer at least partially enclosing and spaced from the multiple quantum well (MQW) layer configured to spread current across the first-type semiconductor layer.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: May 13, 2014
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventors: Chen-Fu Chu, Feng-Hsu Fan, Hao-Chun Cheng, Trung Tri Doan
  • Patent number: 8716693
    Abstract: A light emitting device, a method of manufacturing the same, a light emitting device package, and a lighting system are disclosed. The light emitting device may include a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer interposed between the first and second conductive semiconductor layers. The first conductive semiconductor layer, the active layer, and the second conductive semiconductor layer may include Al. The second conductive semiconductor layer may have Al content higher than Al content of the first conductive semiconductor layer. The first conductive semiconductor layer may have Al content higher than Al content of the active layer.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: May 6, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyo Kun Son
  • Publication number: 20140116502
    Abstract: A quantum nanodot 3 is formed of a semiconductor and has an outer diameter in two-dimensional directions which is not more than twice a bore radius of an exciton in the semiconductor. A two-dimensional quantum nanodot array 1 has a structure that the quantum nanodots 3 are two-dimensionally and uniformly arranged with a spacing between the quantum nanodots 3 being 1 nm or more. The two-dimensional nanodot array 1 may include an intermediate layer 6 which is made of a semiconductor or an insulator and is filled between the quantum nanodot arrays 10. Since the quantum nanodots have high orientation and high density, a high quantum confinement effect is attained. Therefore, the quantum nanodot 3 made of Si produces direct transition type luminescence. It is possible to control an optical property and a transport property of the two-dimensional quantum nanodot array 10.
    Type: Application
    Filed: June 13, 2012
    Publication date: May 1, 2014
    Applicant: TOHOKU UNIVERSITY
    Inventor: Seiji Samukawa
  • Publication number: 20140117311
    Abstract: Semiconductor structures having a nanocrystalline core and nanocrystalline shell pairing compositional transition layers are described. In an example, a semiconductor structure includes a nanocrystalline core composed of a first semiconductor material. A nanocrystalline shell composed of a second semiconductor material surrounds the nanocrystalline core. A compositional transition layer is disposed between, and in contact with, the nanocrystalline core and nanocrystalline shell and has a composition intermediate to the first and second semiconductor materials. In another example, a semiconductor structure includes a nanocrystalline core composed of a first semiconductor material. A nanocrystalline shell composed of a second semiconductor material surrounds the nanocrystalline core. A nanocrystalline outer shell surrounds the nanocrystalline shell and is composed of a third semiconductor material.
    Type: Application
    Filed: October 29, 2012
    Publication date: May 1, 2014
    Inventor: Juanita N. Kurtin
  • Patent number: 8710488
    Abstract: A first exemplary device has a substrate, a nanowire and a doped epitaxial layer surrounding the nanowire. The nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength. The first exemplary device may further have an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire. A second exemplary device has a substrate, a nanowire and one or more photogates surrounding the nanowire. The nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength. The second exemplary device may have an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire. The one or more photogates comprise an epitaxial layer.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: April 29, 2014
    Assignee: Zena Technologies, Inc.
    Inventors: Young-June Yu, Munib Wober
  • Patent number: 8710489
    Abstract: To provide an epitaxial substrate for electronic devices, in which current flows in a lateral direction, which enables accurate measurement of the sheet resistance of HEMTs without contact, and to provide a method of efficiently producing the epitaxial substrate for electronic devices, the method characteristically includes the steps of forming a barrier layer against impurity diffusion on one surface of a high-resistance Si-single crystal substrate, forming a buffer as an insulating layer on the other surface of the high-resistance Si-single crystal substrate, producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate, and measuring resistance of the main laminate of the epitaxial substrate without contact.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: April 29, 2014
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Tetsuya Ikuta, Daisuke Hino, Ryo Sakamoto, Tomohiko Shibata
  • Patent number: 8710533
    Abstract: Light emitting systems are disclosed. More particularly light emitting systems that utilize wavelength converting semiconductor layer stacks, and preferred amounts of potential well types in such stacks to achieve more optimal performance are disclosed.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: April 29, 2014
    Assignee: 3M Innovative Properties Company
    Inventors: Michael A. Haase, Junqing Xie, Thomas J. Miller, Xiaoguang Sun
  • Publication number: 20140110668
    Abstract: An electronic device includes a substrate supporting mobile charge carriers, insulative features formed on the substrate surface to define first and second substrate areas on either side of the insulative features, the first and second substrate areas being connected by an elongate channel defined by the insulative features, the channel providing a charge carrier flow path in the substrate from the first area to the second area, the conductivity between the first and second substrate areas being dependent upon the potential difference between the areas. The mobile charge carriers can be within at least two modes in each of the three dimensions within the substrate. The substrate can be an organic material. The mobile charge carriers can have a mobility within the range 0.01 cm2/Vs to 100 cm2/Vs, and the electronic device may be an RF device. Methods for forming such devices are also described.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 24, 2014
    Applicant: PRAGMATIC PRINTING LIMITED
    Inventor: Aimin Song
  • Publication number: 20140110664
    Abstract: An III-nitride quantum well structure includes a GaN base, an InGaN layer and an InGaN covering layer. The GaN base includes a GaN buffering layer, a GaN post extending from the GaN buffering layer, and a GaN pyramid gradually expanding from the GaN post to form a mounting surface. The InGaN layer includes first and second coupling faces. The first coupling face is coupled with the mounting surface. The GaN covering layer includes first and second coupling faces. The first coupling face of the GaN covering layer is coupled with the second coupling face of the InGaN layer. A method for manufacturing the III-nitride quantum well structure and a light-emitting unit having a plurality of III-nitride quantum well structures are also proposed.
    Type: Application
    Filed: October 18, 2013
    Publication date: April 24, 2014
    Applicant: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: I-Kai LO, Yu-Chi HSU, Cheng-Hung SHIH, Wen-Yuan PANG, Ming-Chi CHOU
  • Patent number: 8704248
    Abstract: Implementations and techniques for coupled asymmetric quantum confinement structures are generally disclosed.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: April 22, 2014
    Assignee: University of Seoul Industry Cooperation Foundation
    Inventor: Doyeol Ahn
  • Patent number: 8704268
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer and a light emitting layer. The emitting layer is provided between the n-type layer and the p-type layer, and includes a plurality of barrier layers and a plurality of well layers, being alternately stacked. The p-side barrier layer being closest to the p-type layer among the plurality of barrier layer includes a first layer and a second layer, containing group III elements. An In composition ratio in the group III elements of the second layer is higher than an In composition ratio in the group III elements of the first layer. An average In composition ratio of the p-side layer is higher than an average In composition ratio of an n-side barrier layer that is closest to the n-type layer among the plurality of barrier layers.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Koichi Tachibana, Shinya Nunoue
  • Patent number: 8704209
    Abstract: An infrared photodetector comprising: a thin contact layer substantially transparent to infrared light; an absorption layer positioned such that light admitted through the substantially transparent thin contact area passes through the absorption layer; the absorption layer being configured to utilize resonance to increase absorption efficiency; at least one reflective side wall adjacent to the absorption layer being substantially non-parallel to the incident light operating to reflect light into the absorption layer for absorption of infrared radiation; and a top contact layer positioned adjacent to the active layer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: April 22, 2014
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Kwong-Kit Choi
  • Patent number: 8698163
    Abstract: A light emitting diode (LED) comprises an n-type Group III-V semiconductor layer, an active layer adjacent to the n-type Group III-V semiconductor layer, and a p-type Group III-V semiconductor layer adjacent to the active layer. The active layer includes one or more V-pits. A portion of the p-type Group III-V semiconductor layer is in the V-pits. A p-type dopant injection layer provided during the formation of the p-type Group III-V layer aids in providing a predetermined concentration, distribution and/or uniformity of the p-type dopant in the V-pits.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 15, 2014
    Assignee: Toshiba Techno Center Inc.
    Inventor: Steve Ting
  • Patent number: 8698125
    Abstract: Provided is a light emitting device, which includes a first conductive type semiconductor layer, an active layer, a roughness pattern, and a second conductive type semiconductor layer. The active layer is disposed on the first conductive type semiconductor layer. The roughness pattern is disposed on the active layer. The second conductive type semiconductor layer is disposed on the roughness pattern and the active layer, and includes a metal oxide.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: April 15, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hyo Kun Son
  • Patent number: 8698126
    Abstract: In the nitride semiconductor device of the present invention, an active layer 12 is sandwiched between a p-type nitride semiconductor layer 11 and an n-type nitride semiconductor layer 13. The active layer 12 has, at least, a barrier layer 2a having an n-type impurity, a well layer 1a made of a nitride semiconductor that includes In; and a barrier layer 2c that has a p-type impurity, or that has been grown without being doped. An appropriate injection of carriers into the active layer 12 becomes possible by arranging the barrier layer 2c nearest to the p-type layer side.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: April 15, 2014
    Assignee: Nichia Corporation
    Inventor: Tokuya Kozaki
  • Patent number: 8697461
    Abstract: There is provided a manufacturing method of an LED module including: forming an insulating film on a substrate; forming a first ground pad and a second ground pad separated from each other on the insulating film; forming a first division film that fills a space between the first and second ground pads, a second division film deposited on a surface of the first ground pad, and a third division film deposited on a surface of the second ground pad; forming a first partition layer of a predetermined height on each of the division films; sputtering seed metal to the substrate on which the first partition layer is formed; forming a second partition layer of a predetermined height on the first partition layer; forming a first mirror connected with the first ground pad and a second mirror connected with the second ground pad by performing a metal plating process to the substrate on which the second partition layer is formed; removing the first and second partition layers; connecting a zener diode to the first mirror
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: April 15, 2014
    Assignee: Daewon Innost Co., Ltd.
    Inventors: Won Sang Lee, Young Keun Kim