Abstract: An integrated circuit device is provided. The integrated circuit device includes: a capacitor including an electrode formed in a first area on a substrate; a through-silicon-via (TSV) landing pad formed in a second area on the substrate, the TSV landing pad including the same material as the electrode; a multi-layered interconnection structure formed on the capacitor and the TSV landing pad; and a TSV structure passing through the substrate, the TSV structure being connected to the multi-layered interconnection structure through the TSV landing pad.

Abstract: SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.

Abstract: A method for fabricating a semiconductor device includes preparing a substrate which includes a memory cell region and a peripheral circuit region; forming a buried word line in the substrate in the memory cell region; forming a planar gate structure over the substrate in the peripheral circuit region; forming a bit line structure over the substrate in the memory cell region; forming a first air spacers over a sidewalls of the planar gate structure; and forming a second air spacers over a sidewalls of the bit line structure.

Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.

Abstract: A technique relates to forming a semiconductor device. A field-effect transistor structure having a substrate, a fin structure patterned in the substrate, a gate stack structure, and an insulator layer is first provided. A non-capacitor region and a capacitor region are then formed on the field-effect transistor structure by masking portions of the field-effect transistor structure with a mask such that a non-capacitor region is masked and a capacitor region is exposed, and etching the insulator layer to further recess the fin structure and gate stack structure within the capacitor region such that a revealed height of the fins within the capacitor region is increased relative to the revealed height of the fins in the non-capacitor region. A high-k layer can be deposited over the recessed fins and gate stack structures and a gate metal can fill the recessed portions therein.

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

Abstract: A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode.

Abstract: In one embodiment, an integrated circuit includes an input-output circuit, first and second electrostatic discharge diode circuits, first and second power clamp circuits and first, second and third voltage rails. The input-output circuit includes an input node that is coupled to an input-output pad. The first electrostatic discharge diode circuit may be coupled between the first and third voltage rails whereas the second electrostatic discharge diode circuit may be coupled between the second and third voltage rails. In addition to that, the first voltage rail may also be coupled to the first power clamp circuit and the second voltage rail may also be coupled to the second power clamp circuit.

Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.

Abstract: A rear-surface-irradiation-type infrared sensor includes a substrate having a through hole passing through between an upper surface and a lower surface; an infrared absorption part on the substrate on a side of the upper surface separate from the substrate by the through hole; and a temperature sensor part detecting a change in a temperature of the infrared absorption part. The through hole includes a first through hole part having an opening on the upper surface and one or more second through hole parts having shapes different from the first through hole constituent part. The first through hole part and the second through hole part(s) communicate with each other. In a cross-sectional shape of the through hole on a plane perpendicular to the upper surface, an inside wall of the first through hole part is outside an inside wall of the of second through hole part(s).

Abstract: Provided is a semiconductor device and a method for fabricating the same. The semiconductor device includes an interlayer insulating layer formed on a semiconductor substrate, a metal contact plug penetrating the interlayer insulating layer, a cylindrical lower electrode formed on the metal contact plug and including a first metal and a trench, a supporter formed in the trench and including a second metal that is different from the first metal, a dielectric layer formed on the lower electrode and the supporter and an upper electrode formed on the dielectric layer.

Abstract: The semiconductor device according to the present invention includes a ferroelectric film and an electrode stacked on the ferroelectric film. The electrode has a multilayer structure of an electrode lower layer in contact with the ferroelectric film and an electrode upper layer stacked on the electrode lower layer. The electrode upper layer is made of a conductive material having an etching selection ratio with respect to the materials for the ferroelectric film and the electrode lower layer. The upper surface of the electrode upper layer is planarized.

Abstract: The present disclosure relates to a semiconductor structure including a plurality of connecting lines arranged on a plurality of vertical levels, the plurality of connecting lines including at least a first connecting line arranged in a first vertical level and a second connecting line arranged in a second vertical level, different from the first vertical level, and a breakdown prevention layer placed in at least part of the vertical space separating the first connecting line from the second connecting line.

Abstract: Sacrificial plugs for forming contacts in integrated circuits, as well as methods of forming connections in integrated circuit arrays are disclosed. Various pattern transfer and etching steps can be used to create densely-packed features and the connections between features. A sacrificial material can be patterned in a continuous zig-zag line pattern that crosses word lines. Planarization can create parallelogram-shaped blocks of material that can overlie active areas to form sacrificial plugs, which can be replaced with conductive material to form contacts.

Abstract: To enhance the write speed of a nonvolatile memory. A charge injection/emission part of a nonvolatile memory cell includes an active region having an upper face, a side wall, and a shoulder part connecting the upper face and the side wall, a conductor film covering the upper face and the shoulder part of the active region, and a capacitance insulating film provided between the conductor film and the active region. Furthermore, the active region has a protrusion part constituted of a first concave part with respect to the upper face and a second concave part with respect to the side wall, in the shoulder part.

Abstract: A method of manufacturing a semiconductor device includes forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating interlayer on the active pattern of the substrate and the isolation layer, removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess, forming a first contact in the first recess on a first region of the active pattern exposed by the first recess, removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess, and filling the enlarged first recess to form a first spacer that surrounds a sidewall of the first contact.

Abstract: According to this embodiment, a semiconductor device includes a semiconductor substrate, element formation regions that are formed in a line-and-space pattern in a surface layer portion of the semiconductor substrate to extend in a first direction, a coupling portion that is formed in the surface layer portion of the semiconductor substrate to couple the element formation regions adjacent to each other in a second direction intersecting the first direction, a source line that is disposed in an upper layer of the semiconductor substrate through an insulating film, a source line contact, having a circular shape or an elliptical shape, that is provided to electrically connect a source region pattern and the source lines by passing through the insulating film, when a region including the coupling portion and portions of the element formation regions coupled by the coupling portion is set to the source region pattern, and a bit line contact, having a circular shape or an elliptical shape, that is provided to elect

Abstract: Non-planar semiconductor devices having group III-V material active regions with multi-dielectric gate stacks are described. For example, a semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a three-dimensional group III-V material body with a channel region. A source and drain material region is disposed above the three-dimensional group III-V material body. A trench is disposed in the source and drain material region separating a source region from a drain region, and exposing at least a portion of the channel region. A gate stack is disposed in the trench and on the exposed portion of the channel region. The gate stack includes first and second dielectric layers and a gate electrode.

Abstract: A technique relates to forming a semiconductor device. A field-effect transistor structure having a substrate, a fin structure patterned in the substrate, a gate stack structure, and an insulator layer is first provided. A non-capacitor region and a capacitor region are then formed on the field-effect transistor structure by masking portions of the field-effect transistor structure with a mask such that a non-capacitor region is masked and a capacitor region is exposed, and etching the insulator layer to further recess the fin structure and gate stack structure within the capacitor region such that a revealed height of the fins within the capacitor region is increased relative to the revealed height of the fins in the non-capacitor region. A high-k layer can be deposited over the recessed fins and gate stack structures and a gate metal can fill the recessed portions therein.

Abstract: A static random-access memory (SRAM) memory cell includes a pair of cross-coupled inverters and a gating transistor coupled to a first node of a first inverter of the pair of cross-coupled inverters. A gate of the gating transistor is coupled to a first wordline. The gating transistor is configured to selectively couple a bitline to the first node of the first inverter responsive to a first wordline signal. The first inverter has a second node coupled to a second wordline. The first wordline and the second wordline are each independently controllable.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.

Abstract: A semiconductor device includes a substrate, a first source/drain (S/D), a second S/D, and a semiconductor sheet unit. The substrate extends in a substantially horizontal direction. The first S/D is formed on the substrate. The second S/D is disposed above the first S/D. The semiconductor sheet unit extends in a substantially vertical direction and interconnects the first S/D and the second S/D. A method for fabricating the semiconductor device is also disclosed.

Abstract: Non-volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different locations along a length of the electrode and may be spaced apart from adjacent diodes by a dielectric material. The electrode may electrically couple the diodes of the memory strings to one another and to another memory device, such as, a MOSFET device. Methods of forming the non-volatile memory devices as well as intermediate structures are also disclosed.

Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.

Abstract: An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

Abstract: A semiconductor process includes the steps of providing a semiconductor substrate with a logic region and a memory region, defining memory gates on the memory region, forming a conformal spacer layer on the memory gates and the semiconductor substrate, and performing an etch process on the conformal spacer layer, such that the conformal spacer layer on sidewalls of the memory gates transforms into spacers, and the conformal spacer layer between the memory gates transforms into a concave block covering the semiconductor substrate between the memory gates.

Abstract: A capacitor structure of capacitive touch panel including a first electrode layer, a first material layer, a second material layer and a second electrode layer is provided. The first material layer is disposed on the first electrode layer, and the material of the first material layer is selected from one of a semiconductor material and an insulating material. The second material layer is disposed on the first material layer, and the material of the second material layer is selected from another one of the semiconductor material and the insulating material. The second electrode layer is disposed on the second material layer.

Abstract: A semiconductor device has a first element region, a second element region, and a first isolation region in a thin film region and a third element region, a fourth element region, and a second isolation region in a thick film region. It is manufactured with step (a) of providing a substrate having a silicon layer formed via an insulating layer, step (b) of forming element isolation insulating films in the silicon layer in the first isolation region and the second isolation region of the substrate step (c) of forming a hard mask in the thin film region, step (d) of forming silicon films over the silicon layer exposed from the hard mask in the third element region and the fourth element region, and step (e) of forming element isolation insulating films between the silicon films in the third element region and the fourth element region.

Abstract: The memory device is provided to include a substrate, a plurality of stack structures, conductive pillars, charge storage layers, and third conductive layers. The stack structures are arranged along a first direction and extend along a second direction, wherein each stack structure includes a plurality of first conductive layers and a plurality of dielectric layers that are alternately stacked along a third direction. Each conductive pillar is located on the substrate between two adjacent stack structures. Each charge storage layer is disposed between the stack structures and the conductive pillars. Each third conductive layer extending along the first direction overlaps the stack structures in a plurality of overlapped regions and covers a portion of top parts of the stack structures and the conductive pillars. An air gap is formed along the third direction in each overlapped region where the stacked structures and the third conductive layers overlap.

Abstract: Methods of forming a hard mask capable of implementing an electrode having a high aspect ratio are provided. A molding layer may be formed on a substrate. A sacrificial layer may be formed on the molding layer. First mask patterns may be formed in parallel in the sacrificial layer. After the first mask patterns are formed, second mask patterns, which cross the first mask patterns and are in parallel, may be formed in the sacrificial layer. The first mask patterns and the second mask patterns may have materials more opaque than the sacrificial layer. Upper surfaces of the sacrificial layer, the first mask patterns and the second mask patterns may be exposed at the same horizontal level. The sacrificial layer may be removed. Openings, which pass through the molding layer, may be formed using the first mask patterns and the second mask patterns as etch masks. Electrodes may be formed in the openings.

Abstract: A method comprises implanting ions in a substrate to form a first active region and a second active region, depositing a first dielectric layer over the substrate, forming a first via and a second via in the first dielectric layer, wherein the first via is over the first active region and the second via is over the second active region, depositing a second dielectric layer over the first dielectric layer, forming a third via and a fourth via in the second dielectric layer, wherein the third via is over the first via and the fourth via is over the second via and forming a connector in a metallization layer over the second dielectric layer, wherein the connector is electrically connected to the third via and the fourth via.

Abstract: A semiconductor device includes a semiconductor layer, gate electrodes, an insulating film, source electrodes, and drain electrodes which are provided on the semiconductor layer. Each of the source electrodes and the drain electrodes are spaced in the insulating film from a corresponding gate electrode, such that one end thereof is in contact with the semiconductor layer and the other end thereof is exposed. Further, the semiconductor device includes first field plate electrodes, each of which is provided on a corresponding gate electrode and the insulating film, and second field plate electrodes, each of which is provided on the insulating film between a corresponding first field plate electrode and a corresponding drain electrode. Furthermore, the thickness of the insulating film between each first field plate electrode and the semiconductor layer is smaller than the thickness of the insulating film between each second field plate electrode and the semiconductor layer.

Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a silicon carbide/silicon nitride nanolaminate stack. The semiconductor layer of the selector element can include a silicon carbon nitride/silicon nitride nanolaminate stack. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or a combination thereof.

Abstract: A semiconductor device having a capacitor which includes a first electrode electrically coupled to a transistor and a second electrode separate from the first electrode and covered with an interlayer insulating film, in which a plurality of coupling holes are formed in the interlayer insulating film and are in contact with the second electrode at the lower ends; and, when the capacitance of the second electrode is represented by C [nF] and the total area of the lower ends of the coupling holes is represented by A [?m2], the following expression (1) is satisfied. C/A?1.98 [nF/?m2]??(1) The elution of the second electrode constituting the capacitor at the lower ends of the coupling holes is suppressed.

Abstract: A nano-piezoelectric generator includes a first electrode and a second electrode, at least one nano-piezoelectric unit, formed of a semiconductor piezoelectric material having a nano-structure, disposed between the first and the second electrodes, and an interlayer, formed of an insulating material, disposed between the first electrode and the at least one nano-piezoelectric unit.

Abstract: Disclosed herein is a device that includes: a substrate having a gate trench; a gate electrode embedded in the gate trench with an intervention of a gate insulation film; and an embedded insulation film embedded in the gate trench. The substrate includes a first impurity diffusion region in contact with the embedded insulation film and a second impurity diffusion region in contact with the gate insulation film. The gate trench including a first trench portion extending in a first direction and second and third trench portions branching from the first trench portion and extending in a second direction that crosses the first direction. The gate electrode including first, second and third electrode portions embedded in the first, second and third trench portions of the gate trench, respectively. The first impurity diffusion region being sandwiched between the second and third electrode portions.

Abstract: A pixel includes a capacitor coupled to a transistor, a first insulating layer over a semiconductor layer of the transistor, a second insulating layer over the first insulating layer, and a blocking layer between the first insulating layer and the second insulating layer. The first plate of the capacitor is on the first insulating layer and a second plate of the capacitor on the second insulating layer. The blocking layer may be made of a natural oxide layer and the first insulating layer may be made of a material different from the blocking layer.

Abstract: An apparatus includes first and second electrodes separated by an insulative material (such as a piezoelectric material). The apparatus also includes a protective layer over the first and second electrodes. The protective layer has a first opening that exposes a portion of the first electrode and a second opening that exposes a portion of the second electrode. The apparatus further includes a first electrical contact at least partially within the first opening and electrically coupled to the first electrode. In addition, the apparatus includes a second electrical contact at least partially within the second opening and electrically coupled to the second electrode. Each of the first and second electrical contacts includes a stack of metal layers. The stack of metal layers includes a titanium nitride layer, a titanium layer over the titanium nitride layer, and an aluminum copper layer over the titanium nitride layer and the titanium layer.

Abstract: This electronic component is provided with an inorganic substrate, a conductor film formed on a surface of the substrate, and bonding wires bonded to a part of said conductor film, and wire bonding sections are formed on at least a part of the electronic component. The part of the conductor film at least forming the aforementioned wire bonding sections contains an Ag-based metal formed of Ag or an alloy having Ag as the main constituent and a metal oxide which coats said Ag-based metal and which has, as a constituent element, any of the elements selected from the group consisting of Al, Zr, Ti, Y, Ca, Mg, and Zn. The coating quantity of the metal oxide is a quantity corresponding to 0.02 to 0.1 parts by mass relative to 100 parts by mass of the aforementioned Ag-based metal.

Abstract: A capacitor comprising: a metal plate a doped semiconductor plate; and a dielectric sandwiched therebetween.

Abstract: A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.

Abstract: Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a storage electrode having a cylinder shape, a dielectric film formed on the storage electrode, and a plate electrode formed on the dielectric film, wherein the plate electrode includes a first semiconductor compound layer and a second semiconductor compound layer sequentially stacked one on the other, and the first semiconductor compound layer has a crystallinity different from that of the second semiconductor compound layer.

Abstract: A vertical transistor device includes a line of active area adjacent a line of dielectric isolation. A buried data/sense line obliquely angles relative to the line of active area and the line of dielectric isolation. A pair of gate lines is outward of the buried data/sense line and obliquely angle relative to the line of active area and the line of dielectric isolation. A vertical transistor channel region is within the active area between the pair of gate lines. An outer source/drain region is in the active area above the channel region and an inner source/drain region is in the active area below the channel region. The inner source/drain region is electrically coupled to the buried data/sense line. Other devices and structures are contemplated, as are methods of forming a plurality of vertical transistor devices.

Abstract: According to example embodiments of inventive concepts, method of forming a semiconductor memory devices includes sequentially forming a first mold layer, a first support layer, a second mold layer, and a second support layer on a substrate, forming lower electrodes penetrating the second support layer, the second mold layer, the first support layer, and the first mold layer on the substrate, patterning the second support layer to form a second support pattern including an opening, removing the second mold layer to expose portions of sidewalls of the lower electrodes, and etching the exposed sidewalls of the lower electrodes.

Abstract: Radiation hardened NMOS devices suitable for application in NMOS, CMOS, or BiCMOS integrated circuits, and methods for fabricating them. A device includes a p-type silicon substrate, a field oxide surrounding a moat region on the substrate tapering through a Bird's Beak region to a gate oxide within the moat region, a heavily-doped p-type guard region underlying at least a portion of the Bird's Beak region and terminating at the inner edge of the Bird's Beak region, a gate included in the moat region, and n-type source and drain regions spaced by a gap from the inner edge of the Bird's Beak and guard regions. A variation of minor alterations to the conventional moat and n-type source/drain masks. The resulting devices have improved radiation tolerance while having a high breakdown voltage and minimal impact on circuit density.

Abstract: Non-volatile storage devices and methods for fabricating non-volatile storage device are described. Sidewalls of the memory cells and their associated word line may be covered with silicon oxide. Silicon nitride covers the silicon oxide adjacent to the word lines, which may provide protection for the word lines during fabrication. However, silicon nitride can trap charges, which can degrade operation if the trapped charges are near a charge trapping region of a memory cell. Thus, the silicon nitride does not cover the silicon oxide adjacent to charge storage regions of the memory cells, which can improve device operation. For example, memory cell current may be increased. Techniques for forming such a device are also disclosed. One aspect includes a method that uses a sacrificial material to control formation of a silicon nitride layer when forming a memory device.

Abstract: A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate, forming a plurality of gate regions on portions of the fins, wherein the gate regions are spaced apart from each other, forming spacers on each respective gate region, epitaxially growing a first epitaxy region on each of the fins, stopping growth of the first epitaxy regions prior to merging of the first epitaxy regions between adjacent fins, forming a dielectric layer on the substrate including the fins and first epitaxy regions, removing the dielectric layer and first epitaxy regions from the fins at one or more portions between adjacent gate regions to form one or more contact area trenches, and epitaxially growing a second epitaxy region on each of the fins in the one or more contact area trenches, wherein the second epitaxy regions on adjacent fins merge with each other.

Abstract: Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone.

Abstract: The present disclosure involves a method. The method includes providing a substrate including a top surface. The method also includes forming a gate over the top surface of the substrate. The formed gate has a first height measured from the top surface of the substrate. The method also includes etching the gate to reduce the gate to a second height. This second height is substantially less than the first height. The present disclosure also involves a semiconductor device. The semiconductor device includes a substrate. The substrate includes a top surface. The semiconductor device also includes a first gate formed over the top surface of the substrate. The first gate has a first height. The semiconductor device also includes a second gate formed over the top surface of the substrate. The second gate has a second height. The first height is substantially less than the second height.

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a local silicon-on-insulator (SOI) substrate in which a portion of a line-shaped active region is connected to a semiconductor substrate, and a remaining portion thereof is insulated from the semiconductor substrate, gate structures formed in a line shape to be substantially perpendicular to the active region on the active region insulated from the semiconductor substrate, and to surround a side and an upper surface of the active region, and having a stacking structure of a gate insulating layer, a liner conductive layer, a gate conductive layer, and a hard mask layer, a source region formed in the active region connected to the semiconductor substrate, and a drain region formed in the active region insulated from the semiconductor substrate between the gate structures.