Abstract: A method and apparatus for forming an interconnect on a substrate is provided. A protective layer is formed on the substrate and in a via formed on the substrate wherein the protective layer is resistant to a halogen containing material. A barrier layer is formed on top of the protective layer. The barrier layer comprises a halogen containing material. A metal layer is deposited over the barrier layer. In another embodiment, the protective layer is selectively deposited in the via.

Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad, and a conductive interconnect can extend from the conductive structure.

Abstract: Various embodiments of mechanisms for forming through a three-dimensional integrated circuit (3DIC) structure are provided. The 3DIC structure includes an interposer bonded to a die and a substrate. The interposer has a conductive structure with through silicon vias (TSVs) connected to a patterned metal pad and a conductive structure on opposite ends of the TSVs. The pattern metal pad is embedded with dielectric structures to reduce dishing effect and has regions over TSVs that are free of the dielectric structures. The conductive structure has 2 or more TSVs. By using a patterned metal pad and 2 or more TSVs, the reliability and yield of the conductive structure and the 3DIC structure are improved.

Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

Abstract: An interposer fabricating process includes the following steps. A substrate, an oxide layer, and a dielectric layer are stacked from bottom to top, and an interconnect in the dielectric layer is provided, wherein the dielectric layer includes a stop layer contacting the oxide layer and the interconnect includes a metal structure having a barrier layer protruding from the stop layer. The substrate and the oxide layer are removed until exposing the stop layer and the barrier layer by a removing selectivity between the oxide layer and the stop layer. A wafer packaging structure formed by said interposer is also provided.

Abstract: Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).

Abstract: A shift register circuit has a plurality of unit circuits that are cascade-connected to one another and that output received pulse signals as output signals in accordance with a clock signal, the shift register circuit sequentially outputting the output signals from the plurality of respective unit circuits. The output circuits each include a double-gate transistor having first gate electrode that controls conductivity between the drain electrode and the source electrode, and a second gate electrode formed through an insulating layer and disposed to face the first gate electrode across a semiconductor layer between the drain electrode and the source electrode. The shift register circuit applies a prescribed voltage to the second gate electrode in accordance with a voltage applied to the first gate electrode.

Abstract: A method of fabricating an integrated circuit includes depositing a cap layer on a substrate; depositing a dielectric layer on the cap layer; and forming a trench in the dielectric layer. The method further includes depositing a tantalum nitride (TaN) layer on a sidewall of the trench such that the TaN layer has a greater concentration of nitrogen than tantalum. The method further includes depositing a tantalum (Ta) layer on the TaN layer using physical vapor deposition (PVD); and depositing a metal layer over the Ta layer.

Abstract: A semiconductor device includes a first stacked portion above a substrate, the first stacked portion comprising a first nitride semiconductor layer containing aluminum and a second nitride semiconductor layer containing carbon, a third nitride semiconductor layer on the first stacked portion, the third nitride semiconductor layer containing carbon and having a greater thickness than each of the first and second nitride semiconductor layers, the third nitride semiconductor layer having a lower carbon concentration than the second nitride semiconductor layer, a second stacked portion on the third nitride semiconductor, the second stacked portion comprising a fourth nitride semiconductor layer containing aluminum and a fifth nitride semiconductor layer containing carbon, a sixth nitride semiconductor layer on the second stacked portion, a seventh nitride semiconductor layer on the sixth nitride semiconductor layer and containing aluminum, and a first electrode on the seventh nitride layer.

Abstract: A semiconductor device includes a semiconductor layer and a first insulating film provided on the semiconductor layer. The first insulating film has a surface opposite to the semiconductor layer, the surface including a first portion, a second portion and a third portion between the first portion and the second portion. The device includes a first interconnection provided on a first portion and a second interconnection provided on the second portion. The first interconnection and the second interconnection extend in a first direction. The device further includes a conductor and a nitride layer. The conductor extends through the first insulating film in a second direction from each of the first interconnection and the second interconnection toward the semiconductor layer, and the conductor electrically connects the first interconnection to the semiconductor layer. The nitrided layer is provided at least on the third surface.

Abstract: A semiconductor device includes a first interlayer dielectric layer disposed over a substrate, metal wirings, a second interlayer dielectric layer disposed over the first interlayer dielectric layer and the metal wirings, a first air gap and a second air gap. The metal wirings are embedded in the first interlayer dielectric layer, and arranged with a first space or a second space between the metal wirings. The second space has a greater length than the first space. The first air gap is formed by the second interlayer dielectric layer and formed in a first area sandwiched by adjacent two metal wirings arranged with the first space. The second air gap is formed by the second interlayer dielectric layer and formed in a second area sandwiched by adjacent two metal wirings arranged with the second space therebetween. No adjacent two metal wirings are arranged with a space smaller than the first space.

Abstract: A testing system for carrying out electrical testing of at least one first through via forms an insulated via structure extending only part way through a substrate of a first body of semiconductor material. The testing system has a first electrical test circuit integrated in the first body and electrically coupled to the insulated via structure. The first electrical test circuit enables detection of at least one electrical parameter of the insulated via structure.

Abstract: A semiconductor device includes first conductive patterns adjacent to each other and isolated by a trench including first and second trenches, a second conductive pattern formed in the first trench, and an insulating pattern partially filling the second trench under the second conductive pattern and formed between the first conductive patterns and the second conductive pattern.

Abstract: A memory device includes a pickup area extending along a first direction. The pickup area includes at least one N-pickup structure, distributing along an N-pickup line extending at the first direction. At least one P-pickup structure distributes by alternating with the N-pickup structure at the first direction and interleaves with the N-pickup structure at a second direction. The second direction is perpendicular to the first direction. Dummy pickup structure distributes along the first direction, opposite to the P-pickup structure with respect to the N-pickup line. Further, a cell area is beside the pickup area. The SRAM cells in the cell area form cell rows extending along the second direction. Each SRAM cell covers one N-type well region along the second direction and two P-type well regions along the second direction to sandwich the N-type well region. The N-pickup/P-pickup structures respectively provide first/second substrate voltage to the N-type/P-type well regions.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.

Abstract: Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; a variable resistance element formed over the substrate; a top electrode formed over the variable resistance element; a barrier layer formed over the top electrode and including a groove; an interlayer dielectric layer formed over the substrate to have a layer structure in which the variable resistance element, the top electrode and the barrier layer are formed in the interlayer dielectric layer; and a metal wiring including a portion formed in the groove of the barrier layer.

Abstract: A method for forming a protecting layer includes determining an expected concentration of metal ions in a dielectric layer. The method also includes determining a thickness of the protecting layer based on the expected concentration of metal ions. The method also includes forming the protecting layer at the determined thickness and in contact with the dielectric layer. The protecting layer can include at least one of silicon doped nitride, carbon nitride, silicon nitride, or silicon carbon.

Abstract: A manufacturing method of an interposed substrate is provided. A photoresist layer is formed on a metal carrier. The photoresist layer has plural of openings exposing a portion of the metal carrier. Plural of metal passivation pads and plural of conductive pillars are formed in the openings. The metal passivation pads cover a portion of the metal carrier exposed by openings. The conductive pillars are respectively stacked on the metal passivation pads. The photoresist layer is removed to expose another portion of the metal carrier. An insulating material layer is formed on the metal cattier. The insulating material layer covers the another portion of the metal carrier and encapsulates the conductive pillars and the metal passivation pads. An upper surface of the insulating material layer and a top surface of each conductive pillar are coplanar. The metal carrier is removed to expose a lower surface of the insulating material layer.

Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing is formed in a second metal layer and directly under the metal pad, wherein an oxide layer is positioned between the first metal layer and the second metal layer.

Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.

Abstract: Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of die bond pads on a surface of the die. The connecting structure includes a plurality of via and groove combinations. Conductive material is formed in the via and groove combinations to provide connection between the die bond pads and bond pads on the support. Other embodiments are described and claimed.

Abstract: An optoelectronic component includes a carrier having an upper side which includes a first subarea and a second subarea, wherein the first subarea and the second subarea have different optical properties, and a method of producing an optoelectronic component includes providing a carrier having an upper side which includes a first subarea and a second subarea, and changing an optical property in the first subarea or in the second subarea.

Abstract: A semiconductor device may include a metal pad and a first specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device and is directly contacting the first metal layer. The first specific metal layer routing is formed on a second metal layer of the semiconductor device and under the metal pad. In addition, the semiconductor device may include at least one via plug for connecting the first specific metal layer routing to at least one metal region in the first metal layer, where the aforementioned at least one via plug is formed directly under the metal pad.

Abstract: In a method of fabricating a semiconductor device, an opening is formed inside a dielectric layer above a semiconductor substrate. The opening has a wall. At least one diffusion barrier material is then formed over the wall of the opening by at least two alternating steps, which are selected from the group consisting of a process of physical vapor deposition (PVD) and a process of atomic layer deposition (ALD). A liner layer is formed over the at least one diffusion barrier material.

Abstract: A semiconductor device according to an embodiment includes a first metal layer, a second metal layer, an n-type first SiC region provided between the first metal layer and the second metal layer and having an n-type impurity concentration of 1×1018 cm?3 or less, and a conductive layer provided between the first SiC region and the first metal layer and containing titanium (Ti), oxygen (O), and at least one element selected from the group consisting of vanadium (V), niobium (Nb), and tantalum (Ta).

Abstract: In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.

Abstract: According to one embodiment, a semiconductor device includes an underlayer formed on a substrate, a catalyst layer disposed on the underlayer and extending in an interconnect length direction. The device further includes an upper graphene layer formed on an upper face of the catalyst layer, and side graphene layers provided on two respective side faces of the catalyst layer, the two side faces extending in the interconnect length direction.

Abstract: Resistive random access memory elements, such as phase change memory elements, may be defined using a plurality of parallel conductive lines over a stack of layers, at least one of which includes a resistive switching material. The stack may be etched using the conductive lines as a mask. As a result, memory elements may be self-aligned to the conductive lines.

Abstract: A method for manufacturing a liquid crystal display includes: forming a first passivation layer and an organic layer, forming an edge of an inclined portion of the organic layer by partially removing the organic layer at a location where a first drain contact hole that exposes a drain electrode of a thin film transistor is formed, forming a second passivation layer including a third drain contact hole exposing the drain electrode, a first electrode including a second drain contact hole exposing the drain electrode, and the first drain contact hole through an etching process using one etching mask, and forming a second electrode on the second passivation layer. The first drain contact hole, the second drain contact hole, and the third drain contact hole overlap with each other, and a size of the second drain contact hole is greater than a size of the third drain contact hole.

Abstract: A method for treating a chip packaging structure includes providing a chip packaging structure having at least a first electrical connect structure and a second electrical connect structure, and an insulation layer exposing portions of the first electrical connect structure and the second electrical connect structure; selecting a plasma gas based on materials of the first electrical connect structure and the second electrical connect structure and a type of process forming the first electrical connect structure and the second electrical connect structure, wherein metal cations are left on the insulation layer; performing a plasma treatment process using the selected plasma gas on the first electrical connect structure, the second electrical connect structure and the insulation layer, causing reaction of the metal cations to substantially convert the metal cations into electrically neutral materials; and removing the reacted metal cations from the insulation layer.

Abstract: A semiconductor device of an embodiment includes an n-type SiC region, a metal layer, and a conductive layer provided between the n-type SiC region and the metal layer, the conductive layer including titanium (Ti), oxygen (O), at least one first element from zirconium (Zr) and hafnium (Hf), and at least one second element from vanadium (V), niobium (Nb), and tantalum (Ta).

Abstract: According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part.

Abstract: The invention provides the Magnetoelectric Effect Material consisted of a single isotope, the alloy of isotopes, or the compound of isotopes. The invention applies enrichment and purification to increase the isotope abundance, to create the density of nuclear exciton by irradiation, and therefore increase the magnetoelectric effect of the crystal of single isotope, the alloy crystal of isotopes and the compound crystal of isotopes. The invention provides the manufacturing method including the selection rules of isotopes, the fabrication processes and the structure of composite materials. The invention belongs to the area of the nuclear science and the improvement of material character. The invention using the transition of entangled multiple photons to achieve the delocalized nuclear exciton. The mix of selected isotopes adjusts the decay lifetime of nuclear exciton and the irradiation efficiency to generate the nuclear exciton.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first dielectric layer over a substrate, forming a first trench in the first dielectric layer, forming a metal line in the first trench, removing a first portion of the metal line to form a second trench and removing a second portion of the metal line to form a third trench. A third portion of the metal line is disposed between the second and third trenches. The method also includes forming a second dielectric layer in the second and third trenches.

Abstract: A semiconductor device includes a substrate having an edge, a semiconductor layer provided on a substrate, an electrode pad provided on the semiconductor layer, an inorganic insulating film having a first opening through which an upper surface of the electrode pad is exposed, and a resin film provided on the inorganic insulating film, the resin film having a second opening and a third opening separated from each other, where the upper surface of the electrode pad is exposed through the second opening, where the third opening is located between the second opening and the edge of the substrate, and where a bottom of the third opening is constituted by the resin film or the inorganic insulating film.

Abstract: Provided is a phase change memory device including a graphene layer inserted between a lower electrode into which heat flows and a phase change material layer, to prevent the heat from being diffused to an outside so as to efficiently transfer the heat to the phase change material layer, and a method of fabricating the phase change memory device. The phase change memory device includes a lower electrode; an insulating layer formed to enclose the lower electrode; a graphene layer formed on the lower electrode; a phase change material layer formed on the graphene layer and the insulating layer; and an upper electrode formed on the phase change material layer. Since a phase of the phase change material layer is changed at a small amount of driving current, the phase change memory device is fabricated to have a high driving speed and a high integration.

Abstract: A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer.

Abstract: A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.

Abstract: A semiconductor device includes a substrate having an edge, a semiconductor layer provided on a substrate, an electrode pad provided on the semiconductor layer, an inorganic insulating film having a first opening through which an upper surface of the electrode pad is exposed, and a resin film provided on the inorganic insulating film, the resin film having a second opening and a third opening separated from each other, where the upper surface of the electrode pad is exposed through the second opening, where the third opening is located between the second opening and the edge of the substrate, and where a bottom of the third opening is constituted by the resin film or the inorganic insulating film.

Abstract: A mask may be used in a process for manufacturing a semiconductor device. The semiconductor device may include a source line, a first drain contact terminal, and a second drain contact terminal. The mask may include the following elements: a source-line corresponding light-transmitting portion, which corresponds to the source line; a first-drain-contact-terminal corresponding light-transmitting portion, which corresponds to the first drain contact terminal; a second-drain-contact-terminal corresponding light-transmitting portion, which corresponds to the second drain contact terminal; and a first light-blocking portion, which abuts at least one of the source-line corresponding light-transmitting portion, the first-drain-contact-terminal corresponding light-transmitting portion, and the second-drain-contact-terminal corresponding light-transmitting portion.

Abstract: A manganese oxide layer is deposited as a hard mask layer on substrate including at least a dielectric material layer. An optional silicon oxide layer may be formed over the manganese oxide layer. A patterned photoresist layer can be employed to etch the optional silicon oxide layer and the manganese oxide layer. An anisotropic etch process is employed to etch the dielectric material layer within the substrate. The dielectric material layer can include silicon oxide and/or silicon nitride, and the manganese oxide layer can be employed as an effective etch mask that minimizes hard mask erosion and widening of the etched trench. The manganese oxide layer may be employed as an etch mask for a substrate bonding process.

Abstract: An interposer fabricating process includes the following steps. A substrate, an oxide layer, and a dielectric layer are stacked from bottom to top, and an interconnect in the dielectric layer is provided, wherein the dielectric layer includes a stop layer contacting the oxide layer and the interconnect includes a metal structure having a barrier layer protruding from the stop layer. The substrate and the oxide layer are removed until exposing the stop layer and the barrier layer by a removing selectivity between the oxide layer and the stop layer. A wafer packaging structure formed by said interposer is also provided.

Abstract: Integrated circuit structures formed using methods herein include a layer, and a material-filled line in the layer. The material-filled line includes a first linear item and a second linear item separated by a separation area of the layer. The first linear item has a first line end where the first linear item contacts the separation area. The second linear item has a second line end where the second linear item contacts the separation area. The first line end and the second line end include line end openings (filled with a material) that increase critical dimension uniformity of the first line end and the second line end.

Abstract: To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-balancing. For example, the stress/management layer can be debonded from the wafer at selected locations, or recesses can be formed in the layer, or phase changes can be induced in the layer. In other embodiments, this layer is tantalum-aluminum that may or may not over-balance the warpage; this layer is believed to reduce warpage due to crystal-phase-dependent stresses which dynamically adjust to temperature changes so as to reduce the warpage (possibly keeping the wafer flat through thermal cycling). Other features are also provided.

Abstract: A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed.

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a passivation layer, a protective layer, a post-passivation interconnect (PPI) structure, and a shielding layer. The semiconductor substrate has electrical circuitry. The dielectric layer is formed on the semiconductor substrate. The passivation layer is formed on the dielectric layer. The first protective layer is formed on the passivation layer. The PPI structure is disposed on the first protective layer and has a signal line and a ground line. The shielding layer is disposed over the semiconductor substrate and between the signal line and the electrical circuitry. The shielding layer is substantially equi-potentially connected to the ground line of the PPI structure.

Abstract: A ruthenium film formation method including: forming a ruthenium oxide film on a substrate; and reducing the ruthenium oxide film into a ruthenium film, wherein the reducing the ruthenium oxide film comprises at least supplying a ruthenium compound gas containing hydrogen as a reducing agent.

Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor layer; and an electrode layer in contact with the silicon carbide semiconductor layer. In a case where the electrode layer is equally divided into two in a thickness direction in one cross section of the electrode layer in the thickness direction to obtain a first region facing the silicon carbide semiconductor layer and a second region opposite to the silicon carbide semiconductor layer, an area of a carbon portion containing the carbon in the first region is wider than an area of the carbon portion in the second region. At an interface region located up to 300 nm from an interface between the silicon carbide semiconductor layer and the electrode layer, the carbon portion includes a plurality of portions disposed with a space interposed therebetween, and a ratio of area occupied by the carbon portion is not more than 40%.

Abstract: Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to VDD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.

Abstract: In various embodiments, electronic devices such as thin-film transistors incorporate electrodes featuring a conductor layer and, disposed below the conductor layer, a barrier layer comprising an alloy of Cu and one or more refractory metal elements selected from the group consisting of Ta, Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Cr, and Ni.