Abstract: An interconnect structure with improved performance and capacitance by providing air gaps inside the dielectric layer by use of a multi-phase photoresist material. The interconnect features are embedded in a dielectric layer having a columnar air gap structure in a portion of the dielectric layer surrounding the interconnect features. The interconnect features may also be embedded in a dielectric layer having two or more phases with a different dielectric constant created. The interconnect structure is compatible with current back end of line processing.

Abstract: A method and structure for creating embedded metal features includes embedded trace substrates wherein bias and signal traces are embedded in a first surface of the embedded trace substrate and extend into the body of the embedded trace substrate. The bias trace and signal trace trenches are formed into the substrate body using LASER ablation, or other ablation, techniques. Using ablation techniques to form the bias and signal trace trenches allows for extremely accurate control of the depth, width, shape, and horizontal displacement of the bias and signal trace trenches. As a result, the distance between the bias traces and the signal traces eventually formed in the trenches, and therefore the electrical properties, such as impedance and noise shielding, provided by the bias traces, can be very accurately controlled.

Abstract: Methods of forming dense seed layers and structures thereof are provided. Seed layers including a monolayer of molecules having a density of about 0.5 or greater may be manufactured over a metal layer, resulting in a well-defined interface region between the metal layer and a subsequently formed material layer. A seed layer including a monolayer of atoms is formed over the metal layer, the temperature of the workpiece is lowered, and a physisorbed layer is formed over the seed layer, the physisorbed layer including a weakly bound layer of first molecules. A portion of the first molecules in the physisorbed layer are dissociated by irradiating the physisorbed layer with energy, the dissociated atoms of the first molecules being proximate the seed layer. The workpiece is then heated, causing integration of the dissociated atoms of the first molecules of the physisorbed layer into the seed layer and removing the physisorbed layer.

Abstract: An electronic component for microwave transmission includes a high resistivity substrate on which is at least located several metallization layers divided into portions. A first set of piled up portions defines a ground ribbon and a second set of piled up portions defines a power ribbon. At least a first active portion of said ground ribbon and a first active portion of said power ribbon are respectively located between the substrate and an uppermost one of the several metallization layers. The electronic component in one implementation is a coplanar waveguide.

Abstract: A semiconductor chip includes a silicon substrate, a first dielectric layer over said silicon substrate, a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure, a polymer bump over said passivation layer, wherein said polymer bump has a thickness of between 5 and 25 micrometers, an adhesion/barrier layer on said pad exposed by said opening, over said passivation layer and on a top surface and a portion of sidewall(s) of said polymer bump, a seed layer on said adhesion/barrier layer; and a third metal layer on said seed layer.

Abstract: An interconnect and method of making the interconnect. The method includes forming a dielectric layer on a substrate, the dielectric layer having a top surface and a bottom surface; forming a first wire and a second wire in the dielectric layer, the first wire separated from the second wire by a region of the dielectric layer; and forming metallic nanoparticles in or on the top surface of the dielectric layer between the first and second wires, the metallic nanoparticles capable of electrically connecting the first wire and the second wire only while the nanoparticles are heated to a temperature greater than room temperature and a voltage is applied between the first and second wires.

Abstract: The invention provides a CSP type semiconductor device with high reliability. The semiconductor device includes a pad electrode formed on a semiconductor substrate, a first passivation film covering an end portion of the pad electrode and having a first opening on the pad electrode, a plating layer formed on the pad electrode in the first opening, a second passivation film covering an exposed portion of the pad electrode between an end portion of the first passivation film and the plating layer, covering an end portion of the plating layer, and having a second opening on the plating layer, and a conductive terminal formed on the plating layer in the second opening.

Abstract: The invention provides an ohmic contact film formed between a doped semiconductor material layer and a conductive material layer of a semiconductor device. The composition of the ohmic contact film according to a preferred embodiment of the invention is represented by the general formula MxQzNy, where M represents the II group chemical element, Q represents the IV group chemical element, N represents the V group chemical element, 1?x?3, 1?y?3, 1?z?3, and x and y and z are molar numbers.

Abstract: A wiring structure of a semiconductor device may have an insulation layer, a spacer and a plug. The insulation layer may be provided on a substrate and may have an opening through which a contact region of the substrate is exposed. The spacer may be provided on a sidewall of the opening. The plug may fill the opening and may include a polysilicon pattern doped with impurities, a metal silicide pattern, and a metal pattern sequentially provided on the substrate.

Abstract: The invention provides a technology for manufacturing a higher performance and higher reliability semiconductor device at low cost and with high yield. The semiconductor device of the invention has a first conductive layer over a first insulating layer; a second insulating layer over the first conductive layer, which includes an opening extending to the first conductive layer; and a signal wiring layer for electrically connecting an integrated circuit portion to an antenna and a second conductive layer adjacent to the signal wiring layer, which are formed over the second insulating layer. The second conductive layer is in contact with the first conductive layer through the opening, and the first conductive layer overlaps the signal wiring layer with the second insulating layer interposed therebetween.

Abstract: A semiconductor device has a porous low-dielectric-constant film formed on a substrate and having an opening and a fine particle film composed of a plurality of aggregately deposited fine particles each having a diameter of not less than 1 nm and not more than 2 nm and formed on a surface of the portion of the porous low-dielectric-constant film which is formed with the opening. The fine particles are filled in voids exposed at the surface of the portion of the porous low-dielectric-constant film which is formed with the opening.

Abstract: An integrated circuit device structure and a process for fabricating the structure wherein the power bus interconnect structure is formed in the aluminum pad or contact layer. An interconnect structure for interconnecting underlying levels of interconnect can also be formed in the aluminum pad layer.

Abstract: An object of the present invention is to provide a transparent positive electrode for use in a face-up-type chip which can emit intense light even using a low drive voltage. The inventive positive electrode for a semiconductor light-emitting device comprises a transparent electrode formed on a semiconductor layer and a bonding pad electrode formed on the transparent electrode, wherein the bonding pad electrode has a reflecting layer that is in contact with at least the transparent electrode.

Abstract: A semiconductor chip 100 includes a semiconductor substrate (not shown), and a stacked film 150 formed over the semiconductor substrate, which includes carbon-containing insulating films such as a first interlayer insulating film 106, and carbon-free insulating films such as an underlying layer 102 and a top cover film 124. The end faces of the carbon-free insulating films herein are located on the outer side of the end faces of the carbon-containing insulating films. The carbon composition of the carbon-containing insulating films is lowered in the end portions thereof than in the inner portions. The film density of the carbon-containing insulating films is raised in the end portions thereof than in the inner portions.

Abstract: A semiconductor device comprises: a lower interconnect formed over a semiconductor substrate; an insulating film formed on the lower interconnect; a via hole penetrating the insulating film to reach the lower interconnect; a first barrier film covering bottom and side surfaces of the via hole; and a metal film filling the via hole covered with the first barrier film. A portion of the first barrier film covering a lower end of the side surface of the via hole is thicker than a portion covering the bottom surface of the via hole.

Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.

Abstract: A system and method for providing low dielectric constant insulators in integrated circuits is provided. One aspect of this disclosure relates to a method for forming an integrated circuit insulator. The method includes forming an insulating layer using a first structural material upon a substrate, the first structural material having sufficient mechanical characteristics to support metal during chemical-mechanical polishing (CMP). The method also includes depositing a metallic layer upon the insulating layer, the metallic layer adapted to be used as a wiring channel. The method further includes processing the metallic layer to form the wiring channel, where processing includes CMP. In addition, the method includes removing and replacing at least a portion of the first structural material with a second structural material, the second structural material having insufficient mechanical characteristics to support metal during CMP. Other aspects and embodiments are provided herein.

Abstract: A semiconductor device comprises a first electrode-lead having a first Au film, a first Ni film, a Cu film, a second Au film and a second Ni film stacked in order, a second electrode-lead having a first Au film, a first Ni film, a Cu film, a second Au film and a second Ni film stacked in order and a semiconductor chip having a first electrode formed on a first surface of the semiconductor chip and a second electrode formed on a second surface of the semiconductor chip, the first electrode being formed on an opposite side of the second electrode. The semiconductor chip mounted on the first electrode-lead, the second electrode facing the first surface of the first electrode-lead. A first connection conductor is connected the first electrode of the semiconductor chip to the first surface of the second electrode-lead. The first electrode-lead, the second electrode-lead and the semiconductor chip are housed in a package.

Abstract: An improved semiconductor device, integrated circuit, and integrated circuit fabrication method introduce highly controlled air cavities within high-speed copper interconnects. A polymer material is introduced on the edges of interconnect lines and vias within an interconnect stack. This incorporates and controls air cavities formation, thus enhancing the signal propagation performance of the semiconductor interconnects.

Abstract: A plurality of vertically spaced-apart microsprings are provided to increase microspring contact force, contact area, contact reliability, and contact yield. The microspring material is deposited, either as a single layer or as a composite of multiple sub layers, to have a tailored stress differential along its cross-section. A lower microspring may be made to push up against an upper microspring to provide increased contact force, or push down against a substrate to ensure release during manufacture. The microsprings may be provided with similar stress differentials or opposite stress differentials to obtain desired microspring profiles and functionality. Microsprings may also be physically connected at their distal ends for increased contact force. The microsprings may be formed of electrically conductive material or coated with electrically conductive material for probe card and similar applications.

Abstract: Methods may be provided for forming an electronic device including a substrate, a conductive pad on the substrate, and an insulating layer on the substrate wherein the insulating layer has a via hole therein exposing a portion of the conductive pad. In particular, a conductive structure may be formed on the insulating layer and on the exposed portion of the conductive pad. The conductive structure may include a base layer of titanium-tungsten (TiW) and a conduction layer of at least one of aluminum and/or copper. Moreover, the base layer of the conductive structure may be between the conduction layer and the insulating layer. Related devices are also discussed.

Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layer is less than 1500 ?, e.g., between 100 and 750 ?. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting of aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.

Abstract: A method of fabricating an integrated circuit device is provided. The method includes sequentially forming a lower interconnection layer, a catalyst layer, and a buffer layer on a semiconductor substrate, forming an interlayer dielectric layer to cover the buffer layer, forming a contact hole through the interlayer dielectric layer so that a top surface of the buffer layer may be partially exposed, removing a portion of the buffer layer exposed by the contact hole so that a top surface of the catalyst layer may be exposed, and growing carbon nanotubes from a portion of the catalyst layer exposed by the contact hole so that the contact hole may be filled with the carbon nanotubes.

Abstract: A structure for reducing stress for vias and a fabricating method thereof are provided. One or more wires or vias in the thickness direction are enframed with the use of a stress block in a lattice structure to be isolated from being directly contacted with the major portion of insulating materials with a high coefficient of thermal expansion. Thus, the shear stress resulting from temperature loading can be blocked or absorbed by the stress block.

Abstract: A method of forming integrated circuit structures, such as capacitors and conductive plugs, within contact openings formed in a photosensitive silicone ladder polymer (PVSQ) is disclosed. Contact openings with reduced striations and CD loss are formed in a photosensitive silicone ladder polymer (PVSQ) layer by patterning the PVSQ film employing a photomask with a predefined pattern, exposing the PVSQ film to i-line, developing the exposed PVSQ film in a mixture of anisole/xylene in a ratio of about 1:2 for about 30 seconds, and subsequently optionally annealing the undeveloped PVSQ film at a temperature of about 300° C. to about 600° C.

Abstract: The present invention provides a structure combining an IC integrated substrate and a carrier, which comprises a carrier and an IC integrated substrate formed on the carrier. The interface between the IC integrated substrate and the carrier has a specific area at which the interface adhesion is different from that at the remaining area of the interface. The present invention also provides a method of manufacturing the above structure and a method of manufacturing electronic devices using the above structure.

Abstract: A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

Abstract: A semiconductor device having macro circuit including concentrated fine interconnections and extension wiring for connecting the macro circuit and the outer circuit. The widths of the fine interconnections are less than 0.1 ?m. An end of the extension wiring is connected to at least two of fine interconnections of the macro circuit arranged in parallel. By this configuration, the possibility of disconnection at the portion where the end of the extension wiring and the fine interconnections are connected is suppressed.

Abstract: Disclosed structures and methods inhibit atomic migration and related capacitive-resistive effects between a metallization layer and an insulator layer in a semiconductor structure. One exemplary structure includes an inhibiting layer between an insulator and a metallization layer. The insulator includes a polymer or an insulating oxide compound. And, the inhibiting layer has a compound formed from a reaction between the polymer or insulating oxide compound and a transition metal, a representative metal, or a metalloid.

Abstract: An integrated circuit device includes a semiconductor chip with a metallization layer on the chip. A gas-phase deposited insulation layer is disposed on the metallization layer.

Abstract: A semiconductor device including: a semiconductor chip including a substrate, an outer-connection electrode, and a bump, wherein the bump has a first conductive layer and a second conductive layer provided on the first conductive layer, and the second conductive layer is made of copper; a wiring board having a land; and an insulating material dispersed with conductive particles, wherein the conductive particles connect between the bump and the land, wherein an electrical connection is established by the conductive particles having penetrated to both the second conductive layer and the land.

Abstract: The present invention relates to a method for connecting electrodes comprising: interposing the polyphthalide represented by the formula (I): wherein R represents a divalent aromatic hydrocarbon group or a divalent heteroring-containing aromatic group, R1 represents an alkyl group, a fluorinated alkyl group, an alkoxy group or a halogen atom, where the number of R1 is 0 to 4, X represents O or N—R3, provided that R3 represents one of the following groups, Y represents SO2 or Co and n represents a number of repeating units in the polymer, as a pressure-sensitive conductive polymer at least partially between electrodes opposed to each other; and applying a pressure to fix the both electrodes, a surface-treated wiring board comprising polyphthalide represented by the formula (I) formed on at least part of the surface of the electrode part, an adhesive film comprising an adhesive and polyphthalide represented by the formula (I), and an electrode-connected structure using the same.

Abstract: An integrated circuit includes an array of memory cells and a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of memory cells. The integrated circuit includes conductive cladding contacting the doped semiconductor line.

Abstract: A system and method for providing low dielectric constant insulators in integrated circuits is provided. One aspect of this disclosure relates to a method for forming an integrated circuit insulator. The method includes forming an insulating layer using a first structural material upon a substrate, the first structural material having sufficient mechanical characteristics to support metal during chemical-mechanical polishing (CMP). The method also includes depositing a metallic layer upon the insulating layer, the metallic layer adapted to be used as a wiring channel. The method further includes processing the metallic layer to form the wiring channel, where processing includes CMP. In addition, the method includes removing and replacing at least a portion of the first structural material with a second structural material, the second structural material having insufficient mechanical characteristics to support metal during CMP. Other aspects and embodiments are provided herein.

Abstract: A semiconductor device with a multilayer interconnection structure comprises a semiconductor substrate, a plurality of metal wiring layers provided on the semiconductor device and electrically insulated from the upper and lower layers by an interlayer insulation film, and via holes penetrating through the interlayer insulation film and connecting the wirings of the first metal wiring layer and the second metal wiring layer positioned above the first metal wiring layer. And, potential of predetermined wiring of the first metal wiring layer is electrically floating from the semiconductor substrate, and a capacitance value between the wiring of the first metal wiring layer and the semiconductor substrate per one via provided on the predetermined wiring of the first metal wiring layer is a predetermined value or less.

Abstract: A driving circuit of a liquid crystal display panel includes a substrate, a plurality of driver IC chips located on the substrate, a current supplier, and a first conductive wire set. The first conductive wire set has a plurality of conductive wire segments for connecting the driver IC chips in parallel to the current supplier. Furthermore, the conductive wire segments each have a form, such that paths formed of the conductive wire segments from the current supplier to the respective driver IC chips have an equal resistance, and, accordingly, each of the driver IC chips obtain the same input voltage. Hence, a problem of band mura is avoided.

Abstract: A multilayer circuit substrate for multi-chip modules or hybrid circuits includes a dielectric base substrate, conductors formed on the base substrate and a vacuum deposited dielectric thin film formed over the conductors and the base substrate. The vacuum deposited dielectric thin film is patterned using sacrificial structures formed by shadow mask techniques. Substrates formed in this manner enable significant increases in interconnect density and significant reduction of over-all substrate thickness.

Abstract: A multilayer interconnection structure of the present invention includes first interconnection, second interconnection belonging to an interconnection layer different from an interconnection layer to which the first layer belongs, and third interconnection for connecting the first and second interconnections, the third interconnection belonging to a different interconnection layer and including interconnection along a body diagonal for connecting two points in different planes belong to different interconnection layers. A method for producing the multilayer interconnection structure includes a step of forming the third interconnection, the step including a step of forming a through hole along the body diagonal, and a step of filling the through hole with a conductive material.

Abstract: An electronic structure having wiring, and an associated method of designing the structure, for limiting a temperature gradient in the wiring. The electronic structure includes a substrate having a layer that includes a first and second wire which do not physically touch each other. The first and second wires are adapted to be at an elevated temperature due to Joule heating in relation to electrical current density in the first and second wires. The first wire is electrically and thermally coupled to the second wire by an electrically and thermally conductive structure that exists outside of the layer. The width of the second wire is tailored so as to limit a temperature gradient in the first wire to be below a threshold value that is predetermined to be sufficiently small so as to substantially mitigate adverse effects of electromigration in the first wire.

Abstract: A thermal enhanced low profile package structure and a method for fabricating the same are provided. The package structure typically includes a metallization layer with an electronic component thereon which is between two provided dielectric layers. The metallization layer as well as the electronic component is embedded and packaged while the substrates are laminated via a lamination process. The fabricated package structure performs not only a superior electric performance, but also an excellent enhancement in thermal dissipation.

Abstract: In one embodiment, a method for forming a barrier material on a substrate is provided which includes exposing a dielectric layer on the substrate to a plasma during a preclean process, wherein the dielectric layer contains a feature having sidewalls and a bottom surface, and depositing a tungsten-containing barrier material containing tungsten nitride on the sidewalls and the bottom surface of the feature during a cyclic layer deposition process. The method further provides depositing a metal-containing seed layer on the tungsten-containing barrier material and depositing a metal-containing layer over the metal-containing seed layer to fill the feature.

Abstract: There is provided a solution to the problem of the poor adhesion in the pad portion while inhibiting the dishing in the pad portion. An SiON film, which covers insulating areas and has an opening above Cu pad areas, is formed, and a barrier metal film is formed in the opening of the SiON film. Such constitution provides the structure, in which the upper portion of the interfaces between the Cu pad areas and the insulating areas are covered by the SiON film.

Abstract: A semiconductor device comprises: a plurality of first wiring lines formed in a first layer with a first wiring width and a first wiring space; a plurality of second wiring lines formed in a second layer different from the above-described first layer with a second wiring width and a second wiring space larger than the above-described first wiring width and first wiring space; and a contact plug connecting the first wiring line and second wiring line. The above-described contact plug is formed over a plurality of adjacent ones of the above-described first wiring lines and has a pattern connecting the plurality of adjacent ones of the above-described first wiring lines and one of the above-described second wiring lines.

Abstract: The object of the present invention is to provide a semiconductor element containing an n-type gallium nitride based compound semiconductor and a novel electrode that makes an ohmic contact with the semiconductor. The semiconductor element of the present invention has an n-type Gallium nitride based compound semiconductor and an electrode that forms an ohmic contact with the semiconductor, wherein the electrode has a TiW alloy layer to be in contact with the semiconductor. According to a preferable embodiment, the above-mentioned electrode can also serve as a contact electrode. According to a preferable embodiment, the above-mentioned electrode is superior in the heat resistance. Moreover, a production method of the semiconductor element is also provided.

Abstract: A configuration terminal for integrated devices includes a first and a second portion structurally independent and connected to respective first and second terminals and it has at least one contact terminal suitable to be selectively connected to such first and second terminals. Also a method configures an integrated device that includes a plurality of address pads and respective supply pins. The method includes: realizing at least one configuration terminal having a first and a second portion structurally independent and connected to at least one contact terminal; providing the contact of such first and second portions with respective terminals; and configuring the device by a short-circuiting of the contact terminal with at least one of said terminals.

Abstract: An ohmic contact in accordance with the invention includes a layer of p-type GaN-based material. A first layer of a group II-VI compound semiconductor is located adjacent to the layer of p-type GaN-based material. The ohmic contact further includes a metal layer that provides metal contact. A second layer of a different II-VI compound semiconductor is located adjacent to the metal layer.

Abstract: A method of forming a protective structure on a top metal line on an interconnect structure is disclosed. The method includes providing a plate opening in the passivation layer on the top metal line and forming a protective plate in the plate opening on the top metal line.

Abstract: A semiconductor device and a fabrication method thereof are proposed. A first dielectric layer is formed on a semiconductor substrate having at least one bond pad, wherein the first dielectric layer has a first opening for exposing the bond pad and a second opening at a predetermined position for redistribution. A first metallic layer is applied on the first dielectric layer and in the first and second openings. A second metallic layer and a third metallic layer are formed on the first metallic layer at positions corresponding to the first and second openings, respectively. A second dielectric layer and a solder bump are formed on the second and third metallic layers, respectively. The second metallic layer can assure electrical quality of the first metallic layer corresponding to the first opening without having an electrical break of the first metallic layer for redistribution.

Abstract: A method of forming an interconnect structure in an inter-layer dielectric (ILD) material, the method include the steps of creating one or more via openings in the ILD material; forming a first liner covering at least one of the one or more via openings; creating one or more trench openings on top of at least one of the one or more via openings covered by the first liner; and forming a second liner covering the trenching openings and at least part of the first liner. An interconnect structure formed by the method is also provided.

Abstract: Embodiments relate to a semiconductor device and a method of fabricating semiconductor device, that may uniformly form a barrier layer in a via hole to thus prevent layers from being broken. In embodiments, a method of fabricating a semiconductor device may include forming an interlayer dielectric layer on a substrate, forming via holes selectively on the interlayer dielectric layer, forming a first metal layer on a top surface of the substrate including inner portion of the via hole, forming spacers on sides of the via holes by etching back the first metal layer, forming a second metal layer on the substrate including the spacer, and forming a tungsten layer by depositing tungsten on the second metal layer.