Abstract: A memory cell having a kinked polysilicon layer structure, or a polysilicon layer structure with a top portion being narrower than a bottom portion, may greatly reduce random single bit (RSB) failures and may improve high density plasma (HDP) oxide layer fill-in by reducing defects caused by various impurities and/or a polysilicon layer short path. A kinked polysilicon layer structure may also be applied to floating gate memory cells either at the floating gate structure or the control gate structure.

Abstract: The present disclosure provides for methods of fabricating a semiconductor device and such a device. A method includes providing a substrate including at least two isolation features, forming a fin substrate above the substrate and between the at least two isolation features, forming a silicon liner over the fin substrate, and oxidizing the silicon liner to form a silicon oxide liner over the fin substrate.

Abstract: A semiconductor structure includes a substrate, a dielectric layer and a fluoride metal layer. The dielectric layer is located on the substrate. The fluoride metal layer is located on the dielectric layer. Furthermore, the present invention also provides a semiconductor process to form said semiconductor structure.

Abstract: A semiconductor device includes gate structures including a tunnel insulating layer pattern, a floating gate, a dielectric layer pattern and a control gate sequentially disposed on a substrate. The control gate includes an impurity doped polysilicon layer pattern and a metal layer pattern. The gate structures are spaced apart from each other on the substrate. A capping layer pattern is disposed on a sidewall portion of the metal layer pattern and includes a metal oxide. An insulating layer covers the gate structures and the capping layer pattern. The insulating layer is formed on the substrate and includes an air-gap therein.

Abstract: A semiconductor device includes a substrate having an active region, a gate structure on the active region, and spacers formed on opposite sides of the gate structure. The gate structure includes a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and sidewalls on both side surfaces of the gate structure. Each of the sidewalls is interposed between the metal gate and one of the spacers. The sidewalls include a self-assembly material. The gate dielectric layer includes a high-K material. The spacers include silicon nitride. The gate structure also includes a buffer layer interposed between the metal gate and the gate dielectric layer.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of pillars by etching a semiconductor substrate, forming a gate dielectric layer on sidewalls of the pillars and on surfaces of the semiconductor substrate between the pillars, forming an implant damage in a portion of the gate dielectric layer between two pillars by implanting ions into the portion of the gate dielectric layer, forming vertical gates to cover the sidewalls of the pillars, and removing the implant damage.

Abstract: A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.

Abstract: A manufacturing method of a semiconductor device having metal gate includes providing a substrate having a first semiconductor device, a second semiconductor device, and a first insulating layer covering the first semiconductor device and the second semiconductor device formed thereon, performing an etching process to remove a portion of the first insulating layer to expose a portion of the first semiconductor device and the second semiconductor device, forming a second insulating layer covering the first semiconductor device and the second semiconductor device, performing a first planarization process to remove a portion of the second insulating layer, forming a first gate trench and a second gate trench respectively in the first semiconductor device and the second semiconductor device, and forming a first metal gate and a second metal gate respectively in the first gate trench and the second gate trench.

Abstract: A semiconductor device includes a gate stacked structure including a gate dielectric layer over a semiconductor substrate, a metal layer formed over the gate dielectric layer, and a capping layer formed over the metal layer, where the capping layer includes a chemical element with a higher concentration at an interface between the capping layer and the metal layer than another region of the capping layer and the chemical element is operable to control an effective work function (eWF) of the gate stacked structure.

Abstract: A metal-oxide-semiconductor (MOS) device having a selectable threshold voltage determined by the composition of an etching solution contacting a metal layer. The MOS device can be either a p-type or n-type MOS and the threshold voltage is selectable for both types of MOS devices. The etching solution is either an oxygen-containing solution or a fluoride-containing solution. The threshold voltage is selected by adjusting the flow rate of inert gases into an etching chamber to control the concentration of oxygen gas or nitrogen trifluoride.

Abstract: An anisotropic silicon nitride etch provides selectivity to silicon and silicon oxide by forming a fluorohydrocarbon-containing polymer on silicon surfaces and silicon oxide surfaces. Selective fluorohydrocarbon deposition is employed to provide selectivity to non-nitride surfaces. The fluorohydrocarbon-containing polymer interacts with silicon nitride to form a volatile compound, thereby enabling etching of silicon nitride. The fluorohydrocarbon-containing polymer interacts with silicon oxide at a low reaction rate, retarding, or completely stopping, the etching of silicon oxide. The fluorohydrocarbon-containing polymer does not interact with silicon, and protects silicon from the plasma. The anisotropic silicon nitride etch can be employed to etch silicon nitride selective to silicon and silicon oxide in any dimension, including small dimensions less than 50 nm.

Abstract: The present invention relates to a fabricating method of a semiconductor element. First, a substrate is provided and a first layout structure having a first width is formed on the substrate. Then, an etching mask is formed to cover the first layout structure, and the etching mask exposes a portion of the first layout structure. After that, the first layout structure is etched with the etching mask to form a second layout structure having a second width. The second width is less than the first width. This fabricating method is capable of finishing the fabrication of gate structures in two different directions. Accordingly, the layout flexibility is improved.

Abstract: Methods for controlling the height of semiconductor structures are disclosed. Amorphous carbon is used as a stopping layer for controlling height variability. In one embodiment, the height of replacement metal gates for transistors is controlled. In another embodiment, the step height of a shallow trench isolation region is controlled.

Abstract: The invention relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a CMOS semiconductor device comprises a substrate comprising an isolation region surrounding and separating a P-active region and an N-active region; a P-metal gate electrode over the P-active region and extending over the isolation region, wherein the P-metal gate electrode comprises a P-work function metal and an oxygen-containing TiN layer between the P-work function metal and substrate; and an N-metal gate electrode over the N-active region and extending over the isolation region, wherein the N-metal gate electrode comprises an N-work function metal and a nitrogen-rich TiN layer between the N-work function metal and substrate, wherein the nitrogen-rich TiN layer connects to the oxygen-containing TiN layer over the isolation region.

Abstract: The present disclosure provides a method including providing a substrate having a first opening and a second opening on the substrate. A blocking layer is formed in the first opening. A second metal gate electrode is formed the second opening while the blocking layer is in the first opening. The blocking layer is then removed from the first opening, and a first metal gate electrode formed. In embodiments, this provides for a device having a second gate electrode that includes a second work function layer and not a first work function layer, and the first gate electrode includes the first work function layer and not the second work function layer.

Abstract: The present disclosure provides a method of semiconductor device fabrication including removing a sacrificial gate structure formed on a substrate to provide an opening. A metal gate structure is then formed in the opening. The forming of the metal gate structure includes forming a first layer (including metal) on a gate dielectric layer, wherein the first layer includes a metal and performing a stress modulation process on the first layer. The stress modulation process may include ion implantation of a neutral species such as silicon, argon, germanium, and xenon.

Abstract: A method for fabricating a semiconductor device is disclosed. A dummy gate feature is formed between two active gate features in an inter-layer dielectric (ILD) over a substrate. An isolation structure is in the substrate and the dummy gate feature is over the isolation structure. Source/drain (S/D) features are formed at edges of the active gate features in the substrate for forming transistor devices. The disclosed method provides an improved method for reducing parasitic capacitance among the transistor devices. In an embodiment, the improved formation method is achieved by introducing species into the dummy gate feature to increase the resistance of the dummy gate feature.

Abstract: Semiconductor devices and related fabrication methods are provided. An exemplary fabrication method involves forming a pair of gate structures having a dielectric region disposed between a first gate structure of the pair and a second gate structure of the pair, and forming a voided region in the dielectric region between the first gate structure and the second gate structure. The first and second gate structures each include a first gate electrode material, wherein the method continues by removing the first gate electrode material to provide second and third voided regions corresponding to the gate structures and forming a second gate electrode material in the first voided region, the second voided region, and the third voided region.

Abstract: A metal gate process includes the following steps. An isolating layer on a substrate is provided, where the isolating layer has a first recess and a second recess. A first metal layer covering the first recess and the second recess is formed. A material is filled in the first recess but exposing a top part of the first recess. The first metal layer in the top part of the first recess and in the second recess is simultaneously removed. The material is removed. A second metal layer and a metal gate layer in the first recess and the second recess are sequentially filled.

Abstract: A wet process utilizing a dilute acid oxidant solution, for example, a dilute sulfuric acid with hydrogen peroxide is used in the fabrication of a metal gate electrode of a semiconductor device, offering high etch selectivity and high controllability to achieve a desired profile for the metal gate electrode. In some embodiments, the dilute acid oxidant solution is a dilute sulfuric peroxide solution, comprising at least 50% or 80% by weight of water, less than 30% or 15% by weight of sulfuric acid, and less than 20% or 20% of hydrogen peroxide with optionally less than 100 ppm or 30 ppm ozone. In some embodiments, the dilute sulfuric peroxide solution further comprises less than 100 ppm of hydrofluoric acid. The dilute acid oxidant solution can be used effectively to clean the metal gate electrode or to form an undercut on a metal gate layer of the metal gate electrode.

Abstract: A method for manufacturing a MOSFET includes the steps of preparing a substrate (10) composed of silicon carbide, forming a gate oxide film (20) in contact with the substrate (10), and introducing nitrogen atoms in a region including an interface between the substrate (10) and the gate oxide film (20). Then, in the step of introducing nitrogen atoms, the substrate (10) on which the gate oxide film (20) has been formed is heated in an atmospheric gas formed by heating a nitriding process gas containing nitrogen atoms but not containing oxygen atoms to a temperature exceeding 1200° C., so that nitrogen atoms are introduced in the region including the interface between the substrate (10) and the gate oxide film (20).

Abstract: A semiconductor device comprises a buried gate formed in a mat and in an adjacent dummy region. A space larger than is conventional is formed in a dummy region of a mat edge where the buried gate is to be created. This larger space inhibits shortening of an end of a buried gate and reduction in pattern size attributable to lithographic distortion arising between patterned (mat) and unpatterned (dummy) regions. Device reliability is thereby improved by avoiding gap-fill defects of a gate material.

Abstract: Methods for forming a metal gate structure on a substrate are provided herein. In some embodiments, a method for forming a metal gate structure on a substrate having a dielectric layer formed on the substrate may include depositing a metal layer while providing a process gas comprising oxygen to form an oxygen doped work function layer atop the dielectric layer; and depositing a metal gate layer atop dielectric layer.

Abstract: A nonvolatile memory device and a method of manufacturing thereof are provided. The method includes forming a floating gate on a substrate, forming a dielectric layer to conform to a shape of the floating gate, forming a conductive layer to form a control gate on the substrate, the control gate covering the floating gate and the dielectric layer, forming a photoresist pattern on one side of the conductive layer, forming the control gate in the form of a spacer to surround sides of the floating gate, the forming of the control gate including performing an etch-back on the conductive layer until a portion of the dielectric layer on the floating gate is exposed, and forming a poly pad, to which a plurality of contact plugs are connected, on one side of the control gate, the forming of the poly pad including removing the photoresist pattern.

Abstract: A method for defining an insulating area in a semiconductor substrate, including a step of forming of a bonding layer on the walls and the bottom of a trench defined in the substrate. A step of passivation of the apparent surface of said bonding layer, at least close to the surface of said semiconductor substrate.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.

Abstract: Methods are disclosed to fabricate a transistor, for example a FinFET, by forming over a substrate at least one electrically conductive channel between a source region and a drain region; forming a gate structure to be disposed over a portion of the channel, the gate structure having a width and a length and a height defining two opposing sidewalls of the gate structure and being formed such that the channel said passes through the sidewalls; forming spacers on the sidewalls; forming a layer of epitaxial silicon over the channel; removing the spacers; and forming a dielectric layer to be disposed over the gate structure and portions of the channel that are external to the gate structure such that a capacitance-reducing air gap underlies the dielectric layer and is disposed adjacent to the sidewalls of said gate structure in a region formerly occupied by the spacers.

Abstract: The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature.

Abstract: A method for manufacturing a semiconductor device having a MOS transistor, includes forming a gate electrode material layer on a first insulating film formed on a semiconductor substrate, forming an etching mask on the gate electrode material layer, forming a gate electrode by patterning the gate electrode material layer such that a protective film that protects at least a lower portion of a side face of the gate electrode and a portion of the first insulating film, which is adjacent to the side face, is formed while the gate electrode material layer is patterned, forming a second insulating film on the semiconductor substrate on which the gate electrode is formed, and forming an interlayer insulation film on the second insulating film.

Abstract: Semiconductor materials, particularly III-V materials used to form, e.g., a finlike structure can suffer structural damage during chemical mechanical polishing steps. This damage can be reduced or eliminated by oxidizing the damaged surface of the material and then etching away the oxidized material. The etching step can be accomplished simultaneously with a step of etching back a patterned oxide layers, such as a shallow trench isolation layer.

Abstract: Disclosed is a semiconductor device including a drift region of a first doping type, a junction between the drift region and a device region, and at least one field electrode structure in the drift region. The field electrode structure includes a field electrode, a field electrode dielectric adjoining the field electrode and arranged between the field electrode and the drift region, and having an opening, at least one of a field stop region and a generation region.

Abstract: A passivation film is formed on a compound semiconductor layered structure, an electrode formation scheduled position for the passivation film is thinned by dry etching, a thinned portion of the passivation film is penetrated by wet etching to form an opening, and a gate electrode is formed on the passivation film so as to embed this opening by an electrode material.

Abstract: Semiconductor devices with replacement gate electrodes are formed with different materials in the work function layers. Embodiments include forming first and second removable gates on a substrate, forming first and second pairs of spacers on opposite sides of the first and second removable gates, respectively, forming a hardmask layer over the second removable gate, removing the first removable gate, forming a first cavity between the first pair of spacers, forming a first work function material in the first cavity, removing the hardmask layer and the second removable gate, forming a second cavity between the second pair of spacers, and forming a second work function material, different from the first work function material, in the second cavity.

Abstract: Multi-gate devices and methods of their fabrication are disclosed. A multi-gate device can include a gate structure and a plurality of fins. The gate structure envelops a plurality of surfaces of the fins, which are directly on a substrate that is composed of a semiconducting material. Each of the fins provides a channel between a respective source and a respective drain, is composed of the semiconducting material and is doped. A first fin of the plurality of fins has a first height that is different from a second height of a second fin of the plurality of fins such that drive currents of the first and second fins are different. Further, the first and second fins form a respective cohesive structure of the semiconducting material with the substrate. In addition, surfaces of the substrate that border the fins are disposed at a same vertical position.

Abstract: The present invention discloses a thin film transistor (TFT), a manufacturing method thereof, an array substrate, and a liquid crystal display (LCD) device. The TFT comprises a gate electrode and a source electrode. The gate electrode comprises a first metal layer block and a second metal layer block positioned on the first metal layer block. The thermal expansion coefficient of the second metal layer block is less than that of the first metal layer block. The top surface of the first metal layer block is in contact with the bottom surface of the second metal layer block, and the width of the top surface of the first metal layer block accords with that of the bottom surface of the second metal layer block. The present invention can prevent hillocks from being produced, and can effectively avoid the phenomenon of electricity leakage.

Abstract: The present invention discloses a CMOS-MEMS cantilever structure. The CMOS-MEMS cantilever structure includes a substrate, a circuit structure, and a cantilever beam. The substrate has a circuit area and a sensor unit area defined thereon. The circuit structure is formed in the circuit area. The cantilever beam is disposed in the sensor unit area with one end floating above the substrate and the other end connecting to the circuit structure. With the above arrangement, the manufacturing process of CMOS-MEMS cantilever structure of this invention can be simplified. Furthermore, the structure of the cantilever beam is thinned down and therefore has a higher sensitivity.

Abstract: A method for fabricating a semiconductor device including providing a semiconductor substrate having a first opening and second opening. A dielectric layer is formed on the substrate. An etch stop layer on the dielectric layer in the first opening. Thereafter, a work function layer is formed on the etch stop layer and fill metal is provided on the work function layer to fill the first opening.

Abstract: A semiconductor process includes the following steps. An interdielectric layer is formed on a substrate and the interdielectric layer has a first recess and a second recess. A metal layer is formed to cover the surface of the interdielectric layer, the first recess and the second recess. Partially fills a sacrificed material into the first recess and the second recess so that a portion of the metal layer in each of the recesses is respectively covered. The uncovered metal layer in each of the recesses is removed. The sacrificed material is removed. An etching process is performed to remove the remaining metal layer in the first recess and reserve the remaining metal layer in the second recess.

Abstract: A thin film transistor array panel includes: an substrate; a gate line and a gate pad portion disposed on the substrate; a gate insulating layer disposed on the gate line and the gate pad portion; a data line and a data pad portion disposed on the gate insulating layer; a gate assistance pad portion disposed at a position corresponding to the gate pad portion; a first insulating layer disposed on the data line and removed at the gate pad portion and the data pad portion; a first field generating electrode disposed on the first insulating layer; a second insulating layer disposed on the first field generating electrode and removed at the gate pad portion and the data pad portion; and a second field generating electrode disposed on the second insulating layer. The assistance gate pad portion and the gate insulating layer include a contact hole exposing the gate pad portion.

Abstract: Semiconductor device fabrication methods having enhanced control in recessing processes are provided. In a method for fabricating a semiconductor device or plurality of them, a structure is formed. The method includes preparing a limited amount of the structure having a depth of less than ten atomic layers for removal. Further, the method includes performing a removal process to remove the limited amount of the structure. The method repeats preparation of successive limited amounts of the structure for removal, and performance of the removal process to form a recess at an upper portion of the structure.

Abstract: The present invention belongs to the technical field of integrated semiconductor circuits, and relates to a method for depositing a gate oxide and a gate electrode selectively. The present invention makes use of Octadecyltriethoxysilane's (ODTS') easy attachment to the Si—OH interface and difficult attachment to the Si—H interface, and selectively deposits the gate oxide and gate electrode materials, which avoids the unnecessary waste of materials and saves cost. Meanwhile, the present invention will transfer the etching of the gate oxide and gate electrode into the etching of SiO2 so as to reduce the difficulty of the etching process and increase the production efficiency.

Abstract: The present invention discloses a double gate transistor and a method of fabricating said transistor, said transistor comprising: a semiconductor layer on a substrate; a fin structure formed in said semiconductor layer, said fin structure having two end portions for forming source and drain regions and a middle portion between said two end portions for forming a channel region, said middle portion including two opposed side surfaces perpendicular to a substrate surface; a first gate dielectric layer and a first gate disposed on one side surface of said middle portion; and a second gate dielectric layer and a second gate disposed on the other side surface of said middle portion.

Abstract: A method for fabricating metal gate transistor is disclosed. First, a substrate having a first transistor region and a second transistor region is provided. Next, a stacked film is formed on the substrate, in which the stacked film includes at least one high-k dielectric layer and a first metal layer. The stacked film is patterned to form a plurality of gates in the first transistor region and the second transistor region, a dielectric layer is formed on the gates, and a portion of the dielectric layer is planarized until reaching the top of each gates. The first metal layer is removed from the gate of the second transistor region, and a second metal layer is formed over the surface of the dielectric layer and each gate for forming a plurality of metal gates in the first transistor region and the second transistor region.

Abstract: Disclosed is a compound semiconductor device in which a first protective film, which is homogeneous and composed of a single material (SiN, in this case) and therefore has a uniform dielectric constant, continuously covers a compound semiconductor layer; an oxygen-containing protective component, which is a second protective film composed of an oxide film, is formed so as to cover one edge portion of an opening formed in the first protective film; and a gate electrode is formed so as to fill the opening and so as to embrace therein the second protective film.

Abstract: An embodiment of the invention provides a germanium-based NMOS device and a method for fabricating the same, which relates to fabrication process technology of an ultra-large-scale-integrated (ULSI) circuit. The germanium-based NMOS device has two dielectric layer interposed between a metal source/drain and a substrate. The bottom dielectric layer includes a dielectric material having a high pinning coefficient S such as hafnium oxide, silicon nitride, hafnium silicon oxide or the like, and the top dielectric layer includes a dielectric material having a low conduction band offset ?EC such as titanium oxide, gallium oxide, strontium titanium oxide or the like. According to the method, Fermi level pinning effect can be alleviated, electron barrier height can be lowered, and thus performance of the germanium-based Schottky NMOS device can be improved.

Abstract: A semiconductor device includes a substrate including a first region and a second region, a gate dielectric layer formed on the substrate, and a metal electrode layer formed on the gate dielectric layer and including a compound of carbon and nitrogen, wherein a metal electrode formed from the metal electrode layer in the first region has a work function lower than a work function of a metal electrode formed from the metal electrode layer in the second region and a nitrogen concentration of the metal electrode of the first region is smaller than a nitrogen concentration of the metal electrode of the second region.

Abstract: The invention relates to a gate stack structure suitable for use in a semiconductor flash memory device and its fabricating method. The gate stack structure is fabricated on a p-type 100 silicon substrate, which also includes the following components in sequence from bottom to top: a charge tunnel layer of Al2O3 film, the first charge trapping layer of RuOx nanocrystals; the second charge trapping layer of high-k HxAlyOz film, a charge blocking layer of Al2O3 film, and a top electrode. In this invention, the RuOx nanocrystals have excellent thermal stability, and do not diffuse easily at high temperatures. The high-k HfxAlyOz film has high density charge traps.Pd with a high work function is used as the top electrode. Therefore, the present gate stack structure has vast practical prospects for nanocrystal memory devices.

Abstract: Improved silicide formation and associated devices are disclosed. An exemplary method includes providing a semiconductor material having spaced source and drain regions therein, forming a gate structure interposed between the source and drain regions, performing a gate replacement process on the gate structure to form a metal gate electrode therein, forming a hard mask layer over the metal gate electrode, forming silicide layers on the respective source and drain regions in the semiconductor material, removing the hard mask layer to expose the metal gate electrode, and forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers.

Abstract: A semiconductor device has a source region, channel region, and drain region disposed in order from the surface of the device in the thickness direction of a semiconductor substrate. The device includes a source metal embedded in a source contact groove penetrating the source region and reaching the channel region, a gate insulating film formed on the side wall of a gate trench that is formed to penetrate the source region and channel and reach the drain region, a polysilicon gate embedded in trench so that at least a region facing the channel region in the insulating film is covered with the gate and so that the entire gate is placed under a surface of the source region, and a gate metal that is embedded in a gate contact groove formed in the gate so as to reach the depth of the channel region and in contact with the gate.

Abstract: Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly spaced disposable gate structures. A printable dielectric layer is deposited over the planarization dielectric layer to fill the gap-fill keyholes. Areas of the printable dielectric layer over the gap-fill keyholes are illuminated with radiation that cross-links cross-linkable bonds in the material of the printable dielectric layer. Non-crosslinked portions of the printable dielectric layer are subsequently removed selective to crosslinked portions of the printable dielectric layer, which fills at least the upper portion of each gate-fill keyhole. The disposable gate structures are removed to form gate cavities.