Abstract: A method for manufacturing a micro-electro-mechanical device, which has supporting parts and operative parts, includes providing a first semiconductor wafer, having a first layer of semiconductor material and a second layer of semiconductor material arranged on top of the first layer, forming first supporting parts and first operative parts of the device in the second layer, forming temporary anchors in the first layer, and bonding the first wafer to a second wafer, with the second layer facing the second wafer. After bonding the first wafer and the second wafer together, second supporting parts and second operative parts of said device are formed in the first layer. The temporary anchors are removed from the first layer to free the operative parts formed therein.

Abstract: A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch.

Abstract: A disclosed method of forming a mask pattern includes forming a first resist film on a film to be etched, opening portions on the first resist film at a predetermined pitch, a first film on the first resist film so as to cover sidewalls of the first opening portions, a second resist film, second opening portions alternately arranged with the first opening portions on the second resist film, and a second film on the second resist film so as to cover sidewalls of the second opening portions, and removing a part of the second film so that the second film is left as first sidewall portions, a part of the first resist film using the first sidewall portions as a mask to form third opening portions, and a part of the first film while leaving the first film as second sidewall portions to form fourth opening portions.

Abstract: A method for manufacturing a single crystal nano-structure includes providing a device layer with a 100 structure on a substrate; providing a stress layer onto the device layer; patterning the stress layer along the 110 direction of the device layer; selectively removing parts of the stress layer to obtain exposed parts of the device layer; plane dependent etching of the exposed parts of the device layer to obtain an exposed 111 faces of the device layer; thermally oxidizing the exposed 111 face of the device layer and forming a lateral oxidation layer at an interface of the device layer and the stress layer; providing a mask layer onto the oxidized exposed 111 face of the device layer; removing remaining parts of the stress layer to obtain further exposed parts of the device layer; removing the mask layer; plane dependent etching of the further exposed parts of the device layer to form a single crystal nano-structure with a triangular shaped cross section, until a side of the triangular shaped cross section

Abstract: A method of selective delivery of material to locations on a substrate using a continuous stream deposition device to deposit the material at selected locations on the substrate. This is achieved by creating a mask with an opening, locating the mask over the substrate and depositing the material through the opening onto the substrate. When locating the mask, over the substrate, a portion of the substrate is exposed through the opening and when the continuous stream deposition device is moved relative to the substrate and the mask, the continuous stream deposition device follows a path relative to the mask which intersects the opening. While the continuous stream deposition device moves, it discharges a continuous stream comprising the material to be delivered, to deposit the material through the mask at a discrete location on the substrate, at the intersection of the opening and the path of the continuous stream deposition device.

Abstract: Provided is a manufacturing method for a semiconductor device having reduced leakage current and increased capacitance while improving interface characteristics. The manufacturing method includes forming a silicon oxide layer on a base layer including silicon, forming a silicon oxynitride layer by implanting nitrogen into the silicon oxide layer, and forming hydroxy groups on a surface of the silicon oxynitride layer while etching the silicon oxynitride layer.

Abstract: A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer, such as Ta. Poly-Si is deposited on top of the metal gate layer.

Abstract: Forming a shallow trench capacitor in conjunction with an FET by forming a plurality of STI trenches; for the FET, implanting a first cell well having a first polarity between a first and a second of the STI trenches; for the capacitor, implanting a second cell well having a second polarity in an area of a third of the STI trenches; removing dielectric material from the third STI trench; forming a gate stack having a first portion located between the first and the second of the STI trenches and a second portion located over and extending into the third trench; and performing a source/drain implant of the same polarity as the second cell well, thereby forming a FET in the first cell well, and a capacitor in the second cell well. The second polarity may be opposite from the first polarity. An additional implant may reduce ESR in the second cell well.

Abstract: The present invention discloses a method for fabricating a semiconductor nano circular ring. In the method, firstly, a positive photoresist is coated on a semiconductor substrate, then the photoresist is exposed by using a circular mask with a micrometer-sized diameter to obtain the circular ring-shaped photoresist, based on the poisson diffraction principle. Then, a plasma etching is performed on the substrate under a protection of the circular ring-shaped photoresist to form a circular ring-shaped structure with a nano-sized wall thickness on a surface of the substrate. The embodiment of present invention fabricates a nano-sized circular ring-shaped structure by using a micrometer-sized lithography equipment and a micrometer-sized circular mask, and overcomes the dependence on advanced technologies, so as to effectively reduce the fabrication cost of the circular ring-shaped nano structure.

Abstract: The invention discloses a smoothing method to decrease bowing of group III nitride semiconductor substrate. The certain face of group III nitride semiconductor substrates is etched under the appropriate etching recipe and time, the certain morphology such as rod-type and other structures are appeared at the certain face. And such structures releases the compressive stresses at these certain faces, resulting in clearly increasing the bowing radius of the group III nitride semiconductor substrates, finally decreasing the bowing phenomenon of the group III nitride semiconductor substrate.

Abstract: There is provided a lithographic resist underlayer film-forming composition for forming a resist underlayer film which can be used as a hard mask. A lithographic resist underlayer film-forming composition including a silane compound having sulfonamide group, wherein the silane compound having sulfonamide group is a hydrolyzable organosilane having a sulfonamide group in the molecule, a hydrolyzate thereof, or a hydrolytic condensation product thereof. The composition including a silane compound having sulfonamide group and a silane compound lacking a sulfonamide group, wherein the silane compound having sulfonamide group is present within the silane compounds overall in a proportion of less than 1 mol %, for example 0.1 to 0.95 mol %.

Abstract: A method for fabricating a fine pattern includes forming a line-shaped partition pattern on an underlayer, adhering a first spacer to the sides of the partition pattern, dividing the first spacer into two line patterns where one line pattern has one end bent by selectively etching the first spacer portion with a division region, adhering a second spacer, which has a connection protrusion filling the division region and connecting to the partition pattern, to the outer side of the two line patterns, and selectively removing the two line patterns.

Abstract: There is disclosed A resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formulae (1-1) and/or (1-2), one or more kinds of a compound represented by the following general formula (2), and one or more kinds of a compound, represented by the following general formula (3), and/or an equivalent body thereof. There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, (namely, an underlayer film having optimum n-value and k-value as an antireflective film), excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same.

Abstract: A method of manufacturing a semiconductor device includes the steps of forming a semiconductor layer made of SiC on an SiC substrate, forming a film on the semiconductor layer, and forming a groove in the film. The semiconductor device including a chip having an interlayer insulating film includes a groove formed in the interlayer insulating film to cross the chip.

Abstract: Methods and hardware for generating variable-density plasmas are described. For example, in one embodiment, a process station comprises a showerhead including a showerhead electrode and a substrate holder including a mesa configured to support a substrate, wherein the substrate holder is disposed beneath the showerhead. The substrate holder includes an inner electrode disposed in an inner region of the substrate holder and an outer electrode being disposed in an outer region of the substrate holder. The process station further comprises a plasma generator configured to generate a plasma in a plasma region disposed between the showerhead and the substrate holder, and a controller configured to control the plasma generator, the inner electrode, the outer electrode, and the showerhead electrode to effect a greater plasma density in an outer portion of the plasma region than in an inner portion of the plasma region.

Abstract: Provided is a method of fabricating a semiconductor device. The method includes: preparing a substrate with an etching target, and etching the etching target through a plasma-free etching process that uses an etching gas including one of interhalogen compound, F2, XeF2 and combinations thereof.

Abstract: A method for forming a shallow trench isolation includes providing a substrate with a trench, a first liner layer and a second liner layer sequentially in the trench with a first oxide filling the trench, performing a first wet etching to remove part of the first oxide and part of the first liner layer to expose the substrate, performing a second wet etching to remove part of the second liner layer so that the second liner layer is lower than surface of the substrate, performing a third wet etching to remove part of the first oxide and part of the first liner layer, and filling the trench with a second oxide to form a shallow trench isolation.

Abstract: An inductively coupled plasma processing apparatus includes a processing chamber in which a semiconductor substrate is processed, a substrate support, a dielectric window forming a wall of the chamber, an antenna operable to generate and maintain a plasma in the processing chamber, and a showerhead plate of dielectric material adjacent the dielectric window. The showerhead plate includes gas holes in fluid communication with a plenum below the dielectric window, the plenum having a gas volume of no greater than 500 cm3. The gas holes extend between the plenum and a plasma exposed surface of the showerhead plate and the gas holes have an aspect ratio of at least 2. A gas delivery system is operable to supply an etching gas and a deposition gas into the processing chamber through the showerhead plate while the semiconductor substrate is supported on the substrate support.

Abstract: A method of forming patterns of a semiconductor device includes forming partition patterns on a hard mask layer; forming a first auxiliary layer on the entire structure including a surface of the partition patterns; forming auxiliary patterns to cover a portion of the first auxiliary layer formed over sidewalls of the partition pattern formed in second region, where each of the auxiliary patterns in the second region has a width greater than a thickness of the first auxiliary layer; forming spacers on sidewalls of the partition patterns, so that a portion of the partition patterns and a portion of the hard mask layer are exposed; removing the auxiliary patterns; etching the partition patterns exposed between the spacers; and removing remaining regions of the partition patterns and the hard mask layer exposed between the spacers.

Abstract: To provide a resist pattern improving material, containing: a compound represented by the following general formula (1), or a compound represented by the following general formula (2), or both thereof; and water: where R1 and R2 are each independently a hydrogen atom, or a C1-C3 alkyl group; m is an integer of 1 to 3; and n is an integer of 3 to 30, where p is an integer of 8 to 20; q is an integer of 3 to 30; and r is an integer of 1 to 8.

Abstract: A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The hardmask is removed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.

Abstract: A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.

Abstract: Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.

Abstract: A method of forming semiconductor memory device includes forming first to fourth spacers over a target layer including a first region and second regions adjacent to the first region so that a first spacer group including the first spacers spaced at a first interval is formed in the first region of the target layer, a second spacer group including the second spacers spaced at second intervals is formed in the second regions, a third spacer is formed between the first and the second spacer groups, and fourth spacers are formed between the third spacer and the first spacer group; forming an overlap pattern blocking the target layer; and forming first patterns, spaced at the first interval and each formed to have a first width, in the first region and second patterns, spaced at the second intervals and each formed to have a second width, in the second regions.

Abstract: The embodiments generally relate to methods of making semiconductor devices, and more particularly, to methods for making semiconductor pillar structures and increasing array feature pattern density using selective or directional gap fill. The technique has application to a variety of materials and can be applied to making monolithic two or three-dimensional memory arrays.

Abstract: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.

Abstract: A method for fabricating a via hole includes forming a first mask pattern on a first surface of a wafer exposing a portion of the first surface of the wafer, forming a passivation region within the wafer by implanting impurities into the exposed portion of the wafer using the first mask pattern as an ion implantation barrier layer, forming an etching stop layer on the first surface of the wafer including the passivation regions, forming a second mask pattern on a second surface of the wafer faces away from the first surface of the wafer, wherein the second mask pattern exposes a portion of the second surface of the wafer over an area between the passivation regions, and forming a via hole by etching the wafer using the second mask pattern as an etching mask.

Abstract: A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate.

Abstract: In a method of making a functionalized graphitic structure, a portion of a multi-layered graphene surface extending from a silicon carbide substrate is exposed to an acidic environment so as to separate graphene layers in a portion of the multi-layered graphene surface. The portion of the multi-layered graphene surface is exposed to a functionalizing material that binds to carbon atoms in the graphene sheets so that the functionalizing material remains between the graphene sheets, thereby generating a functionalized graphitic structure. The functionalized graphitic structure is dried in an inert environment.

Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.

Abstract: A nonvolatile semiconductor memory device includes a first region, a second region, and a plurality of word lines. The first region includes a plurality of electrically-rewritable memory transistors. The second region is located around the first region. The plurality of word lines are connected to the gates of the plurality of memory transistors respectively. The plurality of word lines includes interconnection portions and connection portions respectively. The interconnection portions extend in a first direction to head from the first region to the second region and are arrayed in a second direction orthogonal to the first direction with a first distance therebetween. The connection portions are extending from the interconnection portions, located in the second region, and electrically connected to contacts, respectively. The ends of the plurality of connection portions are formed along straight lines extending in the second direction.

Abstract: A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure position on a substrate. The first rectangular fin structure has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The structure additionally includes a second rectangular fin structure position on the substrate. Similarly, the second rectangular fin structure also has a bottom contacting the substrate, a top opposite the bottom, and sides between the top and the bottom. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and is positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure.

Abstract: A method for fabricating a fine pattern in a semiconductor device includes forming a first photoresist over a substrate where an etch target layer is formed, doping at least one impurity selected from group III elements and group V elements, of the periodic table, into the first photoresist, forming a photoresist pattern over the first photoresist, performing a dry etching process using the photoresist pattern to expose the first photoresist, etching the first photoresist by an oxygen-based dry etching to form a first photoresist pattern where a doped region is oxidized, and etching the etch target layer using the first photoresist pattern as an etch barrier.

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a top surface; a first insulation region and a second insulation region over the substrate top surface comprising tapered top surfaces; a fin of the substrate extending above the substrate top surface between the first and second insulation regions, wherein the fin comprises a recessed portion having a top surface lower than the tapered top surfaces of the first and second insulation regions, wherein the fin comprises a non-recessed portion having a top surface higher than the tapered top surfaces; and a gate stack over the non-recessed portion of the fin.

Abstract: By providing a protection layer for suppressing stress relaxation in a tensile-stressed dielectric material during a dual stress liner approach, performance of N-channel transistors may be increased, while nevertheless maintaining a high degree of compatibility with conventional dual stress liner approaches.

Abstract: A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on the plurality of features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the layer using the first feature, the filler feature and the second feature as a mask.

Abstract: The present method includes: forming a device isolation region in a substrate dividing the device isolation region into first and second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.

Abstract: A method for forming a semiconductor device includes forming a partition line pattern and a partition pad pattern connected to an end part of the partition line pattern over the semiconductor substrate. Spacer insulation layers are formed at sidewalls of the partition line pattern and the partition pad pattern. A gap-filling layer is formed between the spacer insulation layers. A first cutting mask pattern is formed to expose a connecting part between the partition line pattern and the partition pad pattern. The partition line pattern and the gap-filling layer adjacent to the spacer insulation layer are removed using the first cutting mask pattern as a mask. A second cutting mask pattern including a first pattern and a second pattern are formed. The spacer insulation layer is removed using the second cutting mask pattern as a mask to form a gate trench in the substrate.

Abstract: The disclosure relates to integrated circuit fabrication, and more particularly to a method for fabricating a semiconductor device. An exemplary method for fabricating the semiconductor device comprises providing a substrate; forming pad oxide layers over a frontside and a backside of the substrate; forming hardmask layers over the pad oxide layers on the frontside and the backside of the substrate; and thinning the hardmask layer over the pad oxide layer on the frontside of the substrate.

Abstract: A resist composition includes: a crosslinking material that is crosslinked in the presence of an acid; an acid amplifier; and a solvent.

Abstract: A resist lower layer film-forming composition includes (A) a polymer that includes a cyclic carbonate structure. The polymer (A) includes a structural unit (I) shown by the following formula (1).

Abstract: A semiconductor device 100 includes: a silicon substrate 102; a first gate 114a including a gate electrode 108 formed on the silicon substrate 102 and sidewalls 112 formed on the sidewalls of the gate electrode 108; a silicide layer 132 formed lateral to the sidewalls 112 of the first gate 114a on a surface of the silicon substrate 102; and a contact 164 which overlaps at least partially in plan view with the first gate 114a and reaches to the silicide layer 132 of the surface of the silicon substrate 102; wherein an insulator film is located between the contact 164 and the gate electrode 108 of the first gate 114a.

Abstract: Embodiments provide methods for etching and depositing silicon materials on a substrate. In one example, the method includes heating a substrate containing a silicon-containing material to a temperature of about 800° C. or less and removing a portion of the silicon-containing material and a contaminant to reveal an exposed surface of the silicon-containing material during an etching process and depositing a silicon-containing layer on the exposed surface of the silicon-containing material during a deposition process. The method further provides conducting the etching and deposition processes in the same chamber and utilizing chlorine gas and a silicon source gas during the etching and deposition processes. In some examples, the silicon-containing material is removed at a rate within a range from about 2 ? per minute to about 20 ? per minute during the etching process.

Abstract: Hot melt etch resist is selectively applied to an anti-reflective coating or a selective emitter on a semiconductor wafer. The exposed portions of the anti-reflective coating or selective emitter are etched away using an inorganic acid containing etch to expose the semiconductor surface. The hot melt etch resist is then stripped from the semiconductor with an alkaline stripper which does not compromise the electrical integrity of the semiconductor. The exposed semiconductor is then metalized to form current tracks.

Abstract: A naphthalene derivative having formula (1) is provided wherein An and Art denote a benzene or naphthalene ring, and n is such a natural number as to provide a weight average molecular weight of up to 100,000. A material comprising the naphthalene derivative or a polymer comprising the naphthalene derivative is spin coated to form a resist bottom layer having improved properties. A pattern forming process in which a resist bottom layer formed by spin coating is combined with an inorganic hard mask formed by CVD is available.

Abstract: A thermal infrared sensor includes an infrared ray absorbing film that is thermally separated from a semiconductor substrate by a hollow part; and a temperature sensor configured to detect temperature changes of the infrared ray absorbing film. The infrared ray absorbing film includes an infrared ray antireflection structure configured with a sub wavelength structure, the infrared ray antireflection structure being provided on a surface of the infrared ray absorbing film facing the semiconductor substrate.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes preparing an underlying structure; forming a protective film above the underlying structure; forming a trench into the protective film and the underlying structure; filling the trench with a fill material; planarizing the fill material such that the protective film is exposed; forming a sacrificial film above the fill material and the protective film; and reactive ion etching the sacrificial film and the fill material. The fill material is selectively etched back within the trench.

Abstract: Methods for depositing a material, such as a metal or a transition metal oxide, using an ALD (atomic layer deposition) process and resulting structures are disclosed. Such methods include treating a surface of a semiconductor structure periodically throughout the ALD process to regenerate a blocking material or to coat a blocking material that enables selective deposition of the material on a surface of a substrate. The surface treatment may reactivate a surface of the substrate toward the blocking material, may restore the blocking material after degradation occurs during the ALD process, and/or may coat the blocking material to prevent further degradation during the ALD process. For example, the surface treatment may be applied after performing one or more ALD cycles. Accordingly, the presently disclosed methods enable in situ restoration of blocking materials in ALD process that are generally incompatible with the blocking material and also enables selective deposition in recessed structures.

Abstract: The invention provides a composition for a resist underlayer film, the composition for a resist underlayer film to form a resist underlayer film of a multilayer resist film used in lithography, wherein the composition comprises at least (A) a fullerene derivative that is a reaction product of a substance having a fullerene skeleton with a 1,3-diene compound derivative having an electron-withdrawing group and (B) an organic solvent. There can be a composition for a resist underlayer film for a multilayer resist film used in lithography, the composition giving a resist underlayer film having excellent high dry etching resistance, capable of suppressing wiggling during substrate etching with high effectiveness, and capable of avoiding a poisoning problem in upperlayer patterning that uses a chemical amplification resist; a process for forming a resist underlayer film; a patterning process; and a fullerene derivative.

Abstract: There is provided to a pattern reversal film forming composition that is capable of forming a pattern reversal film which is not mixed with a resist pattern formed on a substrate, and that is only capable of forming a pattern reversal film advantageously covering the pattern, but also irrespective of whether the resist pattern is coarse or fine, capable of forming a planar film excellent in temporal stability on the pattern. A pattern reversal film forming composition including a polysiloxane, an additive and an organic solvent, characterized in that the polysiloxane is a product of a hydrolysis and/or condensation reaction of a silane compound containing a tetraalkoxysilane of Si(OR1)4 and an alkoxysilane of XnSi(OR2)4-n, and the tetraalkoxysilane is used in a ratio of 1 to 50% by mole based on the number of moles of the whole silane compound; and a pattern reversal film and a method of forming a reversed pattern in which the composition is used.