Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.

Abstract: A process for producing two interleaved patterns on a substrate uses photolithography and etching to produce, on the substrate, a first pattern of first material protruding regions separated by recessed regions. A non-conformal deposition of a second material on the first pattern forms cavities in the recessed regions of the first pattern. These cavities are opened and filled with a third material. The second material is then removed, and the remaining third material forms a second pattern of third material protruding regions, wherein the second pattern is interleaved with the first pattern.

Abstract: Methods are provided for forming an integrated circuit. In an embodiment, the method includes forming a sacrificial mandrel overlying a base substrate. Sidewall spacers are formed adjacent sidewalls of the sacrificial mandrel. The sidewall spacers have a lower portion that is proximal to the base substrate, and the lower portion has a substantially perpendicular outer surface relative to the base substrate. The sidewall spacers also have an upper portion that is spaced from the base substrate. The upper portion has a sloped outer surface. A first dielectric layer is formed overlying the base substrate and is conformal to at least a portion of the upper portion of the sidewall spacers. The upper portion of the sidewall spacers is removed after forming the first dielectric layer to form a recess having a re-entrant profile in the first dielectric layer. The re-entrant profile of the recess is straightened.

Abstract: A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.

Abstract: According to one embodiment, there is provided a semiconductor package manufacturing method utilizing a support body in which a first layer is stacked on a second layer, the method including: a first step of forming an opening in the first layer to expose the second layer therethrough; a second step of arranging a semiconductor chip on the second layer through the opening; a third step of forming a resin portion on the first layer to cover the semiconductor chip; and a fourth step of forming a wiring structure on the resin portion so as to be electrically connected to the semiconductor chip.

Abstract: Integrated circuit methods are described. The methods include providing a photomask that includes two main features for two via openings and further includes an optical proximity correction (OPC) feature linking the two main features; forming a hard mask layer on a substrate, the hard mask layer including two trench openings; forming a patterned resist layer over the hard mask layer using the photomask, wherein the patterned resist layer includes a peanut-shaped opening with two end portion aligned with the two trench openings of the hard mask layer, respectively; and performing a first etch process to the substrate using the hard mask layer and the patterned resist layer as a combined etch mask.

Abstract: A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film.

Abstract: A method for performing a spacer etch process is described. The method includes providing a gate structure on a substrate having a low-k spacer material conformally applied over the gate structure, and performing a spacer etch process sequence to partially remove the spacer material from the gate structure and the substrate, while retaining a sidewall spacer positioned along a sidewall of the gate structure. The spacer etch process sequence may include depositing a spacer protection layer on an exposed surface of said spacer material, and performing one or more etching processes to selectively and anisotropically remove the spacer protection layer and the spacer material to leave behind the sidewall spacer on the sidewall of the gate structure, wherein, while being partly or fully consumed by the one or more etching processes, the spacer protection layer exhibits a reduced variation in composition and/or dielectric constant.

Abstract: Substrates for solar cells are prepared by the reverse of the standard RCA clean. The substrates are first cleaned in RCA-2 solution and then in RCA-1 solution. A pyramids rounding step using HF/HNO3 solution is inserted between the two RCA clean procedures. This solves all the issues relating to surface contaminations and sharp areas. It also avoids the stain layer on the surface to some extent by RCA-1 treatment. A thin layer of amorphous or micro-crystalline intrinsic silicon may be deposited to passivate the surface.

Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.

Abstract: A method of photo-etching is proposed. The method includes steps as follows. Expose a photoresist layer with a stack of at least two masks. Each mask defines a corresponding pattern, and a new pattern is formed when the at least two masks are stacked. Process the exposed photoresist layer to derive a hollow-out structure that complements the new pattern. A mask system is also proposed. The adoption of the abovementioned method can lower the possibility of manufacturing new masks and reduce production costs.

Abstract: A method of forming a thin film transistor array panel includes: forming a first insulating layer on a substrate; forming an amorphous carbon layer on the first insulating layer; forming a second insulating layer on the amorphous carbon layer; forming an opening in the amorphous carbon layer by patterning the second insulating layer and the amorphous carbon layer; and forming a trench in the first insulating layer by etching the first insulating layer, the etching the first insulating layer using the amorphous carbon layer including the opening as a mask.

Abstract: One illustrative method disclosed herein includes forming a sacrificial mandrel above a structure, forming a plurality of first sidewall spacers on opposite sides of the sacrificial mandrel, removing the sacrificial mandrel, forming a plurality of second sidewall spacers on opposite sides of each of the first sidewall spacers, and removing the first sidewall spacers to thereby define a patterned spacer mask layer comprised of the plurality of second sidewall spacers.

Abstract: Vertical devices and methods of forming the same are provided. One example method of forming a vertical device can include forming a trench in a semiconductor structure, and partially filling the trench with an insulator material. A dielectric material is formed over the insulator material. The dielectric material is modified into a modified dielectric material having an etch rate greater than an etch rate of the insulator material. The modified dielectric material is removed from the trench via a wet etch.

Abstract: Self-aligned sextuple patterning (SASP) processes and mask design methods for the semiconductor manufacturing are invented. The inventions pertain to methods of forming one and/or two dimensional features on a substrate having the feature density increased to six times of what is possible using the standard optical lithographic technique; and methods to release the overlay requirement when patterning the critical layers of semiconductor devices. Our inventions provide production-worthy methods for the semiconductor industry to continue device scaling beyond 15 nm (half pitch).

Abstract: A method of forming semiconductor memory device includes forming first to fourth spacers over a target layer including a first region and second regions adjacent to the first region so that a first spacer group including the first spacers spaced at a first interval is formed in the first region of the target layer, a second spacer group including the second spacers spaced at second intervals is formed in the second regions, a third spacer is formed between the first and the second spacer groups, and fourth spacers are formed between the third spacer and the first spacer group; forming an overlap pattern blocking the target layer; and forming first patterns, spaced at the first interval and each formed to have a first width, in the first region and second patterns, spaced at the second intervals and each formed to have a second width, in the second regions.

Abstract: According to one embodiment, a pattern forming method is disclosed. A resist pattern having a top surface is formed pattern on a substrate. A coating film having a first thickness distribution is formed on the substrate. The coating film covers the resist pattern. The coating film is thinned to expose the top surface of the resist pattern. The first thickness distribution is changed into a second thickness distribution which is more uniform than the first thickness distribution. The resist pattern is removed without removing the coating film. A pattern is formed in the substrate by processing the substrate by using the coating film as a mask.

Abstract: A method of forming an integrated circuit (IC) includes forming a first and second plurality of spacers on a substrate, wherein the substrate includes a silicon layer, and wherein the first plurality of spacers have a thickness that is different from a thickness of the second plurality of spacers; and etching the silicon layer in the substrate using the first and second plurality of spacers as a mask, wherein the etched silicon layer forms a first plurality and a second plurality of fin field effect transistor (FINFET) channel regions, and wherein the first plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the first plurality of spacers, and wherein the second plurality of FINFET channel regions each have a respective thickness that corresponds to the thickness of the second plurality of spacers.

Abstract: A method for forming a self-aligned overlay mark is disclosed. First, a first region, a second region and a main feature which is disposed between the first region and the second region all disposed on the substrate are provided. The first region defines a first edge and the second region defines a second edge. Second, a cut mask layer is formed to respectively cover the first region and the second region to expose the main feature. Next, the cut mask layer is determined if it is self-aligned with the second edge or the first edge, and creates a self-aligned overlay mark. Later, a main feature etching step is carried out to transfer the main feature into the substrate when the cut mask layer is determined to be self-aligned with the second edge or the first edge.

Abstract: The present invention relates to a transistor and the method for forming the same. The transistor of the present invention comprises a semiconductor substrate; a gate dielectric layer formed on the semiconductor substrate; a gate formed on the gate dielectric layer; a source region and a drain region located in the semiconductor substrate and on respective sides of the gate, wherein at least one of the source region and the drain region comprises at least one dislocation; an epitaxial semiconductor layer containing silicon located on the source region and the drain region; and a metal silicide layer on the epitaxial semiconductor layer.

Abstract: Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening.

Abstract: A novel near-field EUV patterning technique and the corresponding imaging film stacks are invented for integrated-circuit manufacturing. This invention pertains to methods of forming one and/or two dimensional features on an EUV near-field imaging material with patterned light absorbers sitting on its top. These methods can be used to produce integrated circuits with a feature density higher than what is possible using conventional EUV or optical DUV lithography.

Abstract: Some embodiments include methods in which photolithographically-patterned photoresist features are used as templates during formation of a series of annular structures. The annular structures have linear segments. The linear segments are within a pattern having a pitch which is less than or equal to about half of a pitch of a pattern containing the photoresist features. An expanse of photoresist is formed across the annular structures. The expanse is photolithographically patterned to form chop patterns over ends of the annular structures, and to form at least one opening over at least one of the linear segments. The annular structures are etched while using the patterned photoresist expanse as a mask. In some embodiments, an opening in a photoresist expanse aligns to an edge of a linear segment through scum generated during photolithographic patterning of the photoresist expanse.

Abstract: A method of forming a plurality of spaced features includes forming sacrificial hardmask material over underlying material. The sacrificial hardmask material has at least two layers of different composition. Portions of the sacrificial hardmask material are removed to form a mask over the underlying material. Individual features of the mask have at least two layers of different composition, with one of the layers of each of the individual features having a tensile intrinsic stress of at least 400.0 MPa. The individual features have a total tensile intrinsic stress greater than 0.0 MPa. The mask is used while etching into the underlying material to form a plurality of spaced features comprising the underlying material. Other implementations are disclosed.

Abstract: Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed.

Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.

Abstract: The present invention relates to a method of manufacturing sidewall spacers on a memory device. The method comprises forming sidewall spacers on a memory device having a memory array region and at least one peripheral circuit region by forming a first sidewall spacer adjacent to a word line in the memory array region and a second sidewall spacer adjacent to a transistor in the peripheral circuit region. The first sidewall spacer has a first thickness and the second sidewall spacer has a second thickness, wherein the second thickness is greater than the first thickness.

Abstract: A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.

Abstract: A method of patterning a material layer of a semiconductor device is disclosed, the method including treating a material layer above a semiconductor substrate with plasma oxygen; depositing a layer of photoresist over a first surface of the material layer after the treating of the material layer; patterning the layer of photoresist, thereby forming a patterned photoresist, exposing portions of the material layer; etching the exposed portions of at least the material layer to form at least one contact via in the material layer extending to a source or drain region of a device at a surface of the substrate; and removing the patterned photoresist from the first surface of the material layer.

Abstract: A method of taper-etching a layer to be etched that is made of SiO2 or SiON and has a top surface. The method includes the step of forming an etching mask with an opening on the top surface of the layer to be etched, and the step of taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces that intersect at a predetermined angle is formed in the layer to be etched. The etching mask is formed of a material containing elemental Al. The step of taper-etching employs an etching gas that contains a main component gas, which contributes to the etching of the layer to be etched, and N2.

Abstract: The present invention relates to a method for producing a thin single crystal silicon having large surface area, and particularly relates to a method for producing a silicon micro and nanostructure on a silicon substrate (or wafer) and lifting off the silicon micro and nanostructure from the silicon substrate (or wafer) by metal-assisted etching. In this method, a thin single crystal silicon is produced in the simple processes of lifting off and transferring the silicon micro and nanostructure from the substrate by steps of depositing metal catalyst on the silicon wafer, vertically etching the substrate, laterally etching the substrate. And then, the surface of the substrate is processed, for example planarizing the surface of the substrate, to recycle the substrate for repeatedly producing thin single crystal silicons. Therefore, the substrate can be fully utilized, the purpose of decreasing the cost can be achieved and the application can be increased.

Abstract: In sophisticated semiconductor devices, replacement gate approaches may be applied in combination with a process strategy for implementing a strain-inducing semiconductor material, wherein superior proximity of the strain-inducing semiconductor material and/or superior robustness of the replacement gate approach may be achieved by forming the initial gate electrode structures with superior uniformity and providing at least one cavity for implementing the strained channel regions in a very advanced manufacturing stage, i.e., after completing the basic transistor configuration.

Abstract: Some embodiments relate to a method for processing a workpiece. In the method, a first photoresist layer is provided over the workpiece, wherein the first photoresist layer has a first photoresist tone. The first photoresist layer is patterned to provide a first opening exposing a first portion of the workpiece. A second photoresist layer is then provided over the patterned first photoresist layer, wherein the second photoresist layer has a second photoresist tone opposite the first photoresist tone. The second photoresist layer is then patterned to provide a second opening that at least partially overlaps the first opening to define a coincidentally exposed workpiece region. A treatment is then performed on the coincidentally exposed workpiece region. Other embodiments are also disclosed.

Abstract: A patterning method is provided for fabrication of a semiconductor device structure having conductive contact elements, an interlayer dielectric material overlying the contact elements, an organic planarization layer overlying the interlayer dielectric material, an antireflective coating material overlying the organic planarization layer, and a photoresist material overlying the antireflective coating material. The method creates a patterned photoresist layer from the photoresist material to define oversized openings corresponding to respective conductive contact elements. The antireflective coating is etched using the patterned photoresist as an etch mask. A liner material is deposited overlying the patterned antireflective coating layer. The liner material is etched to create sidewall features, which are used as a portion of an etch mask to form contact recesses for the conductive contact elements.

Abstract: A wafer-level package structure of a light emitting diode and a manufacturing method thereof, and the package structure includes: a die including a first side and a second side opposite to the first side; a first insulating layer on the first side of the die; at least two wires which are arranged on the insulating layer and electrically isolated from each other; bumps which are arranged on the wires and adapted to be electrically connected correspondingly with electrodes of a bare chip of the light emitting diode; at least two discrete lead areas on the second side of the die; and leads in the lead areas, electrically isolated from each other and electrically connected correspondingly with the wires.

Abstract: A method and apparatus are described for forming a first inter-layer dielectric (ILD0) stack having a protective gettering layer (72) with a substantially uniform thickness. After forming device components (32, 33) on a substrate (31), a gap fill dielectric layer of SATEOS (52) is deposited over an etch stop layer of PEN ESL (42) and then planarized before sequentially depositing a gettering layer of BPTEOS (72) and capping dielectric layer (82) on the planarized gap fill dielectric layer (52). Once the ILD0 stack is formed, one or more contact openings (92, 94, 96) are etched through the ILD0 stack, thereby exposing the etch stop layer (42) over the intended contact regions.

Abstract: A method of fabricating a miniaturized semiconductor or other such device takes advantage of a self-reorganization characteristic of an in-situ dissociable diblock copolymer to form a circular via hole that is centrally disposed relative to other device features. In one embodiment, the method is used to form a dual damascene structure. During formation of the dual damascene structure, due to the self-reorganization characteristics of the monomer constituents of the diblock copolymer, the position of the via hole can be ensured to be self aligned with the position of the trench, thus improving the performance and yield of the so formed semiconductor devices, and lowering fabrication costs.

Abstract: In a method of forming a pattern, a first mask layer and a first sacrificial layer may be sequentially formed on an object layer. The first sacrificial layer may be partially etched to form a first sacrificial layer pattern. A second sacrificial layer pattern may be formed on the first mask layer. The second sacrificial layer pattern may enclose a sidewall of the first sacrificial layer pattern. The first sacrificial layer pattern may then be removed. The first mask layer may be partially etched using the second sacrificial layer pattern as an etching mask to form a first mask layer pattern. The object layer may be partially etched using the first mask layer pattern as an etching mask.

Abstract: Disclosed herein is a resist stripping composition, which has an excellent ability of stripping a residual resist remaining after dry or wet etching at the tune of forming patterns in a process of manufacturing a flat panel display substrate.

Abstract: A method of forming a reverse image pattern on a semiconductor base layer is disclosed. The method comprises depositing a transfer layer of amorphous carbon on the semiconductor base layer, depositing a resist layer on the transfer layer, creating a first pattern in the resist layer, creating the first pattern in the transfer layer, removing the resist layer, depositing a reverse mask layer, planarizing the reverse mask layer, and removing the transfer layer, thus forming a second pattern that is a reverse image of the first pattern.

Abstract: An object is to provide a semiconductor device with a novel structure and favorable characteristics. A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.

Abstract: A novel process technique and mask design based on the optimized self-aligned triple patterning are invented for the semiconductor manufacturing. This invention pertains to methods of forming one and/or two dimensional features on a substrate having the feature density increased to three times of what is possible using optical lithography, and methods to release the overlay requirement when patterning the critical layers of semiconductor devices.

Abstract: According to one embodiment, a design method of layout formed by a sidewall method is provided. The method includes: preparing a base pattern on which a plurality of first patterns extending in a first direction and arranged at a first space in a second direction intersecting the first direction and a plurality of second patterns extending in the first direction and arranged at a center between the first patterns, respectively, are provided; and drawing a connecting portion which extends in the second direction and connects two neighboring first patterns sandwiching one of the second patterns, and separating the one of the second patterns into two patterns not contacting the connecting portion.

Abstract: System and method for implementing multi-resolution advanced process control (“APC”) are described. One embodiment is a method including obtaining low resolution metrology data and high resolution metrology data related to a process module for performing a process on the wafer. A process variable of the process is modeled as a function of the low resolution metrology data to generate a low-resolution process model and the process variable is modeled as a function of the high resolution metrology data to generate a high-resolution process model.

Abstract: A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.

Abstract: A method of suppressing the etch rate for exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. The etch selectivity of silicon relative to silicon nitride and other silicon-and-nitrogen-containing material is increased using the method. The first stage of the remote plasma etch reacts plasma effluents with the patterned heterogeneous structures to form protective solid by-product on the silicon-and-nitrogen-containing material. The plasma effluents of the first stage are formed from a remote plasma of a combination of precursors, including nitrogen trifluoride and hydrogen (H2). The second stage of the remote plasma etch also reacts plasma effluents with the patterned heterogeneous structures to selectively remove material which lacks the protective solid by-product. The plasma effluents of the second stage are formed from a remote plasma of a fluorine-containing precursor.

Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.

Abstract: Provided is a semiconductor device manufacturing method enabling miniaturization by forming a hole in a vertical shape, capable of reducing the number of processes as compared to conventional methods, and capable of increasing productivity. The semiconductor device manufacturing method includes: forming a hole in a substrate; forming a polyimide film within the hole; isotropically etching the substrate without using a mask covering a sidewall portion of the polyimide film within the hole and removing at least a part of a bottom portion of the polyimide film within the hole while the sidewall portion of the polyimide film remains within the hole; and filling the hole with a conductive metal.

Abstract: Semiconductor substrates with high aspect ratio recesses formed therein are described. The high aspect ratio recesses have bottom surface profile characteristics that promote formation of initial growth sites of plated metal as compared to the side surfaces of the recesses. Processes for making and plating the recesses are also disclosed. The metal-plated high aspect ratio recesses can be used as X-ray gratings in Phase Contrast X-ray imaging apparatuses.

Abstract: In a substrate processing apparatus (1), a silicon oxide film on a main surface of a substrate (9) is removed in an oxide film removing part (4) and then a silylation material is applied to the main surface, to thereby perform a silylation process in a silylation part (6). It is thereby possible to lengthen the Q time from the removal of the silicon oxide film to the formation of the silicon germanium film and reduce the temperature for prebaking in the formation of the silicon germanium film.