Abstract: A manufacturing method for a micromechanical semiconductor element includes providing on a semiconductor substrate a patterned stabilizing element having at least one opening. The opening is arranged such that it allows access to a first region in the semiconductor substrate, the first region having a first doping. Furthermore, a selective removal of at least a portion of the semiconductor material having the first doping out of the first region of the semiconductor substrate is provided. In addition, a membrane is produced above the first region using a first epitaxy layer applied on the stabilizing element. In a further method step, at least a portion of the first region is used to produce a cavity underneath the stabilizing element. In this manner, the present invention provides for the production of the patterned stabilizing element by means of a second epitaxy layer, which is applied on the semiconductor substrate.

Abstract: Vertical integrated MEMS switches, design structures and methods of fabricating such vertical switches is provided herein. The method of manufacturing a MEMS switch, includes forming at least two vertically extending vias in a wafer and filling the at least two vertically extending vias with a metal to form at least two vertically extending wires. The method further includes opening a void in the wafer from a bottom side such that at least one of the vertically extending wires is moveable within the void.

Abstract: A photovoltaic cell and a method of forming an electrode grid on a photovoltaic semiconductor substrate of a photovoltaic cell are disclosed. In one embodiment, the photovoltaic cell comprises a photovoltaic semiconductor substrate; a back electrode electrically connected to a back surface of the substrate; and a front electrode electrically connected to a front surface of the substrate. The substrate, back electrode, and front electrode form an electric circuit for generating an electric current when said substrate absorbs light. The front electrode is comprised of a metal grid defining a multitude of holes. These holes may be periodic, aperiodic, or partially periodic. The front electrode may be formed by depositing nanospheres on the substrate; forming a metallic layer on the substrate, around the nanospheres; and removing the nanospheres, leaving an electrode grid defining a multitude of holes on the substrate.

Abstract: Embodiments of the present invention generally provide methods for forming conductive structures on the surfaces of a solar cell. In one embodiment, conductive structures are formed on the front surface of a solar cell by depositing a sacrificial polymer layer, forming patterned lines in the sacrificial polymer via a fluid jet, depositing metal layers over the front surface of the solar cell, and performing lift off of the metal layers deposited over the sacrificial polymer by dissolving the sacrificial polymer with a water based solvent.

Abstract: A method of forming patterns of a semiconductor device includes forming a hard mask layer and a first sacrificial layer over a first region and a second region of a semiconductor substrate, etching the first sacrificial layer to form a first sacrificial pattern having a first width in the first region and second sacrificial patterns having a second width in the second region, wherein the second width is narrower than the first width, forming a first spacer surrounding sidewalls of the first sacrificial pattern and a second spacer surrounding sidewalls of the second sacrificial patterns, removing the first and the second sacrificial patterns; and etching the first and second spacers.

Abstract: A method for forming a floating heater element includes processing a silicon substrate to form a heater stack having the heater element on the substrate with peripheral edge portions, processing the heater stack by depositing and patterning a layer of photoresist or hard mask thereon to substantially mask the heater stack and form a trench through the photoresist or hard mask exposing a surface area of the substrate extending along the peripheral edge portions of the heater element, and processing the masked heater stack and exposed surface area of the substrate by sequentially removing the photoresist and portions of the substrate at the exposed surface area and that underlie the heater element so as to create a well in the substrate undercutting the heater element and open along the peripheral edge portions thereof, the well being capable of filling with a fluid so as to produce the floating heater element.

Abstract: A method of fabricating a self-aligned contact pad (SAC) includes forming stacks of a conductive line and a capping layer on a semiconductor substrate, spacers covering sidewalls of the stacks, and an insulation layer filling gaps between the stacks and exposing the top of the capping layer, etching the capping layer to form damascene grooves, forming a plurality of first etching masks with a material different from that of the capping layer to fill the damascene grooves without covering the top of the insulation layer, and forming a second etching mask having an opening region that exposes some of the first etching masks and a portion of the insulation layer located between the first etching masks.

Abstract: Disclosed is a patterning method including: forming, on a thin film, a sacrificial film made of a material different from that of the thin film and made of SiBN; processing the sacrificial film into a pattern having a preset interval by using a photolithography technique; forming, on sidewalls of the processed sacrificial film, sidewall spacers made of a material different from those of the sacrificial film and the thin film; removing the processed sacrificial film; and processing the thin film by using the sidewall spacers as a mask.

Abstract: A method for forming an RuOx electrode comprising depositing a TiW layer on an RuOx layer, forming a photo-resist mask on the TiW layer, in order to mask the TiW layer into a masked TiW layer, etching the masked TiW layer with a CF4 plasma, a TiW mask being formed on the RuOx layer, the CF4 plasma is not etching the RuOx and vaporizing unmasked RuOx portion of the RuOx layer with an oxygen plasma, the masked RuOx layer being formed into an RuOx electrode.

Abstract: In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer.

Abstract: An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost.

Abstract: A method of manufacturing a redistribution circuit structure is provided. First, a substrate is provided. The substrate has a plurality of pads and a passivation layer. The passivation layer has a plurality of first openings exposing a portion of each of the pads, respectively. A first patterned photoresist layer is formed on the passivation layer. The first patterned photoresist layer has a plurality of second openings exposing a portion of each of the pads. A plurality of first bumps is formed in the second openings, respectively. An under ball metal (UBM) material layer is formed over the substrate to cover the first patterned photoresist layer and the first bumps. A plurality of conductive lines is formed on the UBM material layer. The UBM material layer is patterned to form a plurality of UBM layers using the conductive lines as a mask.

Abstract: A method of fabricating a non-volatile memory device, wherein a gate insulating layer, a first conductive layer, a tunneling layer, a trap nitride layer, a blocking oxide layer, and a capping layer are sequentially formed over a semiconductor substrate of a peripheral region. A contact region of the capping layer is etched. A spacer is formed on sidewalls of the capping layer. A contact region of the blocking oxide layer is etched by using the spacer as a mask. The spacer is removed while etching a contact region of the trap nitride layer. A contact region of the tunneling layer is etched.

Abstract: The present invention relates to a method of forming a phase changeable structure wherein an upper electrode is formed on a phase changeable layer. A material including fluorine can be provided to the phase changeable layer and the upper electrode. The phase changeable layer can be etched to form a phase changeable pattern. Oxygen plasma or water vapor plasma can then be provided to the upper electrode and the phase changeable pattern.

Abstract: A method for fabricating a semiconductor device, including forming a dielectric film above a substrate; forming a metal containing film above the dielectric film; forming at least one carbon containing film of a silicon carbon containing film containing silicon and carbon and a nitrogen carbon containing film containing nitrogen and carbon above the metal containing film; etching the carbon containing film selectively; etching the metal containing film selectively to transfer an opening of the carbon containing film formed by etching; and etching the dielectric film using the carbon containing film and the metal containing film as masks in a state in which a surface of the carbon containing film other than the opening is exposed.

Abstract: A method for fabricating a semiconductor device includes forming a plurality of gate patterns including a tungsten electrode over a substrate, performing a plasma oxidation process to form a capping layer on the surfaces of the gate patterns, forming an etch barrier layer over the substrate where the capping layer is formed, forming an interlayer dielectric layer to fill gap between the gate patterns, and etching the interlayer dielectric layer between the gate patterns to form a contact hole.

Abstract: Provided is a method of fabricating a semiconductor device with a dual damascene pattern. According to the method, a diffusion barrier layer, dielectric, a capping layer, and an organic bottom anti-reflection coating (BARC) are sequentially formed on a substrate where a metal interconnection is formed. A photoresist pattern on the organic BARC is formed and the organic BARC, the capping layer, and the dielectric are selectively etched to form a trench using the photoresist pattern as a mask. The photoresist pattern and the organic BARC are removed, and a byproduct capping mask is formed by reacting the capping layer with a reaction gas to form a byproduct. A portion of the trench is filled with the byproduct. Then, a via hole is formed in the trench using the byproduct capping mask as a mask, and the byproduct capping mask, the diffusion barrier layer, and the capping layer are removed.

Abstract: A manufacturing method for a micromechanical semiconductor element includes providing on a semiconductor substrate a patterned stabilizing element having at least one opening. The opening is arranged such that it allows access to a first region in the semiconductor substrate, the first region having a first doping. Furthermore, a selective removal of at least a portion of the semiconductor material having the first doping out of the first region of the semiconductor substrate is provided. In addition, a membrane is produced above the first region using a first epitaxy layer applied on the stabilizing element. In a further method step, at least a portion of the first region is used to produce a cavity underneath the stabilizing element. In this manner, the present invention provides for the production of the patterned stabilizing element by means of a second epitaxy layer, which is applied on the semiconductor substrate.

Abstract: A method of making nanowires includes providing a silicon substrate having a silicon dioxide insulation on the surface thereof. The silicon dioxide is etched to form one or more pillars, each having a plurality of sidewalls. A thin film of gold is deposited on a sidewall and is subjected to an annealing process. The annealing process causes the gold film to form a globular catalyst particle. The structure is placed in an LPCVD furnace into which is introduced silane gas. Silicon from the gas migrates through the catalyst particle and grows a nanowire from the sidewall of the pillar to a desired length. Electrical contacts are provided at each end of the nanowire to create an active component useable in an electronic circuit.

Abstract: A method of fabricating a liquid crystal display array substrate includes forming a gate wiring line having a gate pad electrode, forming a data wiring line having a data pad electrode, forming a protection layer over the gate pad electrode and the data pad electrode, and positioning etching tapes on the protection layer over the gate pad electrode and the data pad electrode.

Abstract: A manufacturing method for a micromechanical semiconductor element includes providing on a semiconductor substrate a patterned stabilizing element having at least one opening. The opening is arranged such that it allows access to a first region in the semiconductor substrate, the first region having a first doping. Furthermore, a selective removal of at least a portion of the semiconductor material having the first doping out of the first region of the semiconductor substrate is provided. In addition, a membrane is produced above the first region using a first epitaxy layer applied on the stabilizing element. In a further method step, at least a portion of the first region is used to produce a cavity underneath the stabilizing element. In this manner, the present invention provides for the production of the patterned stabilizing element by means of a second epitaxy layer, which is applied on the semiconductor substrate.

Abstract: A substrate processing method includes: performing an etching process to form a predetermined pattern on an etching-target film disposed on a substrate; denaturing a substance remaining after the etching process to be soluble in a predetermined liquid; then, performing a silylation process on a surface of the etching-target film having the pattern formed thereon; and then, supplying the predetermined liquid to dissolve and remove the denatured substance.

Abstract: An etching solution for a multiple layer of copper and molybdenum includes: about 5% to about 30% by weight of a hydrogen peroxide; about 0.5% to about 5% by weight of an organic acid; about 0.2% to about 5% by weight of a phosphate; about 0.2% to about 5% by weight of a first additive having nitrogen; about 0.2% to about 5% by weight of a second additive having nitrogen; about 0.01% to about 1.0% by weight of a fluoric compound; and de-ionized water making a total amount of the etching solution 100% by weight.

Abstract: To remove the disparate substrate from nitride semiconductor layer grown over the disparate substrate, that is made of a material different from nitride semiconductor, by irradiating the disparate substrate with laser beam having a wavelength shorter than the band gap wavelength of the nitride semiconductor layer, while supplying an acidic or alkaline etching solution to the interface between the disparate substrate and the nitride semiconductor layer.

Abstract: A pair of comb-teeth electrodes are made from a material substrate including a first conduction layer, a second conduction layer and an intervening insulation layer. The paired electrodes includes first and second comb-teeth electrodes. The first comb-teeth electrode is composed of a first conductor derived from the first conduction layer, a second conductor derived from the second conduction layer and an insulator derived from the insulation layer. The second comb-teeth electrode is derived from the second conduction layer.

Abstract: A method of manufacturing a through conductor that penetrates from an upper surface of a silicon substrate to its lower surface. The through conductor is manufactured in steps which provide a first conductor which extends in the direction of thickness of the silicon substrate from the upper surface of the silicon substrate, and a second conductor which has a size in the direction orthogonal to the thickness direction is smaller than that of the first conductor and which penetrates the silicon substrate from a bottom face of the first conductor to the lower surface of the silicon substrate.

Abstract: An object of the present invention is to provide a method for manufacturing a display device with few steps and high yield. One feature of the invention is to form a first mask pattern having low wettability over a conductive layer, form a second mask pattern having high wettability over the conductive layer using the first mask pattern as a mask, and form a mask pattern for etching the conductive layer by removing the first mask pattern. Another feature is to form a pixel electrode by etching the conductive layer.

Abstract: The present invention relates to a method for the patterning of a stack of layers on a surface with high topography. A method of the present invention can be used for gate patterning for multiple Gate FETs (MuGFETs), for patterning of the control gate in non-volatile memory applications, and for the patterning of the poly emitter in BiCMOS devices. The present invention also relates to a device prepared by a method of the invention.

Abstract: An imprinting apparatus and method of fabrication provide a mold having a pattern for imprinting. The apparatus includes a semiconductor substrate polished in a [110] direction. The semiconductor substrate has a (110) horizontal planar surface and vertical sidewalls of a wet chemical etched trench. The sidewalls are aligned with and therefore are (111) vertical lattice planes of the semiconductor substrate. The semiconductor substrate includes a plurality of vertical structures between the sidewalls, wherein the vertical structures may be nano-scale spaced apart. The method includes wet etching a trench with spaced apart (111) vertical sidewalls in an exposed portion of the (110) horizontal surface of the semiconductor substrate along (111) vertical lattice planes. A chemical etching solution is used that etches the (111) vertical lattice planes slower than the (110) horizontal lattice plane. The method further includes forming the imprinting mold.

Abstract: Methods for fabricating devices having small feature sizes are provided. In an exemplary embodiment, a method comprises forming a patterned first mask layer overlying a subject material layer and isotropically etching the patterned first mask layer. A second masking layer is deposited overlying the patterned first mask layer and the isotropically-etched patterned first mask layer is exposed. The isotropically-etched patterned first mask layer is removed and the subject material layer is etched to form a feature therein.

Abstract: Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a terminal and a dielectric layer to at least an intermediate depth in a substrate of a workpiece. The hole has a first lateral dimension in the dielectric layer and a second lateral dimension in the substrate proximate to an interface between the dielectric layer and the substrate. The second lateral dimension is greater than the first lateral dimension. The method further includes constructing an electrically conductive interconnect in at least a portion of the hole and in electrical contact with the terminal.

Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, and a plurality of rows of active regions in the substrate, the active regions arranged in a staggered pattern such that active regions of a first row are aligned with portions of an isolation region separating active regions of an adjacent second row. Source and drain regions are in the active regions and are arranged such that each active region comprises a drain region disposed between two source regions. A plurality of word line structures are on the substrate, arranged transverse to the rows of active regions such that that word line structures cross the active regions between the source regions and the drain regions. Respective rows of conductive pads are disposed between respective adjacent word lines structures, including first conductive pads on the source regions, second conductive pads on the drain regions, and third conductive on isolation regions separating active regions.

Abstract: A method of using carbon spacers for critical dimension reduction can include providing a patterned photoresist layer above a substrate where the patterned photoresist layer has an aperture with a first width, depositing a carbon film over the photoresist layer and etching the deposited carbon film to form spacers on lateral side walls of the aperture of the patterned photoresist layer, etching the substrate using the formed spacers and patterned photoresist layer as a pattern to form a trench having a second width, and removing the patterned photoresist layer and formed spacers using an oxidizing etch.

Abstract: In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.

Abstract: A method for fabricating semiconductor components such as printed circuit boards, multi chip modules, chip scale packages, and test carriers is provided. The method includes providing a substrate having a blanket deposited conductive layer thereon. Using a laser machining process, grooves are formed in the conductive layer to define patterns of conductors on the substrate. The conductors can be formed with a desired size and spacing, and can include features such as bond pads, conductive vias, and external ball contacts. In addition, selected conductors can be configured as co-planar ground or voltage traces, for adjusting impedance values in other conductors configured as signal traces.