Abstract: A power supply for an integrated circuit has a piecewise linear operating characteristic for improved integrated circuit testing and screening. In an integrated circuit that receives an externally applied power signal, designated V.sub.CCX, and includes a power supply for generating an internal operating voltage, designated V.sub.CCR, an on-chip power supply circuit provides V.sub.CCR as a piecewise linear function of V.sub.CCX. In a first segment of such a function, V.sub.CCR approximates V.sub.CCX for efficient low voltage operations. In a second segment, used for normal operations of the integrated circuit, V.sub.CCR rises gradually with V.sub.CCX so that test results at the edges of the segment can be guaranteed with a margin for measurement tolerance, process variation, and derating. In a third segment, V.sub.CCR follows below V.sub.CCX at a predetermined constant offset. Transitions between segments are smooth due to nonlinear devices used in the power supply circuitry.

Abstract: A semiconductor device comprises: a signal of high voltage not less than the power voltage; a first transistor for transmitting the high voltage signal; a second transistor for electrically charging and discharging the gate potential of the first transistor; and a circuit for generating a pulse signal of which "H" level is a voltage higher than the power voltage by the threshold voltage of the second transistor. The pulse signal generating circuit is connected to the gate electrode of the second transistor. This cancels the drop of a voltage corresponding to the threshold voltage generated at the time when the electric charge is transferred to the gate electrode of the first transistor. Accordingly, even though the power voltage is low, a high voltage signal can be transferred through the first transistor and the word line potential can be boosted to a voltage not less than the power voltage.

Abstract: A power efficient transistor (11) which operates in or near saturation having a base (16), a collector (17), and an emitter (18). A first transistor (12) having a base, collector, and emitter coupled to the base (16), collector (17), and emitter (18) of the transistor (11). The first transistor (12) is biased to operate in or near saturation under quiescent conditions. A plurality of transistors (13) are incrementally enabled or disabled to maintain the transistor (11) in or near saturation under all operating conditions. Each of the transistors (13) have a base, collector, and emitter coupled to the base (16), collector (17), and emitter (18) of the transistor (11). A plurality of drive transistors (14), enable or disable a corresponding one of each transistor of the transistors (13). Each drive transistor of the drive transistors (14) is enabled at a different voltage thereby incrementally enabling and disabling each transistor of transistors (13) maintaining transistor 11 in or near saturation.

Abstract: A voltage regulation circuit that includes a sample and hold circuit for sampling an input voltage and for holding a reference voltage generated in response to the input voltage. The sample and hold circuit includes a capacitor that holds the reference voltage. The voltage regulation circuit also includes a regulator circuit coupled to the capacitor of the sample and hold circuit. The regulator circuit outputs an output voltage using the reference voltage supplied by the capacitor. The voltage regulation circuit may be used to provide a high precision programming voltage for programming memory cells having two or more analog states.

Abstract: A drive circuit includes a voltage source supplying a reference voltage at its output; a voltage elevating circuit connected to a supply voltage and to the output of the voltage source, and supplying at its output, under normal operating conditions, a drive voltage greater than the supply voltage and increasing with the reference voltage. The input of the voltage source is connected to the output of the voltage elevating circuit, and defines a positive feedback path resulting in an increase in the reference voltage corresponding to an increase in the drive voltage, and therefore results in a corresponding increase in the drive voltage up to a maximum permissible value, thus providing for a sufficient drive voltage for driving the gate-source junction of power MOS transistors, even in the presence of a low supply voltage.

Abstract: A circuit and method for reducing a gate voltage of a transmission gate to prevent overvoltage that could damage or affect reliability of the transmission gate. The transmission gate resides in a charge pump circuit (41) coupled to a capacitor for generating a voltage greater than a power supply voltage. A buffer (44,45) receives a control signal and couples to a gate terminal of the transmission gate. The buffer (44,45) includes a power supply terminal that is coupled to a variable voltage reference (43). The variable voltage reference (43) provides a voltage that reduces the gate voltage of the transmission gate when an output voltage of the charge pump circuit reaches a predetermined voltage. The variable voltage reference (43) reduces a voltage range between logic levels provided by the buffer (44,45) to protect the transmission gate from an excessive voltage.

Abstract: A system and method for detecting the voltage level of a power supply signal and generating a notification signal to indicate when the supply voltage exceeds a minimum voltage that is programmable by a user. A programming signal, that allows for multiple voltages to be detected, is applied to the voltage detection system to generate a notification signal in response to the supply voltage attaining the minimum voltage indicated by the programming signal.

Abstract: A stress mode circuit is provided to generate a voltage that is either equal to a reference voltage or is a proportion of an external voltage (VCCEXT). The circuit includes two voltage divider circuits to provide the proportion voltage. Two differential amplifiers are provided to generate outputs corresponding to a comparison to the proportion voltage and the reference voltage. The outputs operate switches that couple the reference voltage or the proportion voltage to an output terminal.

Abstract: In a CMOS circuit having at least a first subcircuit coupled between a first point of potential and a first circuit node, and having a second subcircuit coupled between a second circuit node and a second point of potential, said first and second circuit nodes being coupled together, the improvement in combination therewith, comprising: first circuit means coupled to the first point of potential for converting the first potential to a third potential as a function of the magnitude of said first potential, said third potential being of a value inbetween the first and second potentials; a FET having source, drain, gate and well terminals, said source terminal being coupled to said well terminal and to said first circuit node, said third potential being applied to said gate terminal, said drain terminal being coupled to said second circuit node; wherein said FET, in conjunction with said first circuit means, operates to selectively provide a difference in potential between said first and second circuit nodes, the

Abstract: A current source circuit according to the present invention is provided with an output terminal 100, a bias voltage source 21, N channel MOS transistors 2 and 1 and P channel MOS transistor 3. The source of transistor 2, the drain of transistor 1 and the drain of transistor 3 are connected to a common node, the drain of transistor 2 is connected to output terminal 100 and the gate of transistor 2 is connected to bias voltage source 21. Conductions of transistors 1 and 3 are dynamically controlled in response to an external signal. As a result, it is possible to implement a current source circuit having a small number of devices and enabling an operation at a high speed.

Abstract: An integrated circuit for driving an active or passive matrix liquid crystal display panel or the like provides an analog output signal which switches through a voltage range that exceeds the safe operating voltage of the CMOS transistors from which it is formed. Duplicate digital to analog conversion circuits are provided on the integrated circuit but are operated from two different power supply voltage ranges. Each voltage range has a magnitude less than the safe operating voltage. The analog output signals generated by the duplicate digital to analog conversion circuits are coupled to an output multiplexer that is responsive to a control signal for selecting one of the two analog output signals to the output terminal of the integrated circuit.

Abstract: An automotive sensor arrangement including an automotive sensor coupled via first and second wires to signal sensor evaluation means, a signal conditioning circuit comprising a first gate means connected to provide a bias operating voltage signal on said first wire to the sensor, a second gate means of similar construction to the first gate means and mounted in the same environment and first gate means, the second gate means being coupled to the second wire of the leas means for receive the voltage signal bears a predetermined relationship to the switching point voltage of the second gate means.

Abstract: The plate voltage for a Dynamic Random Access Memory storage cell array is provided by two amplifiers. The first amplifier operates at a relatively low power level and compensates for leakage in the storage cell array, the compensation initiated by a departure of the plate from a nominal value which exceeds a preselected amount. The second amplifier operates at a higher power level and provides compensation for transients in the plate voltage resulting from the charging and discharging of the storage cells. Because the transients occur when the storage cells are accessed, the second amplifier is enabled only when a group of storage cells is accessed. In addition to operating at a higher power level, the second amplifier is more sensitive and responds to smaller excursions from the nominal voltage. Both the first and the second amplifiers have separate driver circuits for responding to excursions above and for responding to excursions below the nominal voltage.

Abstract: A method and circuit for selectively or programmably controlling the polarity of a signal includes a two transistor invertor with its sources coupled to a select signal and its complement and its drains coupled to buffer circuits that pull the drains to full CMOS voltage rail levels. The circuit consumes no standby current and is fully restoring.

Abstract: An output driver circuit for use with low voltage level, high speed data transmission busses which require slew and skew control of the output voltage transitions. An open collector output transistor has a controlled slew rate for both the high to low and low to high output transitions. The slew rate control is provided by controlling the slew rate of the base voltage of the output transistor in response to an input transition. A slew rate control circuit coupled to the output transistor includes a current source powered by a high stability bias generator, one or more output feedback circuits, an output level compensation circuit, and a base discharge circuit. The current source controls the amount of current available at the base of the open collector output transistor. The feedback circuits are used to control the initial voltage at the base of the output transistor, and the slew rate for the rising voltage at the base of the output transistor.

Abstract: Disclosed is a circuit which receives a supply voltage from a power supply and generates a voltage of a desired level different from that of the supply voltage. The circuit includes an oscillation circuit, a supply voltage generator, a first interconnection and a control circuit. The oscillation circuit generates an oscillation output signal. The supply voltage generator is responsive to the oscillation output signal from the oscillation circuit and generates a voltage of a predetermined level. The first interconnection connects the supply voltage generator to an internal circuit which is to be supplied with the voltage generated by the supply voltage generator. The internal circuit is also connected via a second interconnection to a power supply. The control circuit is provided between the first interconnection and the second interconnection as a variable resistor circuit which is responsive to the oscillation output signal from the oscillation circuit.

Abstract: The invention concerns a power diverting circuit for creating a supply voltage for a signal processing circuit from a source of data signals each having a high or a low potential respectively corresponding to a first or a second logic state. The circuit comprises a first terminal for receiving the data signals, a second terminal for providing the supply voltage, a switch coupled between the first terminal and the second terminal for selectively connecting and disconnecting the first terminal and the second terminal, and an inverter for inverting the state of the data signals. The inverter, which has an input terminal connected to the first terminal and an output terminal for providing the inverted data signals to the signal processing circuit, is responsive to the state of the data signals received at the first terminal to control the operation of said switch means.

Abstract: A charge pump circuit includes a pair of series switching devices coupled between an output node of the circuit and an input node. A power stage drives a charge transfer capacitor which is coupled to an intermediate node between the series switching devices. The power stage has an input coupled to the input node of the circuit, The power stage further includes a bootstrap capacitor for maintaining a conductive state during an entire half of a cycle of a period of oscillation of a local oscillator. The series switching devices may be driven in phase opposition by either a CMOS invertor or a pair of comparators.

Abstract: The present invention relates to an output driver circuit and in particular, an analog output driver circuit. Up to now, relays have been used in such driver circuits for the switching the outputs from output terminals (e.g., to ground) in the event of surges in the supply voltage. In accordance with the present invention, the relay is replaced by an electronic output switch element which has, free of control, a well-defined switch behavior. The output switch element is preferably a self-conducting field-effect transistor one connection of which is connected to the output line while its other connection is connected to ground.

Abstract: A biasing circuit (30) for an output vertical pnp transistor (10) formed in an integrated circuit and having an outer epitaxial region (20) includes a biasing vertical pnp transistor (33) and a comparator (38). Biasing circuit (30) is electrically connected to the integrated circuit voltage supply and the outer epitaxial region (20) of the output vertical pnp transistor (10) for electrically connecting the outer epitaxial region (20) to the voltage supply when the voltage at an output terminal (23) does not exceed the supply voltage and electrically disconnecting the outer epitaxial region (20) from the voltage supply when the voltage at the output terminal (23) exceeds the supply voltage, whereby improper operation of and damage to the integrated circuit upon the occurrence of an external fault condition is at least minimized.

Abstract: A built-in drive-power-source semiconductor device of low cost having a good switching characteristic and a decreased switching loss. In operation, a reference charge potential is applied to a charging IGBT by a first constant voltage diode thereby turning on the IGBT to charge a battery means. When the charge potential of the battery means reaches a prescribed level, a MOSFET is turned on by a second constant voltage diode, shortcircuiting the first constant voltage diode, causing the charging IGBT is turn off to eliminate overcharging of the batter means and maintain the potential of the battery means at a prescribed value.

Abstract: A DC--DC converter using a planar inductor is arranged in an IC memory card incorporating an EEPROM memory chip, and power supply is performed such that a voltage is adjusted by a dropping regulator, thereby reducing power consumption. The power consumption of the IC memory card incorporating the EEPROM can be reduced. The IC card can be driven by a single power supply, thereby providing a compact portable information device which can be driven by a battery for a long time.

Abstract: A dynamic biasing circuit is disclosed that includes a blocking current source (20) having a first current path connected to a first node (NODE 1) and a second current path connected to a second node (NODE 3). A linear source follower (22) has a first current path connected to the second node (NODE 3), a second current path connected to a voltage reference (24), and an input connected to the first node (NODE 1). A parasitic capacitor (26) is connected to the first node (NODE 1) and to ground potential, and a parasitic capacitor (28) is connected to the second node (NODE 3) and to ground potential.

Abstract: A modified pseudo-nMOS logic gate for use in systems in which quiescent current testing is desired. The load transistor of each pseudo-nMOS gate is controlled by a two-input load control gate. One input of the load control gate is connected to a global test signal and the second input of the load control gate is connected to the output of the pseudo-nMOS gate. In normal operation, the global test signal is logically true, and the load control gate has no effect on the pseudo-nMOS gate. During quiescent current testing, the global test signal is logically false and the output of the load control gate is determined by the logical output of the pseudo-nMOS gate. If the output of the pseudo-nMOS gate is logically true, the load control gate has no effect on the pseudo-nMOS gate. If the output of the pseudo-nMOS gate is logically false, the load control gate turns off the load transistor so that no static current flows through the load transistor.

Abstract: A voltage step-down circuit to be built in a highly integrated semiconductor IC chip, including a voltage divider and a voltage comparator. A divided output voltage V.sub.INT of the voltage divider and a comparison reference voltage V.sub.REF are applied to respective input terminals (-) and (+) of the voltage comparator. An output signal of the voltage comparator is supplied to a control signal generator section of the voltage divider to generate control pulses and to control the connection of capacitors of a voltage divider section of the voltage divider with the control pulses so as to supply the divided output voltage V.sub.INT to a load circuit. In this case, the capacitors are used as a voltage divider for generating a voltage for an internal circuit from an external power source voltage. Thus, power loss can be reduced and utilization efficiency of the capacitors is raised. Hence, the voltage step-down circuit is suitable for highly integrated semiconductor IC chip.

Abstract: A subcircuit for discharging a capacitor at a preselected rate incorporates a first transistor and a second transistor connected with the emitter of the first transistor providing current to the collector of the second transistor. The base of the first transistor is connected to a capacitor to be discharged at a preselected rate. The base current of the first transistor discharges the capacitor as a function of the base current provided to the second transistor. In order to provide a current of very small magnitude to the base of the second transistor, a plurality of lateral PNP transistors are connected in a plural stage arrangement in order to take advantage of the current dividing characteristic of lateral PNP transistors. A collector of one lateral PNP transistor is connected to the emitter of another so that each stage of the subcircuit reduces the output current by a very precise ratio.

Abstract: A semiconductor integrated circuit device comprises a semiconductor substrate; an input and output terminal (1) formed on the semiconductor substrate; an input and output circuit (2, 3) formed on the semiconductor substrate, connected to the input and output terminal (1), and having an output buffer (2) of CMOS FETs, supply voltages Vcc1 and Vcc2 being applied to the output buffer; a semiconductor integrated circuit formed on the semiconductor substrate and connected to the input and output circuit; and a circuit for preventing forward junction current from flowing from the input and output terminal (1) to the output buffer (2) when an input voltage exceeding the supply voltages is applied to the output buffer. In an integrated circuit device using a plurality of different supply voltages, it is possible to prevent an input voltage beyond the supply voltages from being applied to the input and output circuit.

Abstract: An integrated circuit including an operating circuit portion which requires a predetermined voltage in order to function properly, a charge pump circuit for providing a high voltage output equal to the predetermined voltage from a lower voltage input, a terminal for receiving voltage from a source of external voltage, and a circuit for selectively providing voltage to the operating circuit portion of the integrated circuit from the terminal if the level of voltage detected at the terminal from the external voltage source is above the predetermined voltage and for providing voltage to the operating circuit portion from the output of the charge pump if the voltage detected at the terminal is less than the predetermined level.

Abstract: An internal power supply circuit includes a main internal power supply potential generating circuit for generating an internal power supply potential based on a prescribed reference potential, and an auxiliary internal power supply potential generating circuit which is activated in response to a control signal and when activated, generating an internal power supply potential together with the main internal power supply potential generating circuit. The auxiliary internal power supply potential generating circuit includes a P channel MOS transistor for driving, a differential amplifying circuit for controlling the driving transistor by comparing the internal power supply potential with the reference potential and a standby potential supplying circuit for applying a standby potential which is slightly higher than the threshold potential at the which the transistor is rendered conductive, to the gate of the driving transistor while the differential amplifying circuit is not activated.

Abstract: In a microcomputer, a circuit is provided which performs the option setting of the condition of an I/O port. The option setting is repeatedly performed while the microcomputer is operating. As a result, even if the option setting is changed to an incorrect setting due to noise from external sources, the incorrect option setting is immediately returned to the correct setting. Moreover, the option setting is never reset at the time of resetting other than the resetting performed at the time of the turning on of the power.

Abstract: Disclosed is a DRAM including a power-on reset signal generating circuit for outputting a voltage of a predetermined level for a definite period by utilizing a rise of an external supply voltage, and a supply voltage conversion circuit for lowering the external supply voltage to a constant voltage. In this DRAM, the power-on reset signal generating circuit is driven by the external supply voltage not an output voltage of the supply voltage conversion circuit. The output voltage of the supply voltage conversion circuit is applied to various internal circuits including smaller-scale MOS transistors, to drive these internal circuits. Since the supply voltage conversion circuit often includes circuit components with a large time constant in order to decrease power consumption, the output voltage of the supply voltage conversion circuit rises rather slowly than the external supply voltage.

Abstract: An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. These devices have been found capable of transferring ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage.

Abstract: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and drain terminals of all other stages, a second N type field effect control transistor device having drain and source terminals connecting the drain terminal and the gate terminal of the first switching transistor device, and a storage capacitor joined to the source terminal of the first device; a source of voltage to be pumped is connected to the drain terminal of the first device of the first stage.

Abstract: There is disclosed on optoelectronic integrated circuit comprising, a plurality of channels each including an optical receiving device for converting a received optical signal to an electric signal, and an amplifier for amplifying an output signal of the optical receiving device, the channels being integrated on the same semiconductor substrate, electric power source nodes of at least two of the amplifiers of the respective channels being connected to a common electric power source node, and the common electric power source node being connected through a resistor element to an electric source power supply terminal for supplying an electric source power to the channels.

Abstract: An integrated circuit including an operating circuit portion which requires a predetermined voltage in order to function properly, a charge pump circuit for providing a high voltage output equal to the predetermined voltage from a lower voltage input, a terminal for receiving voltage from a source of external voltage, and a circuit for selectively providing voltage to the operating circuit portion of the integrated circuit from the terminal if the level of voltage detected at the terminal from the external voltage source is above the predetermined voltage and for providing voltage to the operating circuit portion from the output of the charge pump if the voltage detected at the terminal is less than the predetermined level.

Abstract: An integrated circuit including an operating circuit portion which requires a predetermined voltage in order to function properly, a charge pump circuit for providing a high voltage output equal to the predetermined voltage from a lower voltage input, a terminal for receiving voltage from a source of external voltage, and a circuit for selectively providing voltage to the operating circuit portion of the integrated circuit from the terminal if the level of voltage detected at the terminal from the external voltage source is above the predetermined voltage and for providing voltage to the operating circuit portion from the output of the charge pump if the voltage detected at the terminal is less than the predetermined level.

Abstract: An LCD precharge regulator circuit providing current directly from the input battery voltage to precharge the LCD display. A first switch activates a precharge regulator coupled to the unregulated DC input voltage, to supply the power for the initial current surge from the DC input to charge the LCD display. The precharge regulator includes a transistor and a biasing circuit. The biasing circuit initially turns the transistor fully on, but increasingly biases the transistor off as the LCD display charges to just below the operating voltage of the LCD display. A delay circuit activates a second switch after the LCD display is substantially charged, where the second switch connects the supply voltage from the DC/DC converter to the LCD display. At that point, the transistor is biased off, isolating the LCD display from the DC input voltage. Thus, the supply voltage need only sustain the charge on the LCD display after being substantially charged.

Abstract: A biasing device which is in thermal contact with an RF device for actively biasing the RF device operating in quasi-linear modes. The biasing device provides a low impedance current source with high current capability to the base of the RF device. The biasing device includes three specially-processed transistors. The second and third transistors are connected such that their base-emitter and base-collector junctions are in parallel effectively forming two exceptionally low turn on series diodes. The result of reducing the resistances of the second and third transistors, by configuration and processing, is that they turn on slightly before the RF device is biased to its quiescent point.

Abstract: A circuit for synchronizing an operating clock of a switching power supply (SPS) system is provided. The SPS has an oscillator, a primary control circuit, a secondary voltage generation circuit, a feedback control circuit. The oscillator outputs an oscillation signal to the primary control circuit. The feedback control circuit, in response to a direct current (DC) voltage from the secondary voltage generation circuit, generates a DC feedback voltage signal. The synchronization circuit comprises an isolation device, a signal separation circuit and a triangle-wave generation circuit. The isolation device has an input terminal and an output terminal. The input terminal receives a horizontal synchronization signal and the DC feedback voltage signal. A mixed signal is generated at the output terminal as a result of amplitude-modulating the DC feedback voltage signal by the horizontal synchronization signal. The input terminal is voltage-isolated from the output terminal.

Abstract: In a system wherein a plurality of semiconductor integrated circuit devices are coexistent and wherein a plurality of supply potential lines are laid, the main power sources of a TTL interface LSI and an ECL interface LSI are shared so as to reduce the number of supply potential lines. Besides, in a case where an LSI, for example, BiCMOS LSI to interface with both the TTL and ECL interface LSI's has a device withstand voltage of about 3 V, it is permitted to interface with both the LSI's across the supply voltage .vertline.5 V.vertline. of the main power source of the TTL interface LSI and the supply voltage .vertline.2 V.vertline. of the power source of the emitter follower portion of the ECL interface LSI because the supply voltages have a difference of 3 V.

Abstract: A differential current source circuit includes three P-channel MOSFETs and two N-channel MOSFETs. Each source of first and second P-channel MOSFETs is connected to a power supply, and a bias voltage is applied to each gate of the MOSFETs. A current path of the first N-channel MOSFET is connected between a drain of the first P-channel MOSFET and a ground. A current path of the third P-channel MOSFET is connected between a drain of the second P-channel MOSFET and a current output terminal. A gate of the third P-channel MOSFET is connected to the drain of the first P-channel MOSFET. One end of a current path of the second N-channel MOSFET is connected to a connecting point of the first P-channel and first N-channel MOSFETs, and the other end is connected to a connecting point of the second P-channel and third P-channel MOSFETs. A digital signal is applied to a gate of the second N-channel MOSFET.

Abstract: A boosting circuit is provided applicable in various semiconductor integrated circuits such as a word line boosting circuit in a semiconductor memory. Because a backgate electrode of a PMOS transistor connected between power supply potential and an output node is connected to the output node, the output node is precharged to the Vcc level during a boosting term. Therefore, the boosting condition by a MOS capacitor is alleviated in comparison with a conventional boosting circuit. Proper boosting operation can be carried out even at a lower level of a supplied power supply voltage. Therefore, operable margin of power supply voltage is enlarged.

Abstract: A small value current source circuit utilized in bipolar integrated circuits. A reference potential is level-shifted by a first level shift circuit and applied to one input of a differential amplifier. The reference potential is also level-shifted by a second level shift circuit and applied to the other input of the differential amplifier. A constant current source circuit supplies currents both proportional to the currents flowing in the differential amplifier and of mutually different values to the first and second level shift circuits. The differential amplifier amplifies the difference of the input voltages and produces an output current.

Abstract: A voltage and resistance synthesizer includes a pulse width modulator (PWM) for synthesizing voltage and resistance values at a pair of terminals. A selector switch selects between a resistance synthesis mode, in which resistance values are synthesized from a single reference resistor, and a voltage synthesis mode, in which voltage values are synthesized from a single reference voltage. The pulse width modulator permits digital control words to be received which govern the synthesized value with 16 bit resolution. A low pass filter blocks the switching frequency components and provides a d.c. voltage which is the product of the duty cycle and the reference value.

Abstract: A current source circuit includes at least three pairs of bipolar transistors of the same polarity type. The first transistors of each pair are connected in one series circuit string emitter to collector. The second transistors of each pair are connected in another circuit string. The first-pair second transistor is connected emitter to collector with the second-pair second transistor while the emitter of the second-pair second transistor is connected to the base of the third-pair second transistor which serves as the output transistor. The first transistors of the first and third pairs have their bases connected respectively with their collector. The bases of the two second-pair transistors are cross coupled with the collectors of the second-pair transistors.

Abstract: An integrated circuit which includes a pair of serially arranged P channel transistor devices connected with their source and drain terminals in series. The devices are constructed as N well devices in a P substrate. Using a pair of N well devices allows higher voltages to be divided and applied across the two devices without reaching the breakdown limits of either the oxide or the junctions between different portions of the devices used in the process. These devices have been found capable of transferring ten or more volts to circuitry for programming or erasing flash EEPROM cells even the they are a part of integrated circuitry designed for only 3.3 volt usage.

Abstract: An internal power voltage generating circuit of a semiconductor memory device may be constructed with a voltage sensing circuit (100) and a reference voltage controller (300) providing an internal power voltage int. V.sub.CC of a given reference voltage amplitude V.sub.ref and an external power voltage amplitude ext. V.sub.CC. Thus, when a high voltage over an operating voltage of a chip is applied to a pad (10) of the chip, the internal power voltage is raised to the level of the external power voltage. Therefore, when stress is added to the chip during a "burn-in-test", the defective chip is easily detected. Consequently, the reliability of those semiconductor memory devices subjected to post-manufacturing testing can be improved.

Abstract: A constant voltage generator having a substrate voltage pumping circuit, a voltage pumping circuit and a single oscillator for generating pulses to which the substrate voltage pumping circuit and the voltage pumping circuit are commonly responsive, reducing current consumption of a semiconductor memory device during a stand-by state thereof.

Abstract: A logic circuit is driven by a single alternating voltage power supply so that the energy stored in parasitic capacitances can be mostly recovered, rather than dissipated, as in conventional logic designs. Successive stages of the logic circuit are of opposite conductivity types such that the successive stages are activated in alternate half cycles of the power supply without separate clock signals. Each stage of the logic circuit is precharged during a respective first half cycle of the power supply and is active in logical processing during a second half cycle. The half cycles are defined by the rising and falling edges of the power supply. The logic circuit resonates with an inductor coupled across the power supply but closely coupled to the logic circuit. This inductor and the method of charging and discharging the capacitors in the logic circuit serve to minimize the power dissipated during logical processing.

Abstract: The circuit comprises a tank capacitance and a charge circuit supplied with the same voltage as the bridge and comprising an inductance and a control transistor. There is also provided a control circuit, which comprises an oscillator controlling the periodic switching of control transistor and a comparator which controls the momentary clamping of control transistor in the condition wherein the charge circuit is interrupted when the difference between the voltage across capacitance and the power supply voltage exceeds a present maximum value and the unclamping of the same transistor when such difference falls below a preset minimum value. A further comparator similarly clamps control transistor if there is an excess current in the transistor itself.