Abstract: An intelligent bias voltage generating circuit capable of providing an electronic device with a reliable bias signal includes a power input terminal which is electrically connected to a power generating device for providing a power input, and a bias voltage generating circuit which is electrically connected to the power input terminal for responding to power fluctuations and generating a bias voltage signal output by a multi-section linear variation method.

Abstract: An IC which integrates an EPROM is disposed on a circuit board. Also, a pad for supplying a writing voltage to the EPROM and a voltage supplying circuit, for supplying a power voltage to power terminals of the IC, which includes a first transistor and a second transistor, are disposed on the circuit board. When the pad is supplied with a high voltage for writing the data in the EPROM, the first transistor is on, the second transistor is off, and the voltage is supplied to the EPROM as the writing voltage. When data are read from the EPROM after the circuit board is packaged, because the pad is not supplied with any voltage, the first transistor is off, the second transistor is on, and a reading voltage is supplied to the EPROM via the outer terminal.

Abstract: Disclosed is an integrated circuit device. According to the present invention, an integrated circuit device comprises: a high frequency electronic circuit having a first enhancement transistor, to the gate of which, at least, a bias voltage is applied; and a bias circuit, including a second enhancement transistor formed on a substrate on which the first enhancement transistor is formed, and first, second and third resistors connected in series between a positive power source and a power source ground, in which a connection point of the first and the second resistors is connected to a drain of the second enhancement transistor, a connection point of the second and the third resistors is connected to a gate of the second enhancement transistor, and voltages at the connection point of the second resistor and the third resistor or at a terminal which is closer to the power source ground is applied as a bias voltage to the high frequency electronic circuit.

Abstract: A reference voltage generating circuit is provided with a reference voltage output terminal, a voltage dividing circuit that divides a voltage supplied from a power source, and an integrating circuit having a given time constant, for integrating a voltage of the divided voltage output terminal of the voltage dividing circuit and generating a reference voltage as a result of integration to the reference voltage output terminal. A high-speed charging circuit is connected to the reference voltage output terminal, for charging the integrating circuit at a high speed when the power source is turned on, to elevate a voltage of the reference voltage output terminal at a speed higher than a speed determined by the time constant of the integrating circuit.

Abstract: A circuit configuration for generating a reference potential includes a first transistor with an emitter connected to a ground potential and a base and a collector connected to one another. A second transistor has a base connected to the base of the first transistor. A first resistor is connected between the collector of the first transistor and an output terminal for picking up the reference potential. A second resistor is connected between the collector of the second transistor and the output terminal. A third resistor is connected between the emitter of the second transistor and the ground potential. A third transistor has a base connected to the collector of the second transistor and an emitter connected to the ground potential. A controlled current source is connected between a supply potential and the output terminal and is coupled on the input side to the collector of the third transistor. A capacitor is connected parallel to the second resistor.

Abstract: There is provided an array device including functional circuits for a plurality of channels, constant current generating circuits for the plurality of channels for generating constant currents used to drive the functional circuits, respectively, in accordance with a control signal supplied from the outside, and a wiring for supplying therethrough the constant currents from the constant current generating circuits to the functional circuits, respectively, which are formed on an integrated circuit chip, wherein the constant current generating circuits provided so as to correspond to the channels are arranged concentratedly in a specific region on the integrated circuit chip, and the wiring is comprised of a common wiring extending from one terminal provided in the vicinity of the specific region to the vicinities of the constant current generating circuits.

Abstract: Method and circuitry for power control in integrated circuits using field effect transistor (FET) technology are disclosed. According to the present invention, for each circuit block that is biased by the power supply voltage a dedicated level shifter is inserted between the block and the power supply. In one embodiment, a switch is also coupled in parallel to the level shifter. The switch is closed when a low external power supply voltage is applied, and opened when a higher power supply voltage is applied. A second embodiment removes the switch and adds a bias generator that supplies a bias voltage to each level shifter.

Abstract: A semiconductor integrated circuit system includes a first power line which supplies a first source power voltage, and a second power line which supplies a second source power voltage. A first edge detecting unit outputs a first edge detection signal when a rising edge of the first source power voltage is detected. A second edge detecting unit outputs a second edge detection signal when a rising edge of the second source power voltage is detected. An output unit is connected to the first power line, and outputs data to a data terminal in a data output cycle and sets the data terminal in a high-impedance state in response to the first edge detection signal. An output control unit is connected to the second power line, and controls the output unit in accordance with a read-data signal in the data output cycle, and controls the output unit in response to the second edge detection signal, so that the data terminal is set in the high-impedance state by the output unit.

Abstract: In an intermediate potential generating circuit provided in a DRAM, a reference potential generating circuit includes two combinations of a resistor element constituted by a P channel MOS transistor and a diode constituted by an N channel MOS transistor, and outputs a reference potential Vcc/2+Vthn. A charging circuit constituted by an N channel MOS transistor charges an output node to an intermediate potential Vcc/2 based on the reference potential. A discharging circuit includes one combination of a resistor element constituted by a P channel MOS transistor and a diode constituted by an N channel MOS transistor, and provides a prescribed current flowing from the output node. Reduction of supply voltage Vcc becomes possible by eliminating a diode constituted by a P channel MOS transistor which makes reduction of a threshold voltage Vthp difficult.

Abstract: The semiconductor integrated circuit device of the present invention includes a plurality of integrated circuits. The scheduling circuit selects an arbitrary number of integrated circuit from the plurality of integrated circuits, and connects the selected integrated circuits between the power line and the ground line such that the selected integrated circuits are arranged in series or in series-parallel. The scheduling circuit sets a combination of connection of the selected integrated circuits such that the consumption power of the total of the selected integrated circuits becomes minimum. The voltage control circuit sets a potential of a serial connecting portion of the selected integrated circuits. The data control circuit has an input output circuit for inputting and outputting data between the selected integrated circuits, and the outside, and a level conversion circuit for converting a level of data between certain integrated circuits.

Abstract: A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command, the internal state machine takes control and starts the program or erase operation. While one bank is busy with a program or erase operation, the other bank can be accessed for a read operation. Power is supplied for each of the read and write operations via an internal multiplexed multi power supply source that provides an amount of power needed based on the memory operation being performed.

Abstract: A step generator 800 including at least one gate 805 and a voltage divider 806 coupled to an output of gate 805. The selected node of voltage divider 806 provides an output V.sub.OUT of generator 800. Circuitry 801 presents a signal to an input of gate 805 to initiate current flow through voltage divider 806.

Abstract: A temperature compensated current source for driving a multi-vibrator (19) includes a voltage generator (10) that outputs a voltage that is proportional to absolute temperature (PTAT) and a resistor (12) for setting the current output by the voltage generator (10). The temperature coefficient of the resistor (12) is chosen such that any variations in the current supplied by the voltage generator (10) are compensated for to result in a current that has substantially no temperature variation. This current is mirrored to a current source (18) for driving the multi-vibrator (19). The voltage across the resistor (12) is a function of temperature, with the current being a function of the value of the resistor (12). The temperature coefficient of the resistor (12) is substantially equal to the temperature coefficient of the voltage generator (10) to yield a temperature coefficient of substantially 0 ppm/.degree. C. for the current.

Abstract: The present invention provides an analog biased pre-driver and pad as well as a duty cycle adjustment cell prior to the pre-driver and pad. The pre-driver and pad may operate in either a 3 volt mode, a 5 volt mode or any voltage in between depending only on the power supply voltage present. No production configuration or post-production configuration is required. The present invention utilizes a special bias circuit to reduce the Vcc, temperature and other processing variations. A duty cycle cell produces a range of duty cycles when the circuit is operating between a 3 volt and 5 volt range.

Abstract: An internal voltage generator for a semiconductor device. Whereas a feedback signal is given to maintain a voltage of a predetermined level by a voltage detector in the conventional art, the internal voltage generator adopts a method of adjusting the period. Therefore, the variance of a signal generated due to a time delay can be reduced. The internal voltage generator includes an oscillator for generating pulses of a predetermined period when a power-up signal is activated, a timing generator for generating appropriate timing according to the output of the oscillator for determining the basic operational period of a voltage pump and a series of signals, a pump driver for controlling a voltage pump to operate with a predetermined phase by controlling a pulse signal from the oscillator by the pulse signal of a predetermined period generated from the timing generator, and a voltage pump for pumping voltage to a third voltage and outputting the same.

Abstract: A semiconductor memory device includes a mode detection circuit for generating a mode detection signal in response to external input signals /RAS, /CAS and /WE, an internal potential generating circuit for generating and supplying to an output node an internal potential, in response to an activated potential control signal, and an internal potential control circuit for activating a potential control signal when a potential at the output node has not yet reached a predetermined potential in a case where mode detection signal indicates a mode other than the test mode, and for activating the potential control signal when the potential at the output node has not yet reached an externally supplied external reference potential in a case where the mode detection signal indicates the test mode.

Abstract: A voltage regulator for electrically programmable non-volatile memory cells includes a gain stage which is supplied a voltage from a voltage booster connected to a supply voltage reference, having an input terminal connected to an output of a voltage divider and an output terminal connected to a pull-up transistor of a pull-up and pull-down differential pair to output the regulated voltage for programming at least one column or bit line of the memory cells. The voltage regulator also includes a second gain stage having an input terminal connected to a second output of the voltage divider. The second stage has an output connected to turn on the pull-down transistor in the complementary pair upon the regulated voltage exceeding a predetermined value.

Abstract: Semiconductor device according to the present invention includes package frame, bonding wire, pad, first internal power supply line, second internal power supply line, internal circuit, stabilize circuit, GND package frame, GND bonding wire, GND pad, and internal GND line. Bonding wire, pad, and first and second internal power supply lines function as a filter. As a result, noise generated by operation of the internal circuit is absorbed in propagating to the stabilize circuit through first internal power supply line, pad, and the second internal power supply line. Therefore, effects of noise given to the stabilize circuit are small.

Abstract: An adaptive bias circuit for switched capacitor applications that compensates for temperature and process variations by maintaining a constant settling time of CMOS operational amplifiers is introduced. To this end, the adaptive bias circuit allows a dynamic trade-off between the slew-rate and the gain bandwidth product which allows the output of the operational amplifier to settle within a certain predetermined precision. A first aspect of the invention includes a current source providing a same current to a pair of transistors having different effective current densities. A resistor is coupled between the pair of transistors while from one end of the resistor, a constant bias current is drawn. In this manner, a voltage difference develops across the resistor which effectively indicates the change in the transconductance of the pair of transistors with respect to temperature and process variations.

Abstract: A reference voltage generation circuit includes: a load unit having one end thereof connected to a higher voltage power supply line; an enhancement type n-channel MIS transistor having a drain thereof connected to the other end of the load unit, and a source thereof connected to a lower voltage power supply line; and a source follower circuit using a MIS transistor as a driving element, the source follower circuit having an input end thereof connected to the drain of the n-channel MIS transistor and having an output end thereof connected to a gate of the n-channel MIS transistor. A reference voltage is obtained at the drain of the n-channel MIS transistor. By the constitution, it is possible to obtain a stable reference voltage, and to incorporate the reference voltage generation circuit into an integrated circuit produced by integrating MIS transistors, without introducing an increase in production processes. It is also possible to reduce a consumed current of the reference voltage generation circuit.

Abstract: In a reference voltage generating circuit including a current mirror circuit having an input and an output, a bias current supply circuit for supplying a bias current to the input of the current mirror circuit, a switching element for turning ON and OFF the bias current supply circuit, and an output transistor for generating a reference voltage, a delay circuit formed by a capacitor is connected to the output of the cirrent mirror circuit.

Abstract: A system and method for programming elements in an integrated circuit. The system allows for selection of an internal voltage supply and an external supply. Provision is also possible for improved testing techniques.

Abstract: A circuit for detecting leakage voltage of a MOS capacitor, the detecting circuit including a timing control signal generator for generating a timing control signal; a sample/hold circuit for sampling and holding a first voltage, the sample/hold circuit comprising a switching circuit switched by an output of the timing control signal generator and being operatively coupled to a MOS capacitor; a monitoring capacitor for monitoring a leakage voltage of the MOS capacitor operatively coupled to the sample/hold circuit; a monitoring capacitor precharge circuit for holding a second voltage in the monitoring capacitor; and a leakage voltage detecting portion for detecting when a leakage voltage of the monitoring capacitor is below a predetermined value. The leakage voltage detecting portion is also capable of detecting what value the leakage voltage of the monitoring capacitor is, for example, when the leakage voltage is below the predetermined value.

Abstract: An integrated circuit device provided with (a) an auto-clear circuit for outputting an auto-clear signal in response to a supply of the power source, (2) a mode signal generating circuit for generating a burn-in mode signal or test mode signal based on the auto-clear signal, and for generating a normal mode signal based on a reset signal or operation start signal, and (3) a mode setting circuit for making one of the burn-in setting and the test mode setting respectively in response to the burn-in mode signal and test mode signal, whichever inputted, and for making normal mode setting upon input of the normal mode signal. The present integrated circuit device omits a mode-setting-only input terminal which used to be provided separately only for making the burn-in setting or test mode setting. As a result, a system employing the present integrated circuit device can be designed more flexibly and downsized as well.

Abstract: An intensity controlling circuit device can correct variation in intensity of light beams, due to tolerance occurred in each of a plurality of LED-array chips, emitted by LEDs provided in each of the LED-array chips. The intensity controlling circuit device is connected to at least one LED-array chip comprising a plurality of LEDs and slave transistors corresponding to each of the LEDs. The intensity controlling circuit device comprises an intensity controlling circuit connected to the respective LED-array chip. The intensity controlling circuit comprises a first transistor provided between a power source and a constant current generating unit so as to supply a current to the LED-array chip, and an intensity adjusting unit having a second transistor connected to the first transistor in parallel and a controlling unit for controlling the on/off state of the second transistor.

Abstract: In an SOI-type semiconductor device, a power supply voltage is applied to back gates of P-channel MOS transistors in a standby mode, and a voltage lower than the power supply voltage is applied to the back gates of the P-channel MOS transistors in an active mode. A ground voltage is applied to back gates of N-channel MOS transistors in the standby mode, and a voltage higher than the ground voltage is applied to the back gates of the N-channel MOS transistors in an active mode.

Abstract: A positive current source (PCS) for supplying common mode current. The PCS includes a pair of unity gain inverting single ended amplifiers that are connected in antiparallel across a pair of matched resistors. Alternately, the resistors can be connected across the inverting and non-inverting sides of a differential amplifier. A constant voltage is applied across the resistors to supply the common mode current (I.sub.cm) while maintaining a common mode resistance of R/2 and a differential mode resistance approaching infinity. The PCS has a common mode resistance which is small enough to maintain a stable common mode operating point with process variations providing minimal impact.

Abstract: A low-current source circuit for generating a constant current and a reference voltage from a fluctuating voltage source is disclosed. A resistive circuit is electrically connected to the voltage source for determining amount of the constant current. A charging circuit is electrically connected to a second lead of the resistive circuit and the voltage source for supporting a charging path for the voltage source. A current output circuit is electrically connected to the second lead of the resistive circuit for outputting the constant current. A stabilizing circuit is electrically connected between the second lead of the resistive circuit and a control lead of the current output circuit for stabilizing the current output circuit. A reference voltage circuit is electrically connected to an output lead and the control lead of the current output circuit for generating the reference voltage.

Abstract: A semiconductor device operable in a selected mode which is selected from a plurality of operation modes, a number of the operation modes being more than two. The semiconductor device includes a plurality of voltage supply circuits for supplying an internal voltage to internal circuits of the semiconductor device, and a control circuit for driving a predetermined number of the voltage supply circuits based on a signal indicating the selected mode, the control circuit changing the predetermined number for each of the operation modes.

Abstract: A detection circuit includes a current mirror circuit that produces electric currents at first and second output terminals in response to a current supplied to its input terminal. A first active load is connected to the first output terminal and a second active load is connected to the second output terminal and an external output terminal. A control circuit controls the potential of the control electrode of the second active load according to the voltage or the current at the first output terminal. The control circuit can include a capacitive device that determines the voltage at the control electrodes of the active loads according to the peak value of current supplied to the current mirror circuit input terminal.

Abstract: A main source voltage transmission line for transmitting a source voltage VCH as one power source and a sub source voltage transmission line are provided corresponding to a gate circuit. A resistive element having a high resistance is provided between the main source voltage transmission line and the sub source voltage transmission line. A capacitor comprised of an insulated gate field effect transistor is connected to the sub source voltage transmission line. The gate circuit is operated with a voltage on the sub source voltage transmission line as an operating source voltage. Thus, the voltage on the sub source voltage transmission line can be maintained at a voltage level that balances with a sub-threshold current flowing through the gate circuit, and the voltage on the sub source line can be stably maintained by the capacitor.

Abstract: Activatable/deactivatable circuit arrangement for producing an output reference voltage having a first transistor (T1) whose emitter is connected with a reference potential (M) and whose base and collector are connected with one another, having a second transistor (T2) whose base is connected with the base of the first transistor (T1), having a first resistor (R1) that is connected between the collector of the first transistor (T1) and an output terminal (U) for supplying the output reference voltage, having a second resistor (R2) that is connected between the collector of the second transistor (T2) and the output terminal (U), having a third resistor (R3) that is connected between the emitter of the second transistor (T2) and the reference potential (M), having a third transistor (T3) whose base is connected with the collector of the second transistor (T2) and whose emitter is connected with the reference potential (M), and having a controlled current source (T4) that is connected between a supply potential

Abstract: An output driver for mixed voltage systems includes an input line for receiving a signal to be output. The circuit also includes an overvoltage generator, coupled between the input line and an output stage. The overvoltage generator boosts a level of the signal to a second voltage before it reaches the output stage. A restore circuit is also provided which restores the second voltage with every transition of the input signal.

Abstract: The device comprises, connected to the antenna, a rectifier (RD) delivering a primary DC supply voltage (VNR) at its output terminal (BS), stabilizing means (1,ST) for generating a stabilized DC voltage (VDD) from the said primary voltage. First means (R3, R4, R5) calculate a first prespecified voltage threshold corresponding to a prespecified level of the stabilized DC supply voltage. Comparison means (CP) are also provided, the output terminal (BS2) of which is connected to the processing means, a first input of which is connected to the output of the first calculating means, and a second input of which is connected to the output terminal (BS) of the rectifier. Furthermore, a load (RBL) with chosen impedance is connected between the said output terminal of the rectifier and earth by way of a controllable switching means (T200) whose control input is joined to the output terminal of the comparison means (CP).

Abstract: This invention is a voltage divider circuit having an input voltage at a first terminal (V.sub.IN) and an output voltage at a second terminal (V.sub.OUT). The circuit includes a parallel-connected first resistor (R.sub.1) and first capacitor (C.sub.1) coupled between the first and second terminals (V.sub.IN,V.sub.OUT) and a parallel-connected second resistor (R.sub.2) and second capacitor (C.sub.2) coupled between the second terminal (V.sub.OUT) and a reference (V.sub.REF). The ratio of the ohmic value of the second resistor (R.sub.2) to the sum of the ohmic values of the first and second resistors (R.sub.1,R.sub.2) is substantially equal to the ratio of the value in farads of the first capacitor (C.sub.1) to the sum of the values in farads of the first and second capacitors (C.sub.1,C.sub.2).

Abstract: In a voltage-limiting circuit, the voltage to be limited is applied to the terminals of a resistive line, and the current flowing in this line is amplified by a current mirror that thus produces a reference current. A current-controlled voltage source receives this reference current and produces a reference voltage. This reference voltage is given to a hysteresis comparator that switches over for two distinct values of the voltage to be regulated. The disclosed device is particularly useful in the field of the load pumps used in electrically programmable memories.

Abstract: A current source for generating a current that is relatively stable over variations in the power supply voltage and temperature, and over variations in process parameters is disclosed. The current source includes a bias circuit, for producing a compensating bias voltage, and a current mirror. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating transistor (biased in saturation) in a first current mirror, which controls a current applied to a linear load device. The voltage across the load device determines the bias voltage, which is in turn applied to the gate of a transistor in the reference leg of a second current mirror. The bias voltage controls the current in the reference leg of the second current mirror, and an output leg mirrors the second reference current to produce a stable output current.

Abstract: An injector control circuit for a motor vehicle electronic injection system utilizing current recirculation to control an injector actuation winding provided with a circuit configuration containing a constant current generator operable to eliminate the problems of instability and sensitivity to supply line interruptions to which prior art control circuits are subject.

Abstract: An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than the bias voltage less the pass transistor threshold. The first control voltage corresponds to the input voltage for input voltages less than the bias voltage less the pass transistor threshold.

Abstract: The present invention comprises a cascode circuit of the type having a first and second FET in a first leg and a third and fourth FET in a second leg comprising. The first and third FETs are switched between an on state and an off state substantially in tandem in response to a level change in an input signal to the cascode circuit. The second and fourth FETs are switched between an on state and an off state substantially in tandem in response to a level change in the input signal and substantially complimentary to the switching of said first and third FETS. A biasing signal is applied to a control electrode of the first FET responsive to transition of the input signal from a first level to a second level. A biasing signal is also applied to a control electrode of the third FET responsive to transition of the input signal from the second level to the first level.

Abstract: A signal generator for generating test mode signals when any voltage higher than a recommended input high voltage is applied to a predetermined input pin, and for switching from a normal mode to a test mode in response to the test mode signals. A high impedance circuit is coupled between the input pin and a first node. The high impedance circuit comprises a plurality of transistors, the plurality of transistors respectively being connected in series and respectively having a gate coupled with a source or a drain. A signal amplifier is coupled with the high impedance circuit through the first node. A resistor is coupled between the first node and a reference voltage. A transistor is coupled between the first node and a second node between predetermined transistors among the plurality of transistors. The transistor bypasses a current path from the second node to the first node and maintains a potential level of the first node, in response to an output condition of the signal amplifier.

Abstract: A device for raising voltage comprises a first element for providing a first output pin with a voltage raise in response to a first voltage change at a first input pin, and for providing a second output pin with a voltage raise in response to a second voltage change at a second input pin; and a second element for driving, when the voltage at the first output pin becomes higher than the voltage at the second output pin due to the first voltage change at the first input pin, the second output pin to maintain a voltage keeping pace with the voltage at the first output pin, and for driving, when the voltage at the second output pin becomes higher than the voltage at the first output pin due to the second voltage change at the second input pin, the first output pin to maintain a voltage keeping pace with the voltage at the second output pin.

Abstract: Reference circuitry RC includes a current-sensing translator M5-M7, MX connected to a current reference source RS. The outputs O1, O2, etc. of the current-sensing translator M5-M7, MX are mirrored into one or more sense amplifiers SA1,SA2 of sensing circuitry SC. The current-sensing translator M5-M7, MX permits the current from the current reference source RS to be mirrored to multiple sense amplifiers SA1,SA2 at a predetermined ratio.

Abstract: According to the present invention, there is provided an integrated circuit useful in an electronic encoding device having a voltage source, a user interface and a transmitter. In one embodiment the integrated circuit includes a wake-up circuit which generates a signal responsive to an input received from the user interface; power switching logic which provides power from the voltage source to a non-regulated power bus and a voltage regulating circuit, the power switching logic being responsive to the signal from the wake-up circuit; a regulated power bus in communication with the voltage regulating circuit; non-volatile memory in communication with the regulated power bus; encoder logic in communication with the regulated power bus, the encoder logic having output logic which provides a signal to the transmitter.

Abstract: A voltage level converter having: an input bias terminal; connect to first, second and third voltage sources; first and second complementary output terminals; and an input control terminal wherein, said input bias terminal is connected to a third output terminal of an automatic bias stage, said bias stage having connections to said voltage sources for providing substantially said first low voltage to said third output terminal in the absence of said second high voltage and providing a third voltage that is greater than said first low voltage when said second high voltage is present, said third voltage being derived from said second high voltage.

Abstract: A bi-directional current source which maintains accurate, substantially equal source and sink currents over a large range of output voltages. The current source includes a primary field effect transistor (FET) and two mirroring FET's. It additionally includes at least one operational amplifier for voltage balancing. An optional operational amplifier provides and additional bias voltage and transistor matching optionally provides impedance matching of the supply voltages.

Abstract: A phase generator circuit cyclically produces a first pair of phase signals and a second pair of phase signals, comprising a first circuit to produce a first phase of each pair of phase signals, these first phase signals being non-overlapping and switching over between a voltage 0 and a voltage VCC, and second and third circuits for the production, from the first phase signals, respectively of the second phase of the first pair and the second phase of the second pair of phase signals, these second phase signals being non-overlapping with the first phase signals and switching over between a negative voltage -V and a voltage VCC. The disclosure finds application in the piloting of charge pump type of negative voltage generator circuit.

Abstract: A voltage inverter provided as part of a low power amplifier system includes a charge pump capacitor, a charging inverter circuit for charging the charge pump capacitor in response to clock pulses, a FET grounding switch interposed between the charge pump capacitor and ground so that the charge pump capacitor can accumulate charge, an output storage capacitor for providing inverted voltage at the voltage inverter output, an output series switch interposed between the charge pump capacitor and the output storage capacitor for controlling charge transfer to the output storage capacitor; and a grounding switch driver circuit that includes a gate drive inverter, a gate drive pulldown coupled between the charge pump capacitor and the grounding switch so as to rapidly turn off the grounding switch at the outset of the charge transfer cycle, and a gate drive isolation switch interposed between the gate drive inverter output and the gate drive pulldown and responsive to the gate drive inverter output to prevent condu

Abstract: A digitally controlled programmable attenuator maintains tight phase matching between attenuated signals over wide ranges of frequencies and power levels regardless of the selected attenuation level. This is achieved with a multi-tap ladder network that sets a desired tap-to-tap dB step-size, a plurality of unity gain digitally switched voltage-to-voltage buffers that are connected between the respective taps and a common output, and a fixed gain stage that sets the attenuator's overall gain/attenuation. The buffers maintain a high and substantially constant impedance whether turned on or turned off. Phase matching within 0.2.degree. at frequencies up to 300 MHz for 30 dB of gain variation has been realized.

Abstract: A semiconductor integrated circuit device includes a voltage drop circuit for generating a dropped voltage from a power supply voltage externally supplied to a power supply line, and a plurality of circuits respectively connected to the voltage drop circuit and driven by the dropped voltage. A switching unit, which is connected to at least one of the circuits, connects the power supply line to the above one of the circuits in synchronism with operation of the above one of the circuits. The above one of the circuits is driven by currents from both the voltage drop unit and the power supply line in synchronism with the operation thereof.