Abstract: The voltage-controlled current source receives a control voltage from an operational amplifier which itself receives a reference voltage at one input from a bias circuit. The voltage-controlled current source applies current to the base of the amplifier's main transistor. The base of the transistor is also coupled to the input node of the amplifier through a DC-blocking capacitor and through a feedback loop to the other input of the operational amplifier. The voltage-controlled current source operates to maintain the voltage at the base of the transistor relatively constant for a wide range of input signal levels. As a result, the amplifier is able to operate at relatively low power supply voltages (e.g., as low as 2V) without suffering from premature gain compression at relatively high input signal levels (e.g., as high as 0.4V).

Abstract: A drive circuit for a high-speed integrated circuit, bipolar switching regulator is disclosed. The circuit runs at megahertz frequencies, yet is efficient as previously available bipolar integrated circuit switching regulators operating at much lower frequencies. The circuitry provides three switch drive currents: a first (nominal) current that is provided while the switch is off in order to conserve power; a second (boosted) current, provided while the switch is transitioning from off to on in order to increase the speed at which the switching element switches on; and a third (drive) current, provided after the switch has turned on for maintaining the switch at a desired point in saturation. The drive current, additionally, varies as a function of the load on the switch in order, again, to conserve power. Additional circuitry increases the speed at which the switch turns off, by momentarily boosting base discharge current during the on-to-off transition period of the switch.

Abstract: A semiconductor circuit comprises an I-type of NMOS transistors N15 and N16 connected between a power supply voltage VDD and a ground electrode. The gate electrode of the NMOS transistor N15 is set to a reference voltage VREF that is lower than the power supply voltage VDD. The drain voltage VD of the NMOS transistor N16 is almost equal to the reference voltage VREF, and the NMOS transistor N16 acts in a linear region. Accordingly, the NMOS transistor N16 acts in the same manner as the resistor element and has no influence on change of the concentration of the diffusion resistor or the power supply voltage VDD.

Abstract: A semiconductor device comprises a voltage-driven switching element having a cathode and an anode, in which a voltage is to be applied between the cathode and anode, a power-supply circuit connected between the cathode and anode of the voltage-driven switching element and comprising capacitors, resistors and a reverse current-low preventing diode, for generating an intermediate voltage, a charging switching element for charging a gate of the voltage-driven switching element, using the intermediate voltage generated by the power-supply circuit, a discharging switching element for discharging the gate of the voltage-driven switching element, and a photovoltaic element for generating a photovoltaic power to control to drive the charging switching element and the discharging switching element.

Abstract: A current source circuit includes a series-circuit connected between a power source node and ground and comprising a reference current source circuit, a first transistor Q1 of an NPN type having its collector and base connected to each other and a second transistor Q2 having a multi-emitter area (N) and having a multi-emitter configuration. The current source circuit further includes a third transistor Q3 of an NPN type connected at its collector to the power source node, at its base to the base of the first transistor Q1 and at its emitter connected to the base of the second transistor and has an emitter area (M) and an input current source circuit connected between the emitter of the third transistor Q3 and ground to allow a flow of an input current Iin.

Abstract: A method and apparatus comprising a first circuit configured to generate a first output in response to a first input, a second circuit configured to present a second output in response to a second input, and a third circuit configured to generate a first voltage signal and a second voltage signal in response to the first output and said second output. The first voltage signal may be above the positive supply and the second voltage signal may be below the negative supply.

Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).

Abstract: Integrated power supply voltage generators include a boosted voltage generator which generates a boosted voltage signal (Vpp) at a first level on a boosted voltage signal line during a set-up time interval, in response to an internal power supply voltage signal (VINTA*), and a circuit which is responsive to a first reference voltage (VREFA) and the boosted voltage signal (Vpp) and generates the internal power supply voltage signal (VINTA*) at a second level which is less than the first level throughout the set-up time interval.

Abstract: A dual stage voltage level predrive circuit for an integrated circuit chip including two level shifter stages in series. The voltage level shifting circuit uses single dielectric layer devices and three bias supply circuits each providing a different DC bias voltage for distributing bias voltages among the devices such that dielectric voltage stress across single dielectric layers is reduced. The first stage of the level shifting circuit receives a first input signal having a first voltage swing, converts the first voltage swing to a second voltage swing and provides a first output signal corresponding to the first input signal and having the second voltage swing. The second stage of the level shifting circuit receives the first output signal from the first stage, converts the second voltage swing to a third voltage swing and provides a final output signal having the third voltage swing.

Abstract: The present invention relates to an internal voltage generating circuit. The internal voltage generating circuit comprises a reference voltage generating circuit for generating a reference voltage, which does not depend on an external power supply; and a comparator including a first input terminal, to which the reference voltage is supplied, a second input terminal, for comparing the voltages of the first and second input terminals and generating an output voltage according to the difference thereof at the output terminal; and an impedance element, which is selectively inserted between the output terminal and the second input terminal of the comparator according to an operation mode.

Abstract: A semiconductor memory device includes a difference adjusting circuit for detecting difference in at least one of phase and frequency between an external clock signal and an internal clock signal, for outputting a control potential for reducing the difference, and a current control circuit for adjusting driving current of an internal clock signal generating circuit in accordance with an output potential from the difference adjusting circuit. The current control circuit includes a current change restricting circuit for making smaller an amount of change of current in the clock signal generating circuit with respect to the change in the output potential from the difference adjusting circuit. An internal power supply voltage obtained by lowering internally the external power supply voltage is applied to the clock signal generating circuit. Further, when supply of the external clock signal is stopped, the output potential from the difference adjusting circuit is held.

Abstract: A semiconductor memory device is provided which uses an externally applied power supply voltage as its operating voltage. The device comprises plural memory cells each arranged in intersections of word lines and bit lines. The device further comprises an internal power supply voltage generating circuit for receiving the externally applied power supply voltage to generate an internal power supply voltage of a first level. Furthermore, the device has a plurality of word line drivers each connected to the word lines and to a power node for receiving the internal power supply voltage. The each of the word line drivers drives a corresponding word line with the internal power supply voltage in response to a word line selection signal. According to the semiconductor memory device of the present invention, a potential on the word line becomes maintained constantly at the operating voltage even though the external power supply voltage is increased.

Abstract: An internal power supply generating circuit for a semiconductor memory device reduces fluctuations in the external power supply by reducing the rate at which a drive transistor is turned on and off. The circuit includes a drive transistor that generates an internal power signal by reducing the external power supply voltage responsive to a bias signal. A feedback loop generates the bias signal and slows down the rate at which the bias signal changes, thereby reducing the rate at which the drive transistor turns on and off. The feedback loop includes a comparator for comparing the internal power supply voltage to a reference voltage and a bias circuit having a pair of push-pull transistors for generating the bias signal responsive to the output of the comparator. To slow down the rate at which the bias signal changes, the bias circuit includes a resistor coupled in series with the transistors and/or a capacitor couple to the output terminal of the bias circuit.

Abstract: A circuit for switching between supply voltages and in particular for non-volatile flash memory devices and of the type comprising a first and a second circuit branch each incorporating a pair of transistors connected in series provides that at least one branch of the circuit be structured with a bridge circuit made up of P-channel MOS transistors. The bridge is made of a first and a second pairs of transistors connected between a first supply voltage reference and a common node. The first pair comprises transistors bigger than the transistors of the second pair while between the transistors making up the second pair is inserted a pair of resistors. Between the pair of resistors there is an interconnection node connected to a corresponding interconnection node between the transistors of the first pair.

Abstract: A mixed signal processing system (22) includes digital (28) and analog (29) systems and is powered by a variable external voltage, such as a battery voltage. A voltage regulator (41) regulates the battery voltage to a nominal potential less than the battery voltage. The voltage regulator (41) provides the regulated voltage to a digital subsystem (51) of the digital system (28). A regulated charge pump (43) provides a voltage which is above the battery voltage and substantially constant due to regulation. The regulated charge pump (43) provides the regulated charge-pumped voltage to an analog subsystem (61) of the analog system (29) for better analog operation. A level shifter (44) equalizes signal levels between the digital (28) and analog (29) systems.

Abstract: A semiconductor integrated circuit is constructed with multiple stages of circuit blocks connected in vertical series between a first power supply line and a second power supply line. At least one of the circuit blocks is provided with a load unit connected in parallel therewith so that each circuit block consumes an approximately equal amount of current. This makes it possible to generate a stable intermediate voltage and suppress increases in current consumption and circuit area.

Abstract: A semiconductor integrated circuit capable of eliminating a problem of a conventional semiconductor integrated circuit in that although a power saving mode can be applied normally to a combination circuit, it cannot be applied to a sequential circuit because the sequential circuit operates abnormally in the power saving mode, eliminating its holding data, in the conventional semiconductor integrated circuit. The semiconductor integrated circuit has a controller for varying the threshold voltages of field effect transistors included in the sequential circuit so that the controller places the threshold voltages at a low level in an operating mode to speed up the data write and read, and places them at a high level in an idling mode to reduce leakage currents. This makes it possible to prevent the data held in the sequential circuit from being corrupted and eliminated, and to implement a low power consumption.

Abstract: A semiconductor integrated circuit includes an input buffer circuit that has an input terminal connected to an external signal input pad. A level-setting resistor is arranged between the input buffer circuit and a reference potential terminal having a reference potential, for holding the input terminal at the reference potential. The level-setting resistor comprises a transistor that is supplied with a control signal, and set to an off state by the control signal when the external signal input pad is in a predetermined potential state.

Abstract: The present invention provides a semiconductor integrated circuit device in which its internal node can be precharged at a high speed while suppressing current dissipation as in a conventional device by adding a circuit which assists charging when a power supply voltage begins to rise and a method for precharging. The semiconductor integrated circuit device includes a precharge circuit which comprises a first charge circuit, a second charge circuit which is higher in charging speed than the first charge circuit, a charged level detect circuit for detecting the charged level of the internal node when the first charge circuit is being driven, and a charged level stabilization circuit. The precharge circuit may further comprise a charged level control circuit.

Abstract: According to the present invention, a first voltage is generated at a drain of a first MESFET by a first stage circuit that includes a plurality of diode elements and the first MESFET with its gate and drain connected together provided between power sources. The first voltage is applied to a gate of a second MESFET that performs a source follower operation so that a constant second voltage, which is lower by the equivalent of a threshold voltage than the first voltage, is generated at the source. A third MESFET with a diode connection is provided between the second voltage source and a lower power source, and a bias voltage is generated at the drain terminal of the third MESFET. The bias voltage is supplied to the gate of a constant-current transistor, the source of which is connected to the lower power source. The current of the constant-current transistor is supplied to an SCFL circuit, the source of which is connected for common use.

Abstract: A latch-up protector, and an associated method, for an electronic circuit powered by both a fixed power supply and a pumped power supply. Operation of the latch-up protector prevents the occurrence of latch-up of the circuit during powering-up of the circuit. During powering-up of the electronic circuit, the latch-up protector prevents the application of an input signal to the electronic circuit which might instigate the occurrence of latch-up until the pumped power supply reaches a selected voltage level.

Abstract: A current reference circuit is capable of operation at a very low supply voltage, such as 1 volt. The current reference circuit is composed of a current mirror circuit, serving as an inverse PTAT (i.e., inversely proportional to absolute temperature) subcircuit, and a PTAT subcircuit for driving the current mirror circuit. The current mirror circuit and the PTAT subcircuit are mutually biased to each other. First and second constant currents produced by the PTAT subcircuit are supplied to the current mirror circuit as its reference and mirror currents, thereby cancelling the temperature coefficients of the first and second constant currents.

Abstract: A phase and base potential converter according to the invention is constructed as follows. Two MOS transistors having the same size and characteristic are connected in series between a first power supply and a second power supply, a gate of one MOS transistor is served as an input terminal of a voltage based on the first power supply, and a source of the other MOS transistor is served as an output terminal of a voltage based on the second power supply. One of the first power supply or the second power supply is a lower potential power supply, and the other is a higher potential power supply. The phase and base potential converter being thus constructed makes it possible to convert, for example, a signal based on the Vss into a signal based on the Vdd and thereby synthesize signals having different base potentials.

Abstract: A CMOS circuit (10), which is integrated in a semiconductor substrate, comprises a principal circuit part (12), which includes the major part of the circuit components in a well isolated from the substrate by a substrate diode. The CMOS circuit furthermore comprises a power output stage (16) driving an inductive load (26, 28). A sensor (18) is connected with one output (22, 24) of the power output stage (16) and on detection of a voltage biasing the substrate diode (30, 32) in the conducting direction produces a switching signal at the output. On occurrence of the switching signal produced by the sensor (18) a controllable switch (20) disconnects the supply voltage from the principal circuit part (12). In its own separate well (46) a status memory (14) is formed on the substrate adjacent to the principal circuit part (12), such status memory (14) comprising memory elements for storage of status data of the principal circuit part (12) on disconnection of the supply voltage.

Abstract: A bias circuit for a bipolar transistor includes a constant voltage source connected to a base electrode of the bipolar transistor; and a resistor connected in series between the constant voltage source and the base electrode of the bipolar transistor. By selecting an appropriate resistance for this resistor, the bias point moves due to a change in the voltage drop across the resistor. The change occurs because the base current flowing through the resistor changes, whereby the operating class of the transistor changes, resulting in a high efficiency at a desired output power.

Abstract: An intermediate potential generating circuit mainly includes an intermediate potential generating portion and an output portion. In this event, the intermediate potential generating portion generates first and second signals having first and second intermediate potentials different from each other between a first voltage source and a second voltage source and supplies the first and second signals via first and second signal terminals. Specifically, the intermediate potential generating portion has first, second, third and fourth MOS transistors. On the other hand, the output portion supplies a power supply having a third intermediate potential between the first intermediate potential and the second intermediate potential via an output terminal and is formed by fifth and sixth MOS transistors.

Abstract: A power supply switching circuit comprises first and second PMOSFETs connected in series between a writing high voltage and an output terminal in the named order, and third and fourth PMOSFETs connected in series between a reading voltage and the output terminal in the named order. A substrate potential of the first PMOSFET is connected to the writing high voltage, and a substrate potential of the third PMOSFET is connected to the reading voltage. A substrate potential of the second and fourth PMOSFETs are connected in common to a substrate potential control circuit which is configured to selectively supply either the writing high voltage or the reading voltage to the common connected sub.about.t rate potential of the second and fourth PMOSFETs.

Abstract: A CMOS voltage generator for providing a reference voltage VDD2 that will track the low level power supply voltage VDD (approximately 3.0V-3.6V) as long as the power supply is present. When VDD is not present (defined as at "hot pluggable" condition), the voltage generator is configured to maintain a "protection" output voltage less than the relatively high voltage (approximately 5V) that may appear along a circuit signal bus. In particular, the circuit includes at least a pair of diode-connected N-channel devices disposed between the signal bus line and the output voltage terminal to provide the necessary protection.

Abstract: A current mirror having a high output voltage swing and which uses only one reference current source. The current source provides an output current that is substantially equal to the reference current and, as such, does not suffer from a current offset. The current mirror achieves body-effect cancellation, permits easy scaling of current consumption and provides for fast charging and discharging of the bias lines.

Abstract: The present invention discloses an integrated constant bias voltage generator using only active devise to simulate a high impedance node, as seen from a capacitively coupled input signal. A reference current source an MOS device are coupled in series between Vcc and ground with the drain electrode of the MOS device being the constant bias voltage output. An input signal capacitively coupled to said drain electrode introduces an error current monitored by a current monitoring means. A feedback means responsive to the current monitoring means modulates the control input of the MOS device to select a IDS vs. VDS characteristic curve which will maintain the VDS voltage constant for any given IDS current, including the error current. The feedback means also compensates for voltage fluctuations in Vcc.

Abstract: A circuit and method for preventing latch-up in a CMOS semiconductor device. In an n-type substrate and p-type well region semiconductor, the method comprises the steps of pulling V.sub.sub of the substrate terminal to V.sub.CC and pulling V.sub.well of the well region terminal to V.sub.SS when V.sub.CC is below a predetermined voltage V.sub.det, and releasing V.sub.CC and V.sub.SS from respective substrate and well region terminals when V.sub.CC rises above V.sub.det. Or, if V.sub.CC is above both V.sub.det and V.sub.sub then pulling V.sub.sub to V.sub.CC and pulling V.sub.well to V.sub.SS. If V.sub.CC is above V.sub.det but below V.sub.sub then pulling V.sub.well below V.sub.SS. Similarly, in a p-type substrate and n-type well region semiconductor, the method comprises the steps of pulling V.sub.sub of the substrate terminal to V.sub.SS and pulling V.sub.well of the well region terminal to V.sub.CC when V.sub.CC is below a predetermined voltage V.sub.det, and releasing V.sub.SS and V.sub.

Abstract: An internal voltage generation circuit for a semiconductor device includes a voltage generating unit for converting the level of an external voltage in accordance with a reference voltage applied thereto, a driving unit for receiving an output signal of the voltage generating unit and an internal voltage fed back thereto and outputting a predetermined level of the internal voltage, a region detecting unit for detecting a timing point when the external voltage is lowered below the predetermined level thereof, and outputting a signal corresponding thereto, and a switching unit for supplying the external voltage to the internal voltage or interrupting the external voltage in accordance with the output signal of the region detecting unit. The circuit prevents an error operation which may occur in the semiconductor device, when the level of the external voltage is lowered.

Abstract: An MOS transistor current source has a current mirror constructed of an MOS transistor pair with the transistors having intentionally mismatched W/L aspect ratios such that the intentionally mismatched transistor pair develops a mirror current that varies in an inversely proportional fashion to the process. A precision reference current drives a first, short channel device of the pair which develops a bias voltage which is coupled to the gate terminal of a second, long channel device of the pair. The long channel device conducts a current in operative response to the bias voltage, which current will increase or decrease a corresponding amount in an inversely proportional relationship to the drive strength of the short channel device.

Abstract: A MOS integrated circuit comprising a middle potential node to which a middle potential is to be supplied, a first operation circuit operating between a first potential and the middle potential, a second operation circuit operating between the middle potential and a second potential, and a node stabilization circuit for stabilizing the potential of the middle potential node.

Abstract: The present invention comprises a noise insensitive current source circuit having a high power supply rejection ratio. The circuit of the present invention is for use with noise sensitive circuits. The circuit of the present invention includes a first reference current source, a second reference current source, and a first, second, third, and fourth transistor. The first transistor has a drain coupled to a power supply and a source coupled to a ground via the first reference current. The second transistor has a drain coupled to the power supply and a source coupled to ground via the second reference current source. The gate of the second transistor is coupled to the gate of the first transistor and to the source of the first transistor. A third transistor has a drain coupled to the power supply and a source coupled to ground via the second reference current source. The gate of the third transistor is coupled to the source of the second transistor.

Abstract: A power supply circuit, particularly a flyback converter, comprises a transformer having a secondary winding that powers a load device and/or a rechargeable battery via a rectifier diode. The secondary winding is short circuited by means of a switch connected in series with a diode. The short-circuit is detected by a measurement circuit comprising a measurement winding and a comparator which compares the amplitude variation of the voltage across the measurement winding with a threshold voltage. When a short-circuit is detected a control circuit for the control of the switching transistor of the flyback converter is changed over to a mode in which a given small current is supplied, which flows almost exclusively through the switch. As soon as the short-circuit ends the flyback converter resumes its normal mode of operation. If desired, the load device can control the desired current and/or voltage for powering the load device and charging the battery by turning on and turning off the switch.

Abstract: A current mirror model is provided for designing a continuous-time filter with reduced filter noise. The current mirror model includes an input branch having a voltage V.sub.in across a series circuit including a voltage source and a resistor of resistance value R.sub.m. The voltage source has a voltage value substantially equal to the value 4kTR.sub.m, where k is the Boltzmann constant and T is the temperature. An output branch is coupled to the input branch. The output branch has a first current source and a second current source. The first current source is controlled by the voltage V.sub.in and sources a current substantially equal to a transconductance G.sub.m of the output branch times the voltage V.sub.in. The output branch transconductance G.sub.m has a transconductance value substantially less than a value of an input branch conductance 1/R.sub.m. The second current source, coupled in parallel to the first current source, sources a current substantially equal to the value 4kTG.sub.m.

Abstract: Output buffer (100) translates input signals from one voltage range to a second voltage range. The second voltage range may be identical to the first range or may be greater. The particular range is programmable by one of several ways. This feature makes output buffer especially suitable for use in devices which must be compatible with two voltage ranges. Output buffer uses a bias generator (110) to limit the voltage across the gate oxide of its various transistors to a level which is consistent with the first voltage range.

Abstract: A voltage reference circuit capable of realization of two reference voltages having different temperature coefficients is provided. This circuit includes a first bipolar transistor, a second bipolar transistor, and first, second, and third resistors. An emitter of the first transistor is directly connected to a fixed voltage level. An emitter of the second transistor is connected to the fixed voltage level through the first resistor. A collector of the first transistor is connected to a base of the second transistor. A collector of the second transistor is connected to a base of the first transistor. A first end of the second resistor is connected to the connection point of the collector of the first transistor and the base of the second transistor. A first end of the third resistor is connected to the connection point of the collector of the second transistor and the base of the first transistor. The first transistor is driven by a first driving current through the second resistor.

Abstract: A switch open-close state-detecting circuit for supplying an interrupt signal to a control terminal of a controller in response to a change of state of a switch to either open or closed state by giving a monitoring voltage to a plurality of switches to supply a change of the monitoring voltage corresponding to opening or closing of the switches to a plurality of input terminals of the controller by detecting the change of the monitoring voltage to supply to the control terminal of the controller for controlling the operation modes of the controller. The switch open-close state-detecting circuit has a control IC including the same number of a plurality of pairs of input terminal and a plurality of output terminals for generating interrupt signals at the output terminals only when supply voltages to pairs of input terminals of the control IC are not equal, and delay circuits connected between the input terminals of the control IC.

Abstract: Spurious-emission-reducing terminal configuration for an integrated circuit, particularly a monolithic integrated circuit, operable within an unshielded board network, the integrated circuit being divided into a first subcircuit, which has essentially radio-frequency current components, and a second subcircuit, which has essentially low-frequency current components, the separation also extending to the internal supply lines and supply contact pads. The second subcircuit includes driver circuits which are connected to I/O lines on the board network. On the grounded side, the first and second supply current paths are interconnected within the integrated circuit by a low-resistance and low-inductance connection to establish a ground point.

Abstract: In order to reduce power consumption of the electronic device while it is inactive, the main switch 32 is shifted to the non-conductive state when the electronic device driven by the battery is stopped and the actuating signal decreases below a predetermined voltage, the actuating signal representing the state where the device is in operation. Thus, the power supplied to the control circuit or the like of the electronic device from the battery becomes zero, should a leak current or the like is ignored, and the power consumption can be reduced. In order to start the electronic device, the switch 34 is turned on and the main switch 32 is forced to the conductive state. That is, when the electronic device is started and the actuating signal exceeds the predetermined voltage, the main switch 32 becomes conductive and the electronic device receives power from the battery. In this state, even if the switch 34 is opened, the main switch 32 still remains conductive unless the actuating signal is stopped.

Abstract: A semiconductor integrated circuit device includes a flat-range voltage supply unit which steps down an external power supply voltage and generates a resultant, flat-range voltage, and a burn-in voltage supply unit which generates a burn-in voltage depending on the external power supply voltage. A switching unit selects either the flat-range voltage or the burn-in voltage, a selected voltage being supplied to an internal circuit. A switching instruction unit includes switches and generates a switching instruction signal by an ON/OFF control of the switches. A switching control unit controls the switching unit in accordance with the switching instruction signal.

Abstract: A programmable voltage source produces a set of output reference voltages having levels determined by a sequence of input data values, each input data value corresponding to a separate one of the reference voltages. The voltage source includes a charging current generator for generating a charging current and a set of sample and hold circuits, each corresponding to a separate one of the data values, each for producing a separate one of the output reference voltages. The charging current generator receives each data value in succession and supplies a charging current to the corresponding sample and hold circuit and that sample and hold circuit adjusts its output reference voltage by integrating the charging current. The charging current generator monitors the output reference voltage produced by that sample and hold circuit and sets the charging current to a level proportional to a difference between the reference voltage level and a level indicated by the input data.

Abstract: A capacitive multiplier circuit for an integrated circuit includes a capacitor coupled between a first node and a second node. A current source is coupled to provide a controlling current to the second node. A first current path shunts the first node and a second current path shunts the second node. The first current path is a first transistor having its conductance path connected between the first node and the substrate and its control electrode connected to the first node. The second current path is a second transistor having its conductance path connected between the second node and the substrate and its control electrode connected to the first node. The current ratio between the two current paths will be determined by the relative areas of the respective conductance paths.

Abstract: A programmable logic device (PLD) performs a self-test blank check erase verify operation on memory elements of the PLD to verify that they are erased prior to programming. An enhanced reference voltage source is provided to reliably generate a reference source voltage at a predetermined voltage level regardless of variations in the on-chip power supply voltage and temperature variations. The reference voltage source includes a first resistor connected between the on-chip voltage source and an output node, a second resistor connected to the output node, and a reference voltage adjustment circuit connected between the second resistor and ground. The reference voltage adjustment circuit is programmable to selectively connect the output node to ground through one or more resistive elements in response to input signals such that the output node is maintained at the predetermined reference voltage.

Abstract: A circuit is provided which generates a reference bias current using a difference in base-emitter voltages of two bipolar transistors imposed across a source terminal and a drain terminal of an MOS transistor. The circuit includes a circuit for compensating shifts in threshold voltage, and thus shifts in the current flowing therein, of the MOS transistor. In one embodiment, the bias circuit is configured to achieve superior efficiency in generating small bias currents. In another embodiment, the bias circuit is configured to operate using minimal voltage supplies. In all embodiments, the reference bias current generated thereby has a positive temperature coefficient and is substantially independent of process variations.

Abstract: An internal power control circuit for a semiconductor device allows easy testing of the internal circuit blocks or memory arrays at various voltage levels. In the semiconductor device, internal voltage switching circuits connected between the internal power supply line and each array power supply line are switched ON or OFF according to signals applied to control pads coupled to each internal voltage switching circuit. During normal operation, a power voltage generated by the internal voltage generator is applied through an internal power supply line to each array power supply line coupled to the internal circuit blocks. During a test operation, different power voltages may be applied to the control pads to selectively decouple individual array power supply lines from the internal power supply line, and selectively couple the power voltages applied to the control pads to the corresponding array power supply lines and internal circuit blocks.

Abstract: A power supply circuit is provided with a supplemental power source which is intermittently brought into service each time a main power source is coupled to a high power drain circuit. That is, the supplemental power source is switched to a circuit, which is susceptible to power drop, in response to switching over of the main power source to the high power drain circuit.

Abstract: The invention relates to a device for setting at stand-by a bias source through a stand-by control signal, including an inverter with an active load controlled by the bias source. The inverter includes a first p-channel MOS transistor, whose source is connected to a positive terminal of the supply voltage of the bias source, whose drain constitutes the inverter output connected to a control input of the bias source, and whose gate constitutes the input of the inverter receiving the stand-by inducing control signal.