Abstract: A voltage generation circuit includes: a first MOS transistor connected between a first power supply node and an output node, and operating in a source follower mode; a second MOS transistor connected between the output node and a second power supply node, and operating in a source follower mode; and a voltage generation section using a voltage on a third power supply node having a level greater than two times a voltage from the output node and a voltage VBB on a fourth power supply node receiving a voltage lower than a measurement reference voltage of the voltage of the output node for generating and providing to the gates of the first and second MOS transistors first and second voltages of predetermined voltage levels. The voltage generation circuit can generate a voltage of a predetermined level stably even at power supply voltage with low power consumption.

Abstract: In a semiconductor integrated circuit having an internal wiring conductor for transferring an internal signal, an intermediate voltage generator generates an intermediate voltage equal to a half of a power supply voltage, and a driver circuit receives the intermediate voltage and the internal signal, for generating to the internal wiring conductor a positive/negative pulse signal having the intermediate voltage as a reference level, in response to a rising/falling edge of the internal signal. A receiver circuit receives the positive/negative pulse signal transferred through the internal wiring conductor. An output of the receiver circuit is set in response to a positive pulse of the positive/negative pulse signal, and reset in response to a negative pulse of the positive/negative pulse signal.

Abstract: A CMOS current reference is provided that is relatively independent of supply voltage and generates a substantially steady current. The current reference includes a plurality of P-channel FETs and a plurality of zero threshold voltage N-channel FETs that provide a high level of voltage supply rejection at relatively low supply voltage levels (1.5 to 3.3 volts). Utilization of the P-channel FETs and the zero threshold voltage N-channel FETs in a current mirror and cascade configuration reduces the sensitivity of the current to variations in the supply voltage. The current reference exhibits higher offset voltage capabilities. In addition, the CMOS current reference may be designed to compensate for process variations since the current will increase as the channel length of the zero threshold voltage N-channel FETs increases.

Abstract: In an integrated circuit, a central reference generator (3) generates a setpoint signal determining the operating characteristic required to be common to some of the functional components of the circuit. Lines (4-1 to 4-n) distribute this signal among units of the circuit, each unit comprising a functional Component (2-n). In each unit, a local adjustment circuit (5-n) receives the setpoint signal and generates an adjustment value. Correction circuitry adjusts the operating characteristic of a device in the local adjustment circuit (5-n) as a function of the adjustment value. The device is placed in proximity to the functional component and configured in such a way that the operating characteristic which is thus imposed on the device is also imposed on this component.

Abstract: In a level generating circuit 1 included in an internal power supply circuit of a DRAM, MOS transistors 14 and 16 for inactivating a V.sub.1 generating circuit 3, and MOS transistors 23 and 25 for inactivating a V.sub.2 generating circuit 5 are provided. When V.sub.1 is to be adjusted, V.sub.2 generating circuit 5 is inactivated, and when V.sub.2 is to be adjusted, V.sub.1 generating circuit 3 is inactivated. Therefore, failure of adjustment of internal power supply potential intVcc caused by confusion of V.sub.1 and V.sub.2 can be prevented.

Abstract: A current source that uses a regulated constant current power source to supply current to drive a load, and the load current is controlled by shunt switches. If a plurality of loads utilize less than 50% duty factor, then one current source can drive N multiple dissimilar impedance loads, each at 100%/N duty factor. The current source includes a power converter coupled between the power source and the load(s) for providing pulsed current thereto. A current sensor is provided for sensing current flowing through the loads. A controller is coupled between the sensor and the power converter for regulating the amplitude of the output current supplied to the loads. A shunt switch is coupled across the loads, and a duty factor controller is coupled to the shunt switch for setting the duty factor of the shunt switch. A laser drive circuit, or driving light emitting diode arrays is also disclosed that include a plurality of the current sources.

Abstract: A circuit to detect the crossing of at least one voltage threshold by an input voltage of an integrated circuit has two arms mounted in negative feedback configuration, each comprising a forward biased diode in series with a current generator. The current generator of an arm is controlled in voltage by the other arm. An inverter calibrated to detect a crossing of a given threshold is connected at input to the connection point between the diode and the generator of one of the arms.

Abstract: In a power supply circuit for driving one IC chip on which first and second semiconductor circuit sections are formed integrally with each other as an IC, and wherein the first semiconductor circuit section has a delay circuit formed by an IC for giving a highly accurate delay time to a signal propagating through the delay circuit, and the delay time of the delay circuit varies with a change in the power consumption of the second semiconductor circuit section and a fluctuation in the power supply voltage which is supplied to the first semiconductor circuit section, there are provided a first power supply circuit for supplying an operating voltage to the first semiconductor circuit section and a second power supply circuit for supplying an operating voltage to the second semiconductor circuit section and for controlling to change the output voltage of the first power supply circuit.

Abstract: The dynamic range of operation of a differential transconductance input stage is reduced when the amplitude of the input signal decreases, thus reducing the level of the noise that is generated by the input stage. A DC signal representative of the sensed amplitude of the input signal is employed for either reducing the value of a common, emitter-degenerating resistance or of the bias current that is forced in the two branches of the differential input stage.

Abstract: A charge pump (40) is implemented with several stages (30), including a control stage (50), in a manner integral with a ring-oscillator loop. The charge pump (40) is more efficient for producing voltage VBB to supply to a substrate well implementing circuitry such as a DRAM or SRAM (61), since there are no threshold voltage drops across any of the critical path transistors (M3) within the charge pump (40). This is accomplished by providing a boosted signal level from the proceeding stage (30). In the design, parasitic diode leakage is negligible.

Abstract: A comparison circuit compares a reference voltage Vref from a reference voltage generation circuit with an internal power supply voltage VCI on an internal power supply line to provide a signal according to the comparison result. A drive transistor supplies current to the internal power supply line from an external power supply node according to the output signal of the comparison circuit. A resistance element connected between the external power supply node and the output node of the comparison circuit and a resistance element connected between the output node of the comparison circuit and a ground node VSS suppresses the amplitude of an output signal of the comparison circuit. Thus, overdrive of the drive transistor can be suppressed, and a current corresponding to an abrupt change of the internal power supply voltage can be supplied from the external power supply node to the internal power supply line by the amplitude limitation function.

Abstract: When an IGBT element (9) is turned off and an IGBT element (19) is turned on, capacitors (1, 2) are charged by a current successively passing through the capacitor (1), a resistive element (4), a diode (5), the capacitor (2) and an intermediate wire (32) from a high-potential dc bus (30). At the same time, a capacitor (11) is discharged by a current successively passing through a diode (17), a resistive element (16) and the capacitor (11) from a low-potential dc bus (31) to flow to the intermediate wire (32). When the IGBT element (9) is turned on and the IGBT element (19) is turned off, on the other hand, the capacitors (11, 12) are charged and the capacitor (1) is discharged. The above is so repeated as to maintain source voltages of driving circuits (8, 18) at values exceeding constant levels. Thus, a power circuit for a driving circuit is formed by a simple circuit element.

Abstract: The control circuit includes a reference MOS transistor (24) on which preermined operating characteristics are imposed. Circuitry (21, 22, 23) is provided for comparing an operating characteristic of the transistor (24) with a reference value (V.sub.tnref) so as to produce a control voltage. This voltage, after adaptation, is applied to the transistor (24) so as to fix the threshold voltage (V.sub.th) thereof, in such a way as to maintain the operating characteristics of the transistor (24). This same threshold voltage is then imposed on all the transistors of the logic circuit with which the control circuit is associated. This control circuit makes it possible particularly to reduce the consumption of said logic circuit.

Abstract: A half Vcc generating circuit generates an accurate half supply voltage with high driving power. The half Vcc generating circuit includes a bias circuit supplied with an internal supply voltage and a driving circuit supplied with an external supply voltage. The internal supply voltage is independent of and lower than the external supply voltage.

Abstract: This invention provides a semiconductor device including a circuit having a resistor element whose resistance value can be controlled via application of a control voltage, and permits the circuit to be designed stably without requiring labor and time for adjustment of the control voltage to be applied to the resistor element for precisely controlling resistance of the resistor element, and without increasing chip area. One preferred embodiment includes a reference resistor, such as a carbon film resistor or a chip resistor having a dispersion of approximately .+-.1% and having a very highly stable resistance value, and a diffused layer resistor which is used as the resistor element. The diffused layer resistor has a dispersion of approximately .+-.30% in a LSI circuit.

Abstract: Disclosed is a DC voltage generating circuit for reducing an electric power consumption in a semiconductor memory device. The DC voltage generating circuit comprises: a refresh counter for setting a refresh cycle; a power source supply controller for logically combining a counting value supplied from the refresh counter and a self-refresh timer driving signal, thereby to generate a power source supply control signal in a refresh section; and a DC voltage generator for generating and supplying a DC voltage through an output terminal of the DC voltage generator, as controlled by the power source supply control signal supplied from the power source supply controller.

Abstract: A semiconductor circuit has a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and fourth transistors are a first conduction type, and the second and third transistors are a second conduction type opposite to the first conduction type. The semiconductor circuit employs a first power supply line for supplying a first voltage, a second power supply line for supplying a second voltage, and a third power supply line for supplying a third voltage outside of the range determined by the first voltage and the second voltage. The first, second, and third transistors are connected in series between the second power supply line and the third power supply line, and the fourth transistor is connected between an input terminal and a control electrode of the first transistor.

Abstract: A driver circuit for the generation of a switching voltage, particularly a negative switching voltage, which is suitable for GaAs technology. Field effect transistors whose electric properties can vary within a wide range and ohmic resistances that do not have to be adjusted later are used. The driver circuit is particularly suited for the selection of HF components.

Abstract: A bias circuit for generating a bias voltage over variations in the power supply voltage and over process parameters is disclosed. The bias circuit utilizes a voltage divider to generate a divided voltage based on the power supply value. The divided voltage is applied to the gate of a modulating transistor (biased in saturation) in a current mirror, which controls a current applied to a linear load device biased in the linear region. The voltage across the load device determines the bias voltage. Variations in the power supply voltage are thus reflected in the bias voltage, such that the gate-to-source voltage of the series transistor is constant over variations in power supply voltage. Variations in process parameters that produce different transistor current drive characteristics are reflected in a variations of the bias voltage produced by the linear load device.

Abstract: A simple circuit arrangement for amplifying the effect of a capacitance. The input of the circuit arrangement is connected to an output of a current mirror circuit and, via the capacitance, to an input of the current mirror circuit to which a constant current (I) of known magnitude is applied. The degree of amplification of the effect of the capacitance is dependent on the area ratio n between the input transistor and the output transistor of the current mirror circuit. A constant current (n.multidot.I) is applied to the output of the current mirror circuit and is equal to the current applied to the input of the current mirror circuit multiplied by the area ratio n.

Abstract: The SHF output power and channel frequency switching apparatus having an SHF power amplifier for amplifying an SHF signal and supplying the amplified SHF output power signal to a transmitting antenna, an amplification degree control circuit for controlling the amplification degree of the amplifier, an output power change-over switch for switching a plurality of levels of the SHF output power, a channel frequency change-over switch for switching channel frequencies of the output power signal, a memory having stored therein a table of control signals which are selected to have proper values for the respective positions of each of the output power change-over switch and the channel frequency change-over switch in order that a necessary output power level can be produced each time the channel frequency change-over switch is operated to switch, a control signal supply unit for reading from the table the control signals corresponding to the output power and channel frequency specified by the SHF output power change

Abstract: In a voltage-limiting circuit, the voltage to be limited is applied to the terminals of a resistive line, and the current flowing in this line is amplified by a current mirror that thus produces a reference current. A current-controlled voltage source receives this reference current and produces a reference voltage. This reference voltage is given to a hysteresis comparator that switches over for two distinct values of the voltage to be regulated. The disclosed device is particularly useful in the field of the load pumps used in electrically programmable memories.

Abstract: A bias circuit for generating a bias voltage that tracks power supply voltage variations, and that is compensated for variations in p-channel transistor and process parameters, is disclosed. The bias circuit includes a voltage divider, such as a resistor divider, that produces a ratioed voltage based on the power supply voltage to be tracked. The ratioed voltage is applied to a first input of a differential stage, the output of which is applied to an intermediate stage including a drive transistor and a load; the second input of the differential stage receives a feedback voltage from an intermediate node that is connected to the source of a p-channel modulating transistor that has its gate biased so as to be in saturation, for example at ground. The current conducted by the p-channel modulating transistor depends upon the ratioed voltage from the voltage divider, and also on its transistor characteristics.

Abstract: In a signal transmission circuit having a plurality of signal lines for supplying potentials to load capacitances, in which each load capacitance is driven by each signal line, each signal line can be connected to another signal line via a switch. By connecting two signal lines at different potentials to each other by means of said switch, the potentials of the signal lines are changed through the process of charge redistribution, thereby eliminating charging and discharging through a power-source line and a ground line. Therefore, if n load capacitances are equal to each other, the switches are controlled so that the potential variation of each of the signal lines is phase shifted from those of its adjacent signal lines by 1/n. Thus, the load capacitances can be driven with 1/n of the total amount of charge consumed in the case of driving the n load capacitances independently, thereby reducing the consumed current.

Abstract: A power driving circuit of a thin film transistor liquid crystal display includes Darlington circuits for generating voltages corresponding to the gate driving voltages required in the displays. Analog switching circuits control the application of voltages used to form the Von and Voff driving waveforms, which have driving voltage levels generated from the Darlington circuits. The phasing of the driving waveforms is controlled by a phasing signal which is received by the analog switching circuits. The power driving circuit of the present invention consumes less power than conventional driving circuits.

Abstract: An inherently balanced electrical supply system for a bus provides improved reliability for bus termination in computer systems. The system is particularly well suited for applications such as personal computer systems. The apparatus includes a single current source that is fed into a feeder line connected to opposite ends of the bus at a point at about the center of the feeder line. The feed path is thus divided into two equal-length segments connected to opposite ends of the bus. Integrated circuit chips connected to the bus, when switched on, draw essentially equal amounts of current through each feeder segment, creating substantially equal voltage drops at both ends of the bus, minimizing the voltage difference. Alternative bus configurations are provided in embodiments of the present invention to suit various board spacing requirements.

Abstract: An amplifier circuit for amplifying a change in a resistance value of a magnetic resistance element is formed by connecting a first and a second current mirror circuits having the same structure in cascode, so that a voltage change is amplified without using a capacitive coupling. Hence, a high-pass filter is not created as a parasitic circuit, whereby a gain is maintained high in the low frequency region and a low frequency characteristic is excellent. Further, since control electrodes of transistors which form each current mirror circuit are grounded through the capacitance, a noise is reduced without using a conventional feedback circuit. This eliminates an influence of the feedback circuit over a high frequency characteristic, and therefore, a high frequency characteristic becomes excellent.

Abstract: This invention is a super voltage detection circuit that functions independent of power supply voltage. The circuit employs a reference node that is coupled to V.sub.CC through a current-limiting device. The node is also coupled to ground via a plurality of series-coupled N-channel diodes. The current-sinking capability of the series-coupled diode path is greater than the current passing capability of the current-limiting device. Thus, a reference voltage is established at the node. The reference voltage is applied to the gate of a P-channel field-effect transistor which acts as a comparator device. The source region of the comparator device is coupled to an input terminal through a plurality of series coupled N-channel diodes. A super voltage may be selectively applied to the terminal.

Abstract: A circuit arrangement which comprises at least one stage which is to be fed by a source voltage from a common voltage source, at least one of these stages comprising a control signal generating circuit which can apply a control signal, to be derived from the source voltage, to a control signal output bus conductor which is common to all stages. A control signal input bus conductor can be connected to the control signal output bus conductor via a central bridge when the source voltage has a value within a first value range and which can be isolated from the control signal output bus conductor by the central bridge when the source voltage has a value within a second value range. Each stage includes a respective control circuit which can be connected to the control signal input bus conductor in order to receive the control signal and which can adjust the stage to a source voltage from the associated value range by application or interruption of the control signal.

Abstract: The semiconductor device comprises: an internal supply voltage deboosting circuit for inputting an external supply voltage, deboosting the inputted external supply voltage, and outputting a deboosted voltage as an internal supply voltage; a first control circuit for deactivating the internal supply voltage deboosting circuit when the external supply voltage is lower than a predetermined value; and a second control circuit for outputting the external supply voltage as the internal supply voltage when the external supply voltage is lower than the predetermined value. When the external supply voltage is lower than a predetermined value, since the internal supply voltage deboosting circuit is deactivated by the first control circuit, the current consumption can be reduced. Further, since the external supply voltage is outputted as the internal supply voltage by the second control circuit, the deboosting operation is not required.

Abstract: The invention relates to a control circuit for setting a .DELTA.Vbe/R bias source at stand-by from a stand-by control signal including circuitry for virtually modifying, as a function of the state of the stand-by control signal, the emitter surface area of at least one of the matching-pair current mirror bipolar transistors in the bias source.

Abstract: An adaptive active filtering method and apparatus that detects changes in noise conditions and reduces the signal propagation speed as noise conditions worsen. This active filter has a level shifting inverter, which inverts the input signal and converts the logic levels of the input signal into chip logic levels. This inverted input signal is presented at the input of a driver inverter, which once again inverts the signal. This second inversion filters out input noise, because a voltage controlled device (which is attached to the driver inverter) reduces the switching speed of this inverter as the noise condition worsen; this reduction in switching speed reduces the propagation speed and thus filters out noise.

Abstract: A circuit to detect the crossing of at least one voltage threshold by an input voltage of an integrated circuit has two arms mounted in negative feedback configuration, each comprising a forward biased diode in series with a current generator. The current generator of an arm is controlled in voltage by the other arm. An inverter calibrated to detect a crossing of a given threshold is connected at input to the connection point between the diode and the generator of one of the arms.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: A half power supply voltage generating circuit receiving first and second power supply voltages and comprising; a bias circuit for generating first and second reference voltages in response to the first and second power supply voltages, and a driver circuit receiving the first and second reference voltages and generating a half power supply voltage, the driver circuit comprising four MOS transistors connected in series between the first and second supply voltages.

Abstract: An electrically erasable and programmable read only memory device is equipped with a supply voltage switching circuit responsive to a write enable signal for selectively supplying a write-in voltage and a read-out voltage through a power distribution line to a row address decoder unit, and the supply voltage switching circuit includes a series of first and second p-channel enhancement type field effect transistors having respective gate electrodes coupled to the write-in voltage line and the power distribution line, a third p-channel enhancement type field effect transistor having a gate electrode coupled to the power distribution line and a controlling sub-circuit responsive to the write enable signal so as to supply first and second control signals of the ground level and a third control signal of the potential level equal to the power distribution line to the first and second p-channel enhancement type field effect transistors and the third p-channel enhancement type field effect transistor when the write

Abstract: The invention relates to charge-pump circuits used for the generation, in an integrated circuit, of an internal supply voltage Vpp which is considerably greater than the external supply voltage Vcc. In a charge pump configuration with capacitors and transistors, certain transistors must be driven by bootstrapped logic signals, i.e., having a logic level which is greater than Vcc in order to overcome the threshold voltage of the transistors. According to the invention, there is an oscillator followed by a phase splitter stage which is in turn followed by a bootstrap amplifier stage. The oscillator is a ring oscillator having a number of logic gates which is as small as possible, preferably only three. A satisfactory frequency stability of the charge pump is thus obtained and therefore its design is made easier and its adaptability to various electronic circuits is improved.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: The invention relates to charge-pump circuits used for the generation, in an integrated circuit, of an internal supply voltage Vpp which is considerably greater than the external supply voltage Vcc. In a charge pump configuration with capacitors and transistors, certain transistors must be driven by bootstrapped logic signals, i.e., having a logic level which is greater than Vcc in order to overcome the threshold voltage of the transistors. According to the invention, there is an oscillator followed by a phase splitter stage which is in turn followed by a bootstrap amplifier stage. The oscillator is a ring oscillator having a number of logic gates which is as small as possible, preferably only three. A satisfactory frequency stability of the charge pump is thus obtained and therefore its design is made easier and its adaptability to various electronic circuits is improved.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage is also disclosed, and is based on a current mirror. The sum of the current in the current mirror is controlled by a bias current source, which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by improvements in various circuits and methodologies utilized in the memory. Appropriate bias levels are generated by a bias circuit for use in the output buffer according to whether a process temperature and voltage variations within the memory circuit are such that variation sensitive components will be slowed upon the occurrence of such variations. The bias circuit otherwise generates a bias signal appropriate for fast speed operations within the output buffer circuit when process temperature and voltage variations are such that they do not effect circuit speed of sensitive circuit portions. The back bias generator which operates asynchronously from the memory cycle is improved by disabling the charge pumping action during a memory cycle.

Abstract: An integrated circuit for driving an active or passive matrix liquid crystal display panel or the like provides an analog output signal which switches through a voltage range that exceeds the safe operating voltage of the CMOS transistors from which it is formed. Duplicate digital to analog conversion circuits are provided on the integrated circuit but are operated from two different power supply voltage ranges. Each voltage range has a magnitude less than the safe operating voltage. The analog output signals generated by the duplicate digital to analog conversion circuits are coupled to an output multiplexer that is responsive to a control signal for selecting one of the two analog output signals to the output terminal of the integrated circuit.

Abstract: An output driver circuit for an integrated circuit is disclosed, where the output driver drives an output terminal with a high logic level having a voltage limited from the power supply voltage of the integrated circuit. The limited voltage is provided by applying a limited output high voltage to an output buffer, such that the drive signal applied to the gate of the pull-up transistor in the output driver is limited by the limited output high voltage applied to the output buffer. A voltage reference and regulator circuit for generating the limited output high voltage, or for generating a reference voltage for application to a circuit other than an output buffer and that demands sink current, is also disclosed. The voltage reference and regulator is based on a current mirror, in which the sum of the current in the current mirror is controlled by a bias current source which may be dynamically controlled within the operating cycle or programmed by way of fuses.

Abstract: A semiconductor integrated circuit device includes a pad receiving a power supply potential and a pad receiving a ground potential both formed on a chip, and a power supply potential line and a ground potential line connected to respective pads and formed in a loop manner along a circumference of the chip. The semiconductor integrated circuit device includes a first data output circuit provided for a data output terminal proximate to a predetermined potential pad, and a second data output circuit provided for a data output terminal distant from the predetermined potential pad. First and second data output circuits drive corresponding data output terminals to the predetermined potential in two steps at a lower rate and a higher rate in accordance with an internal output data signal. First and second data output circuits include components for compensating for and canceling an influence on driving the corresponding output nodes due to the difference of distances to the predetermined pad therefrom.

Abstract: A method and circuit for tuning an equivalent resistor in a filter so that the filter is insensitive to temperature changes in which an amplifier output is connected to a common gate of plural MOSFETs for providing equivalent resistances, and in which one input to the amplifier is connected to a reference resistor and the other input to the amplifier is connected to an equivalent resistor that includes one of the plural MOSFETs. An input current to the reference resistor and to the equivalent resistor's MOSFET is inversely proportional to the MOSFET's conduction parameter, k (i.e., .mu.C.sub.ox /2), so that both the inputs to the amplifier vary to change the amplifier output voltage to the common gate. The amplifier output changes render the filter insensitive to temperature changes.

Abstract: A power supply unit including DC-DC converter using a thin and planar inductor arranged in an IC memory card incorporating an EEPROM memory chip, wherein a voltage is adjusted by a dropping regulator, thereby reducing power consumption. The thin and planar inductor includes, stacked on a semiconductor substrate, a planar coil and magnetic thin films formed to sandwich the planar coil, so that an entire area of an IC card can be decreased. The IC card can be driven by a single power supply, thus providing a compact portable information device which can be driven by a battery for a long time.

Abstract: A semiconductor integrated circuit includes memory cell blocks having memory cells arranged in matrix, sense amplifiers, each located adjacent to the memory cells, and sense amplifier control circuits, each of the sense amplifier control circuit being located on outside of the memory cell block. The sense amplifier control circuit has a standard voltage generating circuit and a control circuit for receiving the standard voltage and for transferring a driver signal to the sense amplifier to control the charging ability of the sense amplifier. The source voltage has three voltage regions, first, intermediate, and second regions. In the first voltage region, the potential of the driver signal increases with the increase of the source voltage. In the intermediate voltage region (2.7 to 3 Volt), the potential of the driver signal is changed oppose to the change of the source voltage, and in the second voltage region, the potential of the driver signal decreases with the increase of the source voltage.

Abstract: A unit for stabilizing the voltage on a capacitive node of a memory array, such as a common node bit line (CNBL), is disclosed. The unit includes an amplifier connected to the CNBL line and to one voltage source and a leaker connected to the CNBL line and to the other voltage supply, where the two voltage supplies can be the positive and ground supplies. The leaker is much smaller then the amplifier thereby to remove current from the CNBL line when there is little or no activity in The memory array. An alternative version of the unit which is also operative for standby operation is disclosed. In this embodiment, there is a switchable high power unit activatable during an active mode and a low power unit. Both units include an amplifier and a leaker connected as in the previous embodiment. The leakers are much smaller then the amplifiers and the amplifier of the high power unit is much larger than the amplifier of the low power unit.

Abstract: A power supply for an integrated circuit has a piecewise linear operating characteristic for improved integrated circuit testing and screening. In an integrated circuit that receives an externally applied power signal, designated V.sub.CCX, and includes a power supply for generating an internal operating voltage, designated V.sub.CCR, an on-chip power supply circuit provides V.sub.CCR as a piecewise linear function of V.sub.CCX. In a first segment of such a function, V.sub.CCR approximates V.sub.CCX for efficient low voltage operations. In a second segment, used for normal operations of the integrated circuit, V.sub.CCR rises gradually with V.sub.CCX so that test results at the edges of the segment can be guaranteed with a margin for measurement tolerance, process variation, and derating. In a third segment, V.sub.CCR follows below V.sub.CCX at a predetermined constant offset. Transitions between segments are smooth due to nonlinear devices used in the power supply circuitry.