Abstract: A driving circuit such as for driving pixels of an LCD includes first and second digital-to-analog converters respectively coupled to receive first and second digital input values. The outputs of the first and second digital-to-analog converters are connected to first and second output transistors, the outputs of which are connected together to a driving voltage output terminal. A predetermined voltage is applied to the gate of each output transistor. The first and second digital-to-analog converters and their associated output transistors correspond to upper and lower ranges of output voltage. During a display cycle, one digital-to-analog converter receives a digital value to be output as a driving voltage, while the other digital-to-analog converter receives a digital value to be output as a voltage that renders its associated output transistor nonconductive.

Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. The active digital voltage regulator circuit uses the stored energy to supplement the local power supply voltage during times when the local power supply voltage starts to collapse, e.g., during periods when inductive losses are preventing the power supply from maintaining the local power supply voltage. Consequently, digital active voltage regulator circuit smooths the local power supply voltage by greatly ameliorating the ripple voltages associated with parasitic inductances and resistances. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits.

Abstract: A trimming circuit, the resistance of which can be increased or decreased. The trimming circuit has a first circuit, which includes a first resistor and a Zener diode connected in parallel to the first resistor, and a second circuit, which includes a second resistor and a fuse connected in parallel to the second resistor. The second circuit is connected in series to the first circuit. The resistance of the trimming circuit is decreased by performing trimming with the Zener diode and is increased by performing trimming with the fuse.

Abstract: A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt.

Abstract: A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.

Abstract: A semiconductor device comprises a voltage-down circuit for generating an internal power supply voltage obtained by lowering an external power supply voltage in a chip; and a chip internal circuit applied with the internal power supply voltage obtained in the voltage-down circuit, wherein the voltage-down circuit includes a first circuit connected at one end to an external power supply, a second circuit connected between the other end of the first circuit and the internal circuit, for creating the internal power supply voltage, and a capacitor connected to a connection node of the first circuit and the second circuit and to a ground node of the chip internal circuit, and the capacitor is charged by the first circuit when a current flowing in the second circuit is smaller than a preset value and supplies a discharge current to the second circuit when the current flowing in the second circuit is larger than the preset value.

Abstract: Semiconductor device according to the present invention includes package frame, bonding wire, pad, first internal power supply line, second internal power supply line, internal circuit, stabilize circuit, GND package frame, GND bonding wire, GND pad, and internal GND line. Bonding wire, pad, and first and second internal power supply lines and function as a filter. As a result, noise generated by operation of internal circuit is absorbed in propagating to stabilize circuit through first internal power supply line, pad, and second internal power supply line. Therefore, effects of noise given to stabilize circuit is small.

Abstract: A DRAM includes a first power source section for supplying a higher operational voltage in an active mode and a lower waiting voltage in a waiting mode to a data processing section through a source line, a compensating capacitor connected to the source line for alleviating the fluctuations on the source line, a second power source section for supplying the operational voltage to the compensating capacitor, and a switch for coupling the source line to the compensating capacitor in the active mode.

Abstract: A circuit for addressing leakage. The circuit may have a variable supply stage having an active load in parallel with a switch transistor where the active load and the switch transistor are coupled to a decoupling capacitor. The circuit may also have a leakage detect stage having a leak device coupled to a critical node. An embodiment of the circuit may have a supply node; an input node; an output node; a buffer stage where the buffer stage supply node is coupled to a variable supply stage output, the buffer stage input is coupled to the input node and the buffer stage output is coupled to the output node; a leakage detect stage where the leakage detect stage supply node is coupled to the supply node and the leakage detect stage input is coupled to the input node; and a variable supply stage where the variable supply stage supply node is coupled to the supply node and the variable supply stage input is coupled to the leakage detect stage output.

Abstract: A low supply voltage for operating an operational amplifier operating as a voltage follower is derived from a high voltage source. Two npn transistors, two Zener diodes and a current source are connected in series across the high voltage source. The input voltage (to the operational amplifier) plus a Zener reference voltage is applied to the base of the transistor near the positive terminal of the high voltage source. Then, a low positive supply voltage V+ nearly equal to the input voltage plus the Zener voltage (Vi+Vz) is derived at the emitter. This low positive supply voltage V− is derived by dropping V+ through the two series Zener diodes to obtain a low negative supply voltage equal to (Vi−Vz).

Abstract: A liquid crystal display makes it possible to reduce the current consumption and to prevent abnormal writing to a liquid crystal. A liquid crystal display driver of the liquid crystal display comprises: a shift register inputting a clock signal CLK; a data register inputting display data DR, DG and DB and outputs control signals DRc, DGc and DBc; and a latch, a DAC and an output amplifier inputting strobe signals respectively. This output amplifier makes output power only for amended source lines higher, based on the output power control signals DRc, DGc and DBc indicating whether the source line is being amended or not.

Abstract: The invention relates to an impedance control output circuit of a semiconductor device and a method relevant thereto to prevent or minimize various problems caused by a transmission error by automatically resetting the impedance mismatch resulting from variances of supply voltage, temperature, other operational conditions.

Abstract: The present invention relates to a bias circuit for biasing a depletion mode power transistor. The bias circuit includes a voltage offset circuit and a transistor, where the voltage offset circuit is serially coupled between the gate terminal of the depletion mode power transistor and the drain terminal of the transistor. The bias circuit generates a bias voltage that, when applied to the gate terminal of the depletion mode power transistor, maintains a substantially constant drain current through the power transistor over a range of threshold voltages caused by process and temperature variations.

Abstract: A common mode bias voltage generator apparatus and method includes a plurality of MOSFET-based transistors and a plurality of resistors configured and arranged to provide a half of a supply voltage with a predetermined low output impedance while using relatively little power and circuit area.

Abstract: A semiconductor integrated circuit device and a contactless electronic device are provided with a power supply circuit producing a stable smooth voltage with high efficiency for stable operation of an inner circuit. An AC voltage is applied to first and second input terminals and a rectification transistor having drain (or collector) connected to second input terminal and gate (or base) and drain (or collector) connected to each other through resistor supplies a rectified current between the first and second input terminals. The first voltage detection means produces control voltage so that the rectified voltage obtained on the source (or emitter) side of the first rectification transistor is equal to the predetermined reference voltage. The first voltage controlled current source can produce current in accordance with the control voltage and supply the current to the first resistor means. Such power supply circuit is mounted in the contactless electronic device.

Abstract: A semiconductor memory device for a package-state voltage test has a plurality of bonding pads that are electrically connected to an external device in a package state, at least one internal DC voltage generator, at least one switch connected between one of the bonding pads and the internal DC voltage generator. The switch is on during a test mode and is off during a normal mode. The switch controller is connected between at least two of the plurality of bonding pads and serves to control the switch in response to an external switching signal in the test mode. Because of this design, a number of DC voltage tests can be performed without increasing chip size since a general control pad also serves as a DC voltage test pad.

Abstract: An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).

Abstract: A high performance high input voltage input buffer manufacture using a low voltage process contains an input buffer circuit (136) and a level shifter (132). The input buffer (136) will receive an input signal via a chip pad (112). The input signal from trip pad (112) will be provided to an inverter stack (135) that contains or is coupled to protection transistors (116, 114, 110, and 111). The protection transistors are biased by a reference generator (134) which outputs a voltage that is a function of the maximal voltage that can be provided on the chip pad (112). By using the circuit (134), the trigger point of the inverter stack (135) can be dynamically adjusted for any OVDD (110) value whereby input buffer performance is improved and made more flexible.

Abstract: There is described a BiCMOS switch circuit which allows a low voltage CMOS signal to control a bipolar current source or sink circuit. The circuit includes a current mirror circuit, drawing a constant current through a first bipolar transistor. The collector of that transistor is connected firstly through a second bipolar transistor to a circuit output, and secondly through a CMOS transistor to a positive voltage supply. Depending on an input control signal supplied to the gate of the CMOS transistor, that device can be switched on or off. When the CMOS transistor is switched off, the constant current through the first bipolar transistor is drawn through the circuit output. When the CMOS transistor is switched on, the constant current through the first bipolar transistor is drawn through the CMOS transistor, and the output current is zero.

Abstract: A constant-voltage generation circuit is provided which creates a constant voltage. The constant-voltage generation circuit may consist of a first voltage creation circuit for creating a reference voltage and a second voltage creation circuit for creating a constant voltage which has a predetermined relationship with the reference voltage. The first voltage creation circuit may consist of a constant-current source for supplying a constant current and a voltage-control transistor through which this constant current flows, for outputting the reference voltage on the basis of a predetermined potential. The constant current is set to a value within the saturated operating region of the voltage-control transistor.

Abstract: An IC comprises a pair of circuit nodes, a current mirror that includes dual-function transistor, and a controller for switching the transistor between a pair of states. In a first state, the transistor provides current gain and also provides a relatively high impedance between the nodes, and in a second state, it provides no current gain and a relatively lower impedance between the nodes.

Abstract: A connecting arrangement includes a number of NMOS transistors that can be activated or deactivated by means of a control voltage, serving as a control signal, connected to the gate terminals of transistors, to be able to form a circuit connected between two conductors, the circuit presenting resistive properties. The circuit is equipped with a signal receiver and it is regulated by an analog control voltage. The control voltage is connectable to one or several of a number of available control connections. Each control connection is connected to the gate terminals of a group of transistors where the drain and source terminals are connected to the conductors. The control voltage is selected so that the operating point of the transistors will be within, or at least close to, the region where the transistor presents resistive properties.

Abstract: A boost circuit for a ferroelectric memory operated in a low voltage supply environment is achieved by floating a local supply voltage and using a single boost via one or more appropriately sized ferroelectric boost capacitors to elevate the local supply level to the desired boosted voltage. When boosting is not required, the local supply voltage is tied to the system external power supply through an appropriately sized PMOS transistor.

Abstract: A system and method for a supply-independent VCO biasing scheme for generating bias voltages and currents for a VCO of a phase-locked loop are disclosed A biasing scheme for generating a bias electrical signal comprises a first and second current source coupled to a power supply, a current drain coupled to the second current source and to ground, a replica device having a first node, a second node coupled to the second current source and the current drain, and a third node coupled to ground, and a first and second current splitting device having first nodes coupled to each other and to the current source and having third nodes coupled to the first and second nodes of the replica device, respectively.

Abstract: The invention relates to a voltage reference source used to control an overvoltage tolerant input/output buffer for a mixed voltage bus system. The voltage source comprises a voltage tracking circuit having a first input receiving a variable voltage. and a second input receiving a reference voltage. the voltage tracking circuit being adapted to generate an output voltage in response to the difference between the variable voltage and the reference voltage. wherein where the variable voltage is less than the reference voltage. the output voltage is held at substantially zero volts. When the variable voltage exceeds the reference voltage. the output tracks the voltage at the variable voltage input.

Abstract: To reduce current consumption, there is provided a circuit for each bank, comprising selection circuits 26 through 28 each for selecting either a normal supply voltage Vii or a higher supply voltage Vjj as a supply voltage VH0 in response to a selection control signals SC0 and *SC0, a selection control circuit 22 for generating the signals SC0 and *SC0 to make the selection circuits select Vii when a bank activation signal BRAS0 is inactive and Vjj for a predetermined period in response to activation of BRAS0, and sense amplifier driving circuits 111 through 113 for supplying the ground voltage and VH0 to the sense amplifier rows in response to activation of sense amplifier control signals. To stabilize the output voltage Vii of the power supply circuit having a NMOS transistor, the drain electrode, gate and source electrodes of which are at VCC, VG and approximately Vii=VG−Vth, where Vth is the threshold voltage of the NMOS transistor 45, a leak circuit is employed.

Abstract: The present invention relates to a circuit for generating a reference voltage trimmed by an anti-fuse programming, comprising: reference voltage generation means for providing a reference voltage having a predetermined level; decoding means generating for decoding signals in order to trim a level of said reference voltage according the anti-fuse programming; and voltage trimming means for dividing said reference voltage using resistance variable in response to said decoding signals supplied from said decoding means, thereby trimming the level of said reference voltage. The present invention programs the anti-fuses on the basis of the voltage signals applied through the bonding pads to generate the decoding signals, and thereafter divide the reference voltage using the resistance variable in response to the decoding signals, thereby capable of minutely trimming the level of the reference voltage from the reference voltage generation means.

Abstract: There is provided a gray scale display reference voltage generating circuit that can change a gamma correction characteristic in accordance with a liquid crystal material and LCD panel characteristics. Resistor elements R0 through R7 have a resistance ratio for gamma correction and generate gamma-corrected intermediate voltages on the basis of voltages across both input terminals V0 and V64. A gamma correction adjustment circuit 42 adjusts the gamma-corrected intermediate voltages upward or downward on the basis of adjustment data latched in a data latch circuit 43. By thus supplying the adjustment data corresponding to the liquid crystal material and the LCD panel characteristics to the data latch circuit 43, the gamma correction characteristic can be changed in accordance with the liquid crystal material and the LCD panel characteristics without modifying the design of a source driver.

Abstract: A semiconductor integrated circuit device comprises a first switching element, such as a p-channel MOSFET, capable of connecting said first power supply with a first power supply line, a second switching element, such as an n-channel MOSFET, capable of connecting said second power supply with a second power supply line, a first voltage drop circuit connected between said first power supply and said first power supply line, a second voltage drop circuit connected between said second power supply and said second power supply line, and a sequential circuit connected between said first and second power supply lines and comprised of p-channel MOSFETs and n-channel MOSFETs, substrate terminals of the p-channel MOSFETs being connected to said first power supply and substrate terminals of the n-channel MOSFETs being connected to said second power supply.

Abstract: A method and circuits are provided for high speed powerup of an analog reference source, such as used in a direct access storage device (DASD). The high speed powerup circuits for the analog reference source include a biasing current source. Biasing circuitry is provided for establishing a first bias reference voltage level. An enable input is provided for disabling and for enabling powerup of the analog reference source. A transistor switch is coupled between the bias reference voltage level and the analog reference source. The transistor switch is operatively controlled by the enable input for driving the analog reference source and enabling fast powerup of the analog reference source.

Abstract: First and second buffer circuits generate first and second reference potentials. A switching circuit selects a first reference potential as a reference potential while a sense operation is not performed and selects a lower second reference potential while the sense operation is performed. A buffer circuit is controlled such that a through current increases only for a predetermined time period at a initiation and a termination of the sense operation.

Abstract: A control device having a forced operation function has an output circuit that operates in response to an output control signal generated within the control device and a terminal for feeding a signal from the output circuit to outside the control device. The control device further has a signal detection circuit that outputs a forced operation signal when a predetermined signal is fed from the outside to that terminal. The output control signal generated within the control device and the forced operation signal produced by the signal detection circuit are fed through an OR circuit to the output circuit. This circuit configuration makes it possible to reduce the number of terminals to be provided in a control device having a forced operation function and thereby reduce its costs.

Abstract: A reference voltage generation circuit includes: a load unit having one end thereof connected to a higher voltage power supply line; an enhancement type n-channel MIS transistor having a drain thereof connected to the other end of the load unit, and a source thereof connected to a lower voltage power supply line; and a source follower circuit using a MIS transistor has a driving element, the source follower circuit having an input end thereof connected to the drain of the n-channel MIS transistor and having an output end thereof connected to a gate of the n-channel MIS transistor. A reference voltage is obtained at the drain of the n-channel MIS transistor. By the constitution, it is possible to obtain a stable reference voltage, and to incorporate the reference voltage generation circuit into an integrated circuit produced by integrating MIS transistors, without introducing an increase in production processes. It is also possible to reduce a consumed current of the reference voltage generation circuit.

Abstract: A reference voltage generating circuit with MOS transistors having a floating gate is disclosed. The reference voltage generating circuit has first and second MOS transistors in which substantially the same current flows by means of a current mirror circuit. The differential voltage between the threshold voltages of the first and second MOS transistors is applied from the source of the first transistor as the reference voltage. The first and second transistors are of a construction that includes a floating gate, and the threshold voltage can be set to any value by means of the amount of charge injected to the floating gate.

Abstract: A synchronous rectifier MOSFET control circuit which overcomes many of the shortcomings of the prior art employs MOSFET for supplying voltage to a load when the MOSFET is in the forward biased condition (i.e., when an input voltage level exceeds the threshold voltage level by a pre-determined amount). The MOSFET control circuit is configured to turn off the MOSFET when the input voltage level dips below that pre-determined level required to maintain the MOSFET in the forward biased condition. When the MOSFET is turned off, the diode internal to the MOSFET device prevents current flow in the reverse bias direction (i.e., the internal diode prevents current flow from the output to the input), effectively isolating the load from the input voltage source, thereby allowing the capacitors to discharge their energy to the load to maintain a voltage supply to the load which is at or above the output load threshold voltage level.

Abstract: A constant voltage circuit is made up of a first transistor of an N-channel type having a drain connected to a power supply voltage and a source connected to the drain of the respective memory cells, a second transistor of an P-channel type having a source connected to the power supply voltage, a gate connected to a ground, and a drain connected to a gate of the first transistor, and a reference voltage generating circuit turning on and fixing the gate of the first transistor to the predetermined voltage when the power supply voltage is more than a predetermined voltage. Accordingly, the constant voltage circuit can apply a high voltage for the output voltage Vmcd to drains of each memory cells even if the power supply voltage Vcc is a low voltage and further can achieve the improvement of the access velocity for the data reading operation of the semiconductor memory device.

Abstract: The current mirror circuit in accordance with the present invention includes a first current mirror circuit composed of first and second MOS transistors being cascade connected to a second current mirror circuit composed of third and fourth MOS transistors. Further, an NPN transistor is interposed between the gate and the drain of the third MOS transistor to which an input current is supplied. Thus, the third MOS transistor can operate normally even with a higher input voltage than in a case where the drain is connected to the gate by as much as the base-emitter voltage of the NPN transistor. In addition, even if the input current is in an off state, electric charge always flows out via the gates of the first and second MOS transistors as the base current of the NPN transistor. Thus, a current mirror circuit can be offered with high precision in output current and a short rise-time when changed from an on state to an off state, while maintaining a wide input voltage range.

Abstract: A semiconductor device for outputting a reference voltage, the value of which changes depending on the ambient temperature, and a crystal oscillator device comprising the semiconductor device. The semiconductor device comprises at least one depletion MOS transistor having an overall conductivity coefficient KDO and at least one enhancement MOS transistor having an overall conductivity coefficient KEO, wherein KDO does not equal KEO and the transistors are connected in series. Thus, the semiconductor device provides an output reference voltage having a predetermined temperature characteristic which can be effectively controlled in accordance with the ambient temperature. The semiconductor device is employed in a two-level housing or in a one-level housing package so that the crystal oscillator device can have a small size and is produced easily. Also disclosed is a method of producing the crystal oscillator device.

Abstract: A Norton equivalent implementation of a fail safe bias circuit drives a bus to provide a stable bias voltage which is not affected by an output impedance of a current source. The Norton equivalent implementation has first current source, a bias resistor and a current sink in series. The bias resistor is connected across a pair of differential bus lines so that the current flowing through the bias resistor causes a bias voltage to be generated between the bus lines. The current to the bias resistor is selectively switched on and off to control the bias voltage so that the bias voltage can be turned off during high speed data transfers on the bus.

Abstract: A circuit comprising a positive switch and a steering network. The positive switch may be configured to present a first and a second switch signal in response to a first select signal. The steering network may be configured to present a high voltage output that may transition between a very high positive and a very low negative voltage, where the transition may respond to a high positive voltage input, a low negative voltage input, a first and second switch signal, and a second select signal.

Abstract: The present invention concerns an output buffer circuit with a switchable common mode output voltage level. An output buffer circuit according to the invention comprises a plurality of output stages (1,2) for driving a symmetrical transmission line (RT). A power supply circuit (U1,U2) provides an upper power supply potential (Vbh) and a lower power supply potential (Vbl) for the output stages (1,2). The power supply circuit is adapted to provide the lower power supply potential (Vbl) at different levels in accordance with a configuration signal (En). Depending on the configured lower power supply potential (Vbl) of the output stages (1,2) at least one of the output stages is activated or inactivated in order to compensate the effect of the lower power supply potential (Vbl) on the output impedance of the output stages (1,2).

Abstract: A voltage supply generator for a semiconductor memory improves the reliability of the erasing operation. A Vcc voltage detecting unit detects an intensity of a Vcc voltage, which is an external power source, to provide first and second Vcc voltages. A charge pump circuit receives the Vcc voltage and provides a VNEG voltage. A clock circuit applies a clock pulse to the charge pump circuit. A voltage regulating circuit receives the first and second Vcc voltages to monitor and control the VNEG voltage and provides a constant VNEG voltage.

Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

Abstract: A low power consumption component which operate at a high frequency is provided by separating out those critical signal paths which acquire a higher voltage to operate below a maximum propagation delay requirement and operating the remainder of the devices of the component at a lower power supply to minimize overall power consumption of the component.

Abstract: An isolation mechanism serves to isolate digital signal processor outputs from a dynamic random access memory controller upon the occurrence of a low power condition. The isolation prevents corruption of dynamic random access memory due to low power. The isolation mechanism receives inputs of a first low power indicator and a second low power indicator. The first low power indicator pulls low and the second low power indicator is forced high when a low power condition exists. One embodiment of the isolation mechanism includes a NAND gate connected to a first low power indicator signal and to a second low power indicator signal as inputs, a NOR gate connected with a NAND gate output as input, and a flip flop connected with a NOR gate output and the first low power indicator as inputs. The flip flop output is input to the NOR gate.

Abstract: An analog process/voltage/temperature (PVT) compensated buffer includes a differential amplifier providing a first output signal indicative of a difference between an input signal and a reference signal. The input signal is compatible with a first type of logic. An active gain stage is coupled to translate the first output signal to a second output signal. The second output signal is compatible with a second type of logic. The differential amplifier and the active gain stage are coupled to receive a process/voltage/temperature (PVT) compensation signal. In one embodiment, the first type of logic is Gunning Transceiver Logic (GTL) and the second type of logic is complementary metal oxide semiconductor (CMOS) logic.

Abstract: A reference voltage generating circuit generates a reference voltage having a flat temperature characteristic over a practical temperature range. In a reference voltage transistor pair, a depletion N-channel field effect transistor and an enhancement N-channel field effect transistor are connected in series between a first voltage source and a second voltage source so that the reference voltage is output from a juncture between a gate of the depletion N-channel field effect transistor and a gate of the enhancement N-channel field effect transistor. A temperature characteristic correction circuit is provided to at least one of the depletion N-channel field effect transistor and the enhancement N-channel field effect transistor. The temperature characteristic correction circuit changes temperature sensitivity of the reference voltage by changing an effective gate size of the one of the depletion N-channel field effect transistor and the enhancement N-channel field effect transistor.

Abstract: In an LSI circuit, respective voltages on power-source lines connected to the respective sources of transistors which are turned OFF in a circuit block in the standby state are controlled by a power-source-voltage control circuit to vary in response to variations in the threshold voltages of the transistors. Consequently, the differential voltage (Vgs-Vt) between the gate-to-source voltage Vgs of each of the transistors and the threshold voltage Vt thereof is held constant at a given value, so that an OFF-state leakage current flowing through the transistor in the circuit block in the standby state is reduced and held constant at a given value. What results is a reduction in the power consumption of the circuit block in the standby state.

Abstract: A reference circuit includes a first resistive element and a current source. The first resistive element is adapted to produce an output voltage based on a first current and a resistance of the first resistive element. The resistance of the first resistive element is a function of a temperature of the current. The current source includes a second resistive element that has a resistance that is a function of the temperature. The current source is adapted to adjust the first current to minimize variation of the output voltage with the temperature based on the resistance of the second resistive element.

Abstract: An electrical circuit provides a variety of stable and reliable bias voltages to accommodate the bias requirements of various sensor types. The electrical circuit comprises a programmable analog circuit capable of maintaining a plurality of programmable threshold voltages and producing a plurality of intermediary voltages. Such voltages act as an input to a differential amplifier that outputs a bias voltage within a range consistent with said programmable threshold voltages. The bias voltage is further conditioned by a conditioning amplifier that further stabilizes the bias voltage to an attached sensor.