Abstract: A cryogenic electronic package includes a first superconducting multi-chip module (SMCM), a superconducting interposer, a second SMCM and a superconducting semiconductor structure. The interposer is disposed over and coupled to the first SMCM, the second SMCM is disposed over and coupled to the interposer, and the superconducting semiconductor structure is disposed over and coupled to the second SMCM. The second SMCM and the superconducting semiconductor structure are electrically coupled to the first SMCM through the interposer. A method of fabricating a cryogenic electronic package is also provided.

Abstract: A method of processing a wafer includes a laser beam applying step of applying a laser beam to the wafer to form modified layers in the inside of the wafer along division lines and to extend device layer splitting cracks from the modified layers to the front surface of the wafer. After the laser beam applying step is performed, a cutting step of cutting the wafer is performed by a cutting blade from the back surface side to form cut grooves and to remove the modified layers. Therefore, the modified layers are not left on chips, and the die strength of the chips is enhanced.

Abstract: A flexible touch sensing unit includes a substrate including a plane region and a bending region, a plurality of sensing electrodes disposed on the substrate, a plurality of sensing lines surrounding the plurality of sensing electrodes and electrically connected to the plurality of sensing electrodes, and a damage prevention layer disposed in the bending region. Cracks on the sensing electrodes and the sensing lines which are disposed in the bending region may be prevented by the damage prevention layer in the bending region. A resulting flexible display device using the flexible touch sensing unit may be thinner by omission of a flexibility enhancing layer.

Abstract: A method for fabricating a semiconductor package is provided. Semiconductor dice are disposed on a top surface of a carrier. Each of the semiconductor dice has an active surface and a bottom surface that is opposite to the active surface. Input/output (I/O) pads are distributed on the active surface. Interconnect features are printed on the carrier and on the active surface of each of the semiconductor dice. The top surface of the carrier, the semiconductor dice and the interconnect features is encapsulated with an encapsulant. The carrier is then removed.

Abstract: A slider includes a reader element, a bottom shield located adjacent to the reader element, a top shield located adjacent to the reader element, a heater, a substrate located below the reader element, the top shield, the bottom shield and the heater, and a cap substantially surrounding the reader element, the top shield, the bottom shield and the heater. The cap includes a base coat layer comprising a first electrically insulative cap material adjoining the substrate, and an overcoat layer comprising a second electrically insulative cap material adjoining the base coat layer opposite the substrate. The base coat layer and the overcoat layer meet at an interface located at or below the top shield. The first and second electrically insulative cap materials are different.

Abstract: A semiconductor device chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a semiconductor device disposed on the first surface of the semiconductor substrate, an interconnect pattern having an end connected to the semiconductor device and another end exposed on a surface of a function layer disposed on the first surface of the semiconductor substrate, plurality of external connection electrodes mounted on the surface of the function layer and electrically connected to the other end of the interconnect pattern, an electromagnetic wave shield film for shielding electromagnetic waves, which is disposed on the second surface of the semiconductor substrate and side surfaces of the function layer, and a ground interconnect electrically connected to the electromagnetic shield film and disposed on the function layer.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and a first protective layer surrounding the semiconductor die. The chip package also includes a second protective layer over the semiconductor die and the first protective layer. The chip package further includes an antenna element over the second protective layer. The antenna element is electrically connected to the conductive element of the semiconductor die.

Abstract: An embodiment of the present invention describes a method for forming a doped region at a first major surface of a semiconductor substrate where the first doped region being part of a first semiconductor device. The method includes forming an opening from the first major surface into the semiconductor substrate and attaching a semiconductor die to the semiconductor substrate at the opening. The semiconductor die includes a second semiconductor device, which is a different type of semiconductor device than the first semiconductor device. The method further includes forming a chip isolation region on sidewalls of the opening and surrounding the second semiconductor device, and singulating the semiconductor substrate.

Abstract: Embodiments disclosed herein provide for a circuit including first die having an active side and a backside, wherein the first die is flip-chip mounted to a carrier. The circuit also includes a second die stacked on the backside of the first die, wherein the second die is stacked on the first die such that a backside of the second die is facing the backside of the first die and an active side of the second die faces away from the first die.

Abstract: A semiconductor package includes a substrate including at least one mounted electronic device; a sealer disposed to seal the electronic device; and a conductive blocking film disposed on a surface of the sealer and a side surface of the substrate, wherein the substrate includes a spacer formed along an outer edge of a lower surface of the substrate to space the side surface of the substrate and the lower surface of the substrate to be apart from each other.

Abstract: In a semiconductor element of the present invention, an electroless nickel-phosphorus plating layer and an electroless gold plating layer are formed on both a front-side electrode and a back-side electrode of a front-back conduction-type substrate. The front-side electrode and the back-side electrode are formed of aluminum or an aluminum alloy. The proportion of the thickness of the electroless nickel-phosphorus plating layer formed on the front-side electrode with respect to the thickness of the electroless nickel-phosphorus plating layer formed on the back-side electrode is in a range of 1.0 to 3.5. The semiconductor element of the present invention allows the occurrence of voids inside solder during mounting by soldering to be prevented.

Abstract: An electronic component, an electronic component manufacturing apparatus, and an electronic component manufacturing method are provided which enable an electromagnetic wave shielding film formed on a package to achieve an excellent shielding characteristic. An electronic component 10 includes an electromagnetic wave shielding film 13 formed on the top face of a package sealing elements. The thickness of the electromagnetic wave shielding film 13 on the top face of the package 12 is 0.5 to 9 ?m, and the relationship between the average height Rc of the roughness curvature factor of the top face of the package 12 and the thickness Te of the electromagnetic wave shielding film 13 is Rc?2Te.

Abstract: Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.

Abstract: A semiconductor integrated circuit device includes: an insulating substrate; a via which penetrates through the insulating substrate; a first metal layer disposed on a front surface of the insulating substrate; a first resist layer disposed on the first metal layer in the vicinity of the via; a solder layer disposed on the first metal layer, the via and the first resist layer; a gap region formed between the solder layer and the first resist layer, and a semiconductor integrated circuit disposed on the solder layer.

Abstract: The electronic device comprises a semiconductor chip comprising a first main face, a second main face opposite to the first main face, side faces connecting the first and second main faces, and a sensor element or actuator element disposed at the first main face, and a substrate, wherein the semiconductor chip is disposed above the substrate, the first main face of the semiconductor chip facing the substrate, wherein the substrate comprises a substrate opening, the substrate opening permitting passage of signals to the sensor element or from the actuator element.

Abstract: Conventional package for integration of MEMS and electronics suffer from profiles that are undesirably high to due to the thickness of the glass. Also in conventional package manufacturing, the MEMS and electronic devices are first individualized, and the individualized MEMS and electronics are combined into a package, and thus can be costly. To address these and other disadvantages, a panel level packaging is proposed. In this proposal, plural MEMS devices are integrated with plural semiconductor devices at a panel level, and the panel is then individualized into separate packages.

Abstract: An electronics package includes a lower insulating layer, an upper insulating layer coupled to the lower insulating layer, and a conductive contact pad coupled to a second surface of the upper insulating layer. An electrical component is positioned within an opening formed through the upper insulating layer. A first interconnect layer extends through at least one via in the lower insulating layer to electrically couple with at least one contact pad on the electrical component and a second interconnect layer extends through at least one via in the upper insulating layer and electrically couples the first interconnect layer to the conductive contact pad.

Abstract: An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated circuit. The I/O cells may each include a bond pad formed in one or more top metal layers. One or more of the bond pads may be offset a predetermined distance from an I/O cell edge corresponding to a chip edge of the integrated circuit. A volume may be determined by the I/O cell edge and the predetermined distance and one or more rails may be disposed in the volume and in at least one metal layer common with at least one metal layer of the bond pad. The rails may be involved in the discharge of electrostatic discharge (ESD) current, and may reduce path resistance of the path used to discharge the ESD current.

Abstract: An example device includes a silicon substrate having a first substrate surface and a second substrate surface; a plurality of layers associated with one or more electronic components of an integrated circuit (IC), where the plurality of layers are deposited on the second substrate surface; a lithium-based battery having a plurality of battery layers deposited on the first substrate surface of the silicon substrate, where the lithium-based battery includes an anode current collector and a cathode current collector; a first through-silicon via (TSV) passing through the silicon substrate and providing an electrical connection between the anode current collector and the plurality of layers associated with the one or more electronic components of the IC; and a second TSV passing through the silicon substrate and providing an electrical connection between the cathode current collector and the plurality of layers associated with the one or more electronic components of the IC.

Abstract: The printed circuit board, according to one embodiment, comprises: an insulation substrate; a pad formed on at least one side of the insulation substrate; a protection layer which is formed on the insulation substrate and exposes an upper surface of the pad; and a bump formed on the pad exposed by the protection layer, wherein the bump comprises a plurality of solder layers having melting points different from each other.

Abstract: The present invention relates to a gas sensor package including an insulating substrate, a metal layer on one surface of the insulating substrate, a stepped portion disposed on the metal layer and configured to divide the metal layer into a plurality of portions, and a gas sensor chip mounted on the metal layer located on the stepped portion and including a sensing part, wherein a width of the stepped portion is provided to be equal to or less than an interval between two adjacent electrode terminals of a plurality of electrode terminals of the gas sensor chip.

Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

Abstract: A device includes a metal pad at a surface of an image sensor chip, wherein the image sensor chip includes an image sensor. A stud bump is disposed over, and electrically connected to, the metal pad. The stud bump includes a bump region, and a tail region connected to the bump region. The tail region includes a metal wire portion substantially perpendicular to a top surface of the metal pad. The tail region is short enough to support itself against gravity.

Abstract: A semiconductor device includes a substrate; a semiconductor layer; a first protective film; a first adhesive layer disposed on the first protective film; an electrode pad disposed on the first protective film; a second protective film disposed to cover and be in contact with the electrode pad and the first adhesive layer; and a first opening formed in part of the second protective film such that the upper surface of the electrode pad is exposed, wherein in a plan view, the first adhesive layer includes a first projection projecting from the electrode pad radially in a direction of the periphery of the electrode pad and continuously surrounding the periphery of the electrode pad; and the second protective film is continuously to cover and contact part of the upper and side surfaces of the electrode pad, the upper and side surfaces of first projection, and the first protective film.

Abstract: A semiconductor package includes a first semiconductor device provided on a support substrate; a first encapsulation material covering the first semiconductor device; a first line provided on the first encapsulation material, the first line being connected with the first semiconductor device; an intermediate buffer layer covering the first line, and a second encapsulation material provided on the intermediate buffer layer. The first encapsulation material and the second encapsulation material are each formed of an insulating material different from an insulating material used to form the intermediate buffer layer. A second semiconductor device covered with the second encapsulation material may be provided on the intermediate buffer layer.

Abstract: Bottom terminated components and methods of making bottom terminated components are provided. The bottom terminated component includes a die paddle and at least one die paddle structure configured to prevent wicking into a respective thermal via of a printed circuit board. The at least one die paddle structure includes a base defining an axis, the base having an axial thickness extending from the die paddle, and a contact surface configured to contact the printed circuit board at the thermal via of the printed circuit board to prevent wicking of solder into the respective thermal via.

Abstract: A medical device with structure elements is made by providing a substrate; optionally depositing a layer of a sacrificial material on the substrate; and applying of a photoresist layer to the substrate. The layer of sacrificial material and structuring of the photoresist layer according to the shape of the structure elements are produced such that first free spaces are formed which are open on the side facing away from the substrate and are delimited by side faces of the photoresist layer. An angle is set between the side faces and the substrate. Sacrificial material is deposited in the first free spaces so first mask elements from sacrificial material are adapted to the inner contour of the first free spaces. The photoresist layer is removed so that second free spaces are formed between the first mask elements.

Abstract: Optoelectronic devices and method of forming the same include an optoelectronic chip in a substrate layer, the optoelectronic chip having one or more optoelectronic components. An integrated circuit chip is positioned on the substrate layer. A lens array is positioned on the substrate layer above the optoelectronic chip and above at least part of the integrated circuit chip. The lens array includes one or more lens positioned directly respective optoelectronic components.

Abstract: Optical sensor packages include a substrate assembly such as a leadframe or semiconductor substrate. One or more optical devices are mounted to the substrate assembly. One or more optical overlays are disposed (e.g., stacked) on the active side of the optical device(s), and mounted to the device(s) using an adhesive layer. In embodiments, the optical devices may comprise optical sensors (e.g., photodetector such as phototransistors or photodiodes), light sources (e.g., light emitting diodes (LED), combinations thereof, and so forth. A mold layer is formed over the substrate assembly, proximate to the optical device and optical overlay so that an outer surface of the optical overlay is exposed.

Abstract: Methods and apparatus are described for creating a multi-die package from a wafer without dicing the wafer into individual dies and reassembling the dies on an interposer. One example method generally includes testing a plurality of IC dies disposed on a wafer; disposing one or more connectivity layers above the plurality of IC dies, the one or more connectivity layers comprising one or more electrical conductors configured to connect together two or more of the plurality of dies in each of one or more groups of the IC dies; dicing the wafer having the one or more connectivity layers disposed above the plurality of dies into sets, each set comprising one or more of the plurality of dies, wherein the dicing is based on the one or more groups having IC dies that passed the testing; and packaging at least a portion of the sets of dies.

Abstract: A wafer having on one side a device area with devices partitioned by division lines is divided into dies. An adhesive tape for protecting the devices is attached to the one side of the wafer, and a carrier for supporting the adhesive tape is attached to the outside of the adhesive tape. The other side of the wafer is ground to adjust the wafer thickness, and a protective layer is applied to the ground side of the wafer. The side of the wafer opposite to the adhesive tape is mechanically partially cut along the division lines with a first cutting width. A remaining part of the wafer, in the thickness direction thereof in the region or regions where the partial cut or cuts had been formed, is cut with a second cutting width. The second cutting width is smaller than or equal to the first cutting width.

Abstract: A method for manufacturing a semiconductor package structure includes: (a) disposing at least one semiconductor element on a conductive structure, wherein the conductive structure includes at least one insulation layer and at least one circuit layer; (b) disposing an encapsulant on the conductive structure to cover the semiconductor element; (c) attaching a supporting structure on the conductive structure to surround the semiconductor element; and (d) disposing an upper element on the encapsulant, wherein a coefficient of thermal expansion of the upper element is in a range of variation less than or equal to about ±20% of a coefficient of thermal expansion of the circuit layer, and a bending modulus of the upper element is in a range of variation less than or equal to about ±35% of a bending modulus of the circuit layer.

Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure and a dielectric structure. The conductive structure has a first conductive surface and a second conductive surface opposite to the first conductive surface. The dielectric structure covers at least a portion of the conductive structure, and has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The first conductive surface does not protrude from the first dielectric surface, and the second conductive surface is recessed from the second dielectric surface. The dielectric structure includes, or is formed from, a photo-sensitive resin, and the dielectric structure defines a dielectric opening in the second dielectric surface to expose a portion of the second conductive surface.

Abstract: A system for decapsulating a portion of an encapsulated integrated circuit that includes copper elements has one or more containers holding specific etchant solutions, a pump having an inlet port connected to the one or more containers holding specific etchant solutions, and an outlet port, a temperature-controlled metal block having a fluid inlet connected to the pump outlet port, and an outlet port from the block, and control circuitry enabling control of temperature of the metal block and operation of the pump, and flow and temperature sensors coupled to the control circuitry. Etchant temperature at the outlet of the metal block is controlled to be at or below ambient temperature by controlling the pump and temperature of the metal block, and etchant mixture is delivered via a delivery conduit to an encapsulation surface of an encapsulated integrated circuit, decapsulating a portion of encapsulated circuit, minimizing damage to the copper elements.

Abstract: The present disclosure relates to a semiconductor element, a manufacturing method of a semiconductor element, and an electronic apparatus, which enable suppression of crack occurrences and leaks. The present technology has a laminated structure including an insulating film having a CTE value between those of metal and Si and disposed under a metal wiring, and P—SiO (1 ?m) having good coverage and disposed as a via inner insulating film in a TSV side wall portion. As the insulating film having a CTE that is in the middle between those of metal and Si, for example, SiOC is used with a thickness of 0.1 ?m and 2 ?m respectively in the via inner insulating film and a field top insulating film continuous to the via inner insulating film. The present disclosure can be applied to, for example, a solid-state imaging element used in an imaging device.

Abstract: The present invention relates to a method for handling an ultra-thin glass for a display panel and, more specifically, the invention enables the ultra-thin glass to be easily attached to or detached from a carrier glass for supporting the ultra-thin glass before and after a surface treatment process for applying the ultra-thin glass to a display panel. To this end, the method for handling an ultra-thin glass for a display panel, according to the present invention, comprises: a bonding step for bonding an ultra-thin glass and a carrier glass for supporting the ultra-thin glass by means of a phase transition material; a surface treatment step for treating a surface of the ultra-thin glass; and a separation step for separating the ultra-thin glass from the carrier glass.

Abstract: A digital x-ray detector has a non-metallic housing. A two dimensional array of photosensors enclosed by the housing is in electrical communication with an electrical circuit formed on an interior surface of the housing.

Abstract: In some embodiments, integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate are presented.

Abstract: A microelectronic component arrangement includes a sensor and a carrier. The sensor has a detection surface and a region including contact elements situated at a first distance with respect to one another. The carrier includes a mounting surface, and the sensor is fixed on the carrier by the contact elements situated at a first distance with respect to one another at least regionally. The detection surface is opposite the mounting surface in a manner having a second distance with respect to the mounting surface. The contact elements are wetted by a mechanically stabilizing material, the region including the contact elements is enclosed by the mechanically stabilizing material, and the detection surface is free of the mechanically stabilizing material.

Abstract: A head including a channel formation substrate is provided with a pressure generating chamber which communicates with a nozzle for ejecting a liquid; a piezo element includes a first electrode which is provided on one surface side of a channel formation substrate, a piezoelectric layer is provided on the first electrode, and a second electrode is provided on the piezoelectric layer; and a driving circuit board is bonded to the one surface side of the channel formation substrate via an adhesive layer, and is provided with a driving circuit for driving the piezo element, in which the piezo element and the driving circuit are electrically connected to each other via a bump which is provided on any one of the channel formation substrate and the driving circuit board, and in which the bump and the adhesive layer are provided above the piezoelectric layer of the piezo element.

Abstract: A sensor package comprises a carrier comprising a through hole, and a sensor chip with a front side and a back side and a recess in the back side. The sensor chip is attached to the carrier with its back side facing the carrier by means of an attachment layer thereby defining a first area of the carrier the sensor chip rests on and a second area of the carrier facing the recess. The through hole is arranged in the first area of the carrier.

Abstract: A wiring board is provided, wherein electrical function of the wiring board is normal, the wiring board has a front side, a reverse side opposite to the front side, an opening and an interconnection layer, the opening penetrates the wiring board and connects the front side and the reverse side, and the interconnection layer is located on the front side and extends toward the opening. A component is bonded to the wiring board, wherein electrical function of the component is normal, the component has an active surface, a back surface opposite to the active surface, and a working area located on the active surface, the active surface is bonded to the interconnection layer, the component is located in the opening, and the active surface and the front side of the wiring board face in a same direction. An encapsulant is filled into the opening, so as to cover the component and expose the working area.

Abstract: A chip packaging structure includes a flexible circuit board, a first built-up structure, a second built-up structure, and a first solder resist layer. The flexible circuit board defines a bent area and a laminated area. The flexible circuit board includes a first dielectric layer. The first dielectric layer includes a first conductive pattern, a bearing layer opposite to the first conductive pattern and corresponding to the laminated area. The first built-up structure is located on the first conductive pattern and corresponds to the laminated area, and includes a second dielectric layer and a second conductive pattern electrically connected with the first conductive pattern. The second built-up structure is located on the bearing layer and corresponds to the laminated area, and includes a third dielectric layer and a third conductive pattern electrically connected with the first conductive pattern. The first solder resist layer covers the second conductive pattern.

Abstract: An electronic device is manufactured by a method including applying a photosensitive adhesive agent either to a pressure chamber forming substrate and a vibrating plate or to a sealing plate having a structure of a lower height from a bonding surface, precuring the photosensitive adhesive agent by heating, patterning the precured photosensitive adhesive agent, and bonding the substrates together with the structure (bump electrode) and the photosensitive adhesive agent interposed therebetween.

Abstract: Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a trench in a substrate, the trench being formed within a first side of the substrate and disposed around a portion of the substrate. A first insulating material is formed over the first side of the substrate and the trench, and a second insulating material is formed over the first insulating material. Apertures are formed in the second insulating material and the first insulating material over the portion of the substrate. Features are formed in the apertures, and a carrier is coupled to the features and the second insulating material. A second side of the substrate is planarized, the second side of the substrate being opposite the first side of the substrate. The second insulating material is removed, and the carrier is removed.

Abstract: An electronic assembly includes a Light Emitting Diode (LED) and a substrate. The LED has a solderable surface other than the contacts. The substrate has an opening. The solderable surface is mounted substantially over the opening. When the opening is filled with solder, the solderable surface is metallically bonded with the solder in the opening.

Abstract: A manufacturing method of ultra-thin semiconductor device package structure is provided. Firstly, a wafer including a plurality of semiconductor devices is provided, and one of the semiconductor devices has an active surface having an active region and an outer region and a back surface. A first electrode and a second electrode are arranged in the active region, and the outer region has a cutting portion and a channel portion. Subsequently, a trench is formed in the channel portion, and filled with a conductive structure. The wafer is fixed on a supporting board, and then a thinning process and a deposition process of a back electrode layer are performed on the back surface in sequence. Thereafter, the supporting board is removed and a plurality of contacting pads is formed. A cutting process is performed along the cutting portion.

Abstract: Disclosed are a light emitting device package and a lighting system. The light emitting device package includes a first cavity in a first region of the body; a second cavity in a second region of the body; first and second lead frames spaced apart from each other in the first cavity; a third lead frame spaced apart from the second lead frame in the second cavity; a first light emitting device on the first and second lead frames in the first cavity; a second light emitting device on the second and third lead frames in the second cavity; and a molding member in the first and second cavities.

Abstract: A substrate structure including a carrier and a substrate is provided. The carrier includes a release layer, a dielectric layer and a metal layer. The dielectric layer is disposed between the release layer and the metal layer. The substrate includes a packaging region and a peripheral region. The peripheral region is connected to the packaging region and surrounds the packaging region. The peripheral region or the packaging region has a plurality of through holes. The substrate is disposed on the carrier. The release layer is located between the substrate and the dielectric layer. The release layer and the dielectric layer are filled in the through hole such that the substrate is separably attached to the carrier.

Abstract: A substrate plate is provided for at least one MEMS device to be mounted thereon. The MEMS device has a certain footprint on the substrate plate, and the substrate plate has a pattern of electrically conductive leads to be connected to electric components of the MEMS device. The pattern forms contact pads within the footprint of the MEMS device and includes at least one lead structure that extends on the substrate plate outside of the footprint of the MEMS device and connects a number of the contact pads to an extra contact pad. The lead structure is a shunt bar that interconnects a plurality of contact pads of the MEMS device and is arranged to be removed by means of a dicing cut separating the substrate plate into a plurality of chip-sized units. At least a major part of the extra contact pad is formed within the footprint of one of the MEMS devices.