Abstract: A fabrication method of a trenched metal-oxide-semiconductor device is provided. After the formation of the gate dielectric layer, a first poly-silicon layer is deposited along the profile of the gate trench. Then, impurities of first conductivity type are implanted to the first poly-silicon layer at the bottom of the gate trench. Then, a second poly-silicon layer with second conductivity type is deposited over the first poly-silicon layer. The impurities in the first poly-silicon layer and the second poly-silicon layer are then driven by an annealing step to form a first doping region with first conductivity type located at the bottom of the gate trench and a second doping region with second conductivity type.

Abstract: A MOSFET on SOI device includes an upper region having at least one first MOSFET type semi-conductor device formed on a first semi-conductor layer stacked on a first dielectric layer, a first conductive layer and a first portion of a second semi-conductor layer. A lower region includes at least one second MOSFET type semi-conductor device formed on a second portion of the second semi-conductor layer, a gate of the second semi-conductor device being formed by at least one conductive portion. The second semi-conductor layer is arranged on a second dielectric layer stacked on a second conductive layer.

Abstract: In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern.

Abstract: A capacitor structure includes a plurality of lower electrodes on a substrate, the lower electrodes having planar top surfaces and being arranged in a first direction to define a lower electrode column, a plurality of lower electrode columns being arranged in a second direction perpendicular to the first direction to define a lower electrode matrix, a plurality of supports on upper sidewalls of at least two adjacent lower electrodes, a dielectric layer on the lower electrodes and the supports, and an upper electrode on the dielectric layer.

Abstract: The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node dielectric layer located between the outer electrode and the inner electrode. The vertical transistor is located over the trench capacitor and comprises a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The channel region of the vertical transistor is located in a tensilely or compressively strained semiconductor layer that is oriented perpendicularly to a surface of the semiconductor substrate. Preferably, the tensilely or compressively strained semiconductor layer is embedded in an insulator structure, so that the vertical transistor has a semiconductor-on-insulator (SOI) configuration.

Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor under bit line (CUB) structure capable of increasing a gap between a bit line in a cell area and an upper plate of a capacitor, reducing coupling capacitance therebetween, and forming deep contacts in a logic area. A capacitor including a lower electrode, a dielectric material layer, and an upper electrode is formed in an opening of a first insulating layer for exposing a first part of a semiconductor substrate in a cell area. A second insulating layer is formed on the first insulating layer. The first and second insulating layers are etched. First and second contact plugs are formed in first and second contact holes for exposing second and third parts in the cell area and the logic area. A third insulating layer including first through third conductive studs is formed on the second insulating layer.

Abstract: A semiconductor device with a dielectric structure and a method for fabricating the same are provided. A capacitor in the semiconductor device includes: a bottom electrode formed on a substrate; a first dielectric layer made of titanium dioxide (TiO2) in rutile phase and formed on the bottom electrode; and an upper electrode formed on the first dielectric layer.

Abstract: A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer.

Abstract: Provided is a semiconductor integrated circuit device including a capacitor element with an improved TDDB life. A semiconductor integrated circuit device (1) includes: a first electrode (4) including a first semiconductor layer which protrudes with respect to a plane of a substrate; a side surface insulating film (5) formed on at least a part of a side surface of the first electrode (4); an upper surface insulating film (6) formed on the first electrode (4) and the side surface insulating film (5); and a second electrode (7) which covers the side surface insulating film (5) and the upper surface insulating film (6). The first electrode (4), the side surface insulating film (5), and the second electrode (7) constitute a capacitor element. A thickness of the upper surface insulating film (6) between the first electrode (4) and the second electrode (7) is larger than a thickness of the side surface insulating film (5) between the first electrode (4) and the second electrode (7).

Abstract: A method of manufacturing a dynamic random access memory cell includes: forming a substrate having an insulating region over a conductive region; forming a fin of a fin-type field effect transistor (FinFET) device over the insulating region; forming a storage capacitor at a first end of the fin; and forming a back-gate at a lateral side of the fin. The back-gate is in electrical contact with the conductive region and is structured and arranged to influence a threshold voltage of the fin.

Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.

Abstract: A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a patterned second mask layer in a predetermined region for formation of a capacitor. A plurality of hemispherical grain structures are formed on a sidewall of the patterned second mask layer. The first mask layer is etched by using the hemispherical grain structures and the patterned second mask layer as a mask, thereby forming a patterned first mask layer having a pattern. The pattern of the first mask layer is transferred to the bottom electrode material layer. And, a capacitor dielectric layer and a top electrode layer are formed on the bottom electrode material layer to form the capacitor.

Abstract: An upper electrode of a capacitor has a two-layer structure of first and second upper electrodes. A gate electrode of a MOS field effect transistor and a fuse are formed by patterning conductive layers used to form the lower electrode, first upper electrode and second upper electrode of the capacitor. In forming a capacitor and a fuse on a semiconductor substrate by a conventional method, at least three etching masks are selectively used to pattern respective layers to form the capacitor and fuse before wiring connection. The number of etching masks can be reduced in manufacturing a semiconductor device having capacitors, fuses and MOS field effect transistors so that the number of processes can be reduced and it becomes easy to improve the productivity and reduce the manufacture cost.

Abstract: A semiconductor fin having a doping of the first conductivity type and a semiconductor column are formed on a substrate. The semiconductor column and an adjoined end portion of the semiconductor fin are doped with dopants of a second conductivity type, which is the opposite of the first conductivity type. The doped semiconductor column constitutes an inner electrode of a capacitor. A dielectric layer and a conductive material layer are formed on the semiconductor fin and the semiconductor column. The conductive material layer is patterned to form an outer electrode for the capacitor and a gate electrode. A single-sided halo implantation may be performed. Source and drain regions are formed in the semiconductor fin to form an access transistor. The source region is electrically connected to the inner electrode of the capacitor. The access transistor and the capacitor collectively constitute a DRAM cell.

Abstract: An IrOx film of a thickness of 50 nm is formed on a PZT film by a sputtering method. The value of x is less than 2. Namely, an unsaturated iridium oxide film is formed. By performing RTA, the PZT film is completely crystallized. Thereafter, an IrOY film of a thickness of 50 nm to 100 nm is formed on the IrOX film by a sputtering method. The composition of IrOY is made a composition closer to the stoichiometric composition of IrO2 than the composition of IrOX (X<Y?2). This is because by adopting such a composition, the catalytic action to hydrogen is suppressed, the problem of the PZT film being reduced by hydrogen radicals is suppressed and hydrogen endurance of the ferroelectric capacitor is enhanced. An SrXRuYO3 film in an amorphous state with a thickness of about 20 nm is formed on IrOY film by a sputtering method.

Abstract: A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.

Abstract: Disclosed are methods and systems for improving cell-to-cell repeatability of electrical performance in memory cells. The methods involve forming an electrically non-conducting material having ordered porosity over a passive layer. The ordered porosity can facilitate formation of conductive channels through which charge carriers can migrate across the otherwise non-conductive layer to facilitate changing a state of a memory cell. A barrier layer can optionally be formed over the non-conductive layer, and can have ordered porosity oriented in a manner substantially perpendicular to the conductive channels such that charge carries migrating across the non-conductive layer cannot permeate the barrier layer. The methods provide for the manufacture of microelectronic devices with cost-effective and electrically reliable memory cells.

Abstract: Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.

Abstract: An integrated circuit includes a memory cell arrangement with a plurality of active regions along a first direction, a plurality of parallel buried word lines (BWL) along a second direction, a plurality of parallel bitlines along a third direction, and a plurality of storage capacitors. The BWLs run through the active regions. Two of the BWLs are spaced apart from one another and from isolation trenches running through a respective active region, the BWLs being insulated from a channel region by a gate dielectric. The bit lines run perpendicular to the second direction, wherein each bit line makes contact with the relevant source region of the associated active region. The first direction lies between the second and third directions. Storage capacitors are connected to associated drain regions in a respective active region.

Abstract: A semiconductor component has an insulating layer which is formed on a semiconductor substrate and in which a capacitance structure (K) is formed. The capacitance structure (K) has at least two metallization planes (1 to 7) which are arranged parallel to one another and are each connected to an electrical connecting line. Arranged between the metallization planes (1 to 7) is at least one electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) for producing a capacitance surface, the electrically conductive region (1a to 1j; 2a to 2j; 31a to 36a; 41a to 46a; 5a to 5f) being electrically connected only to one of the metallization planes (1 to 7).

Abstract: A method for forming a semiconductor device of the present invention solves problems in a process for forming a fin type gate including a recess region, such as, a complicated process, low production margin, and difficulty in forming an accurate fin shape. In a process for forming an isolation dielectric film defining an active region, a nitride film pattern is formed in such a manner that the size of the nitride film is adjusted according to line width of a fin portion in a fin type active region formed in a subsequent process step, and an isolation dielectric film is formed in every region except for the nitride film pattern of a semiconductor substrate. Then, a recess is etched, and the isolation dielectric film is removed from a region where the line width of the nitride film pattern was reduced to a certain degree.

Abstract: A semiconductor storage device, has a first conductive type semiconductor region formed on a semiconductor substrate, a plurality of second conductive type semiconductor regions formed separately from each other on the first conductive type semiconductor region, a plurality of MOSFETs each formed on the plurality of second conductive type semiconductor regions, and element isolating regions each formed between the adjacent second conductive type semiconductor regions, a bottom surface of which being located in the first conductive type semiconductor region, wherein the number of crystal defects per unit volume in the first conductive type semiconductor region is larger than the number of the crystal defects per unit volume in the second conductive type semiconductor regions.

Abstract: A seed film and methods incorporating the seed film in semiconductor applications is provided. The seed film includes one or more noble metal layers, where each layer of the one or more noble metal layers is no greater than a monolayer. The seed film also includes either one or more conductive metal oxide layers or one or more silicon oxide layers, where either layer is no greater than a monolayer. The seed film can be used in plating, including electroplating, conductive layers, over at least a portion of the seed film. Conductive layers formed with the seed film can be used in fabricating an integrated circuit, including fabricating capacitor structures in the integrated circuit.

Abstract: A semiconductor device includes a memory cell region and a peripheral circuit region. The memory cell region includes a first region and a second region surrounding the first region. The first region includes a plurality of first electrodes, a plurality of first support portions, and a second support portion. The plurality of first electrodes upwardly extends. The plurality of first support portions upwardly extends along the plurality of first electrodes. Each of the plurality of first support portions mechanically supports corresponding one of the plurality of first electrodes. The second support portion contacts with the plurality of the first support portions. The second support portion connects between each of the plurality of first electrodes.

Abstract: A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface.

Abstract: A method includes forming a lower dielectric layer on a semiconductor substrate, forming a bit line landing pad and a storage landing pad that penetrate the lower dielectric layer, covering the lower dielectric layer, the bit line landing pad, and the storage landing pad with an intermediate dielectric layer, forming an upper dielectric layer on the intermediate dielectric layer, partially removing the upper dielectric layer and the intermediate dielectric layer to form a contact opening that exposes the storage landing pad and a portion of the lower dielectric layer, forming a contact spacer on an inner wall of the contact opening, and filling the contact opening with a contact plug, a top surface of the contact plug larger than a surface of the contact plug that is in contact with the storage landing pad, the top surface of the contact plug eccentric in relation to the storage landing pad.

Abstract: A memory cell that includes a first contact having a first surface and an opposing second surface; a second contact having a first surface and an opposing second surface; a memory material layer having a first surface and an opposing second surface; and a nanoporous layer having a first surface and an opposing second surface, the nanoporous layer including at least one nanopore and dielectric material, the at least one nanopore being substantially filled with a conductive metal, wherein a surface of the nanoporous layer is in contact with a surface of the first contact or the second contact and the second surface of the nanoporous layer is in contact with a surface of the memory material layer.

Abstract: A method for manufacturing an electrolyte material layer with a chalcogenide material incorporated or deposited therein for use in semiconductor memory devices, in particular resistively-switching memory devices or components. The method comprises the steps of producing a semiconductor substrate, depositing a binary chalcogenide layer onto the semiconductor substrate, depositing a sulphur-containing layer onto the binary chalcogenide layer, and creating a ternary chalcogenide layer comprising at least two different chalcogenide compounds ASexSy. One component A of the chalcogenide compounds ASexSy comprises materials of the IV elements main group, e.g., Ge, Si, or of a transition metal, preferably of the group consisting of Zn, Cd, Hg, or a combination thereof.

Abstract: A method of forming a contact structure includes forming an isolation region defining active regions in a semiconductor substrate. Gate patterns extending to the isolation region while crossing the active regions are formed. A sacrificial layer is formed on the semiconductor substrate having the gate patterns. Sacrificial patterns remaining on the active regions are formed by patterning the sacrificial layer. Molding patterns are formed on the isolation region. Contact holes exposing the active regions at both sides of the gate patterns are formed by etching the sacrificial patterns using the molding patterns and the gate patterns as an etching mask. Contact patterns respectively filling the contact holes are formed. The disclosed method of forming a contact structure may be used in fabricating a semiconductor device.

Abstract: An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the semiconducting substrate, and a capacitor (130) at least partially embedded in the semiconducting substrate. The capacitor includes a first electrode (131) and a second electrode (132) that are electrically isolated from each other by a first electrically insulating material (133). The first electrode is electrically connected to the semiconducting substrate and the second electrode is electrically connected to the source/drain region of the transistor.

Abstract: A semiconductor memory device includes a semiconductor layer; a source layer and a drain layer in the semiconductor layer; an electrically floating body region in the semiconductor layer between the source layer and the drain layer, accumulating or discharging charges for storing logical data; a gate dielectric film on the body region; and a first gate electrode and a second gate electrode on one body region via the gate dielectric film, the first and the second gate electrodes separated from each other in a channel length direction of a memory cell comprising the drain layer, the source layer, and the body region.

Abstract: A decoupling capacitor is formed on a semiconductor substrate that includes a silicon surface layer. A substantially flat bottom electrode is formed in a portion of the semiconductor surface layer. A capacitor dielectric overlies the bottom electrode. The capacitor dielectric is formed from a high permittivity dielectric with a relative permittivity, preferably greater than about 5. The capacitor also includes a substantially flat top electrode that overlies the capacitor dielectric. In the preferred application, the top electrode is connected to a first reference voltage line and the bottom electrode is connected to a second reference voltage line.

Abstract: An improved method for forming a capacitor. The method includes the steps of: providing a metal foil; forming a dielectric on the metal foil; applying a non-conductive polymer dam on the dielectric to isolate discrete regions of the dielectric; forming a cathode in at least one discrete region of the discrete regions on the dielectric; and cutting the metal foil at the non-conductive polymer dam to isolate at least one capacitor comprising one cathode, one discrete region of the dielectric and a portion of the metal foil with the discrete region of the dielectric.

Abstract: A metal-insulator-metal capacitor structure includes a lower electrode, a buffer layer, a barrier layer, a dielectric layer and an upper electrode. The lower electrode is disposed in the buffer layer. The barrier layer covers part of the lower electrode and is disposed between the lower electrode and the upper electrode. The buffer layer serves as an etching stop layer to define the dielectric layer. The dielectric layer in the metal-insulator-metal capacitor structure has a uniform and ideal thickness.

Abstract: A first MOS transistor includes, as a first impurity region, a pair of first source/drain regions including first portions formed in a semiconductor substrate and second portions formed so as to project upward from the first portions. A second MOS transistor includes a pair of second source/drain regions including second impurity regions formed in the semiconductor substrate, third impurity regions located in contact with the second impurity regions so as to project upward from the semiconductor substrate, and fourth impurity regions located on the third impurity regions. The concentration of impurities in the third impurity regions is lower than that of impurities in the fourth impurity regions. The concentration of impurities in the first impurity regions is lower than that of impurities in the second impurity regions. The first, the second, the third and the fourth impurity regions are same conductivity type.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer 148 located over a gate electrode layer 143, a capacitor 170 located on the recrystallized polysilicon layer 148. The capacitor 170, in this embodiment, includes a first electrode 173, an insulator 175 located over the first electrode 173, and a second electrode 178 located over the insulator 175.

Abstract: A deep trench metal-insulator-metal (MIM) capacitor in an SOI-type substrate. In the deep trench, a layer of TiN, followed by a layer of high-k dielectric, followed by a second layer of TiN. The resulting capacitor is completely buried below the SOI layer, thereby allowing for subsequent structures to be placed over the deep trench.

Abstract: A method of fabricating an integrated circuit device storage cell may include forming a channel region comprising a semiconductor material doped to a first conductivity type; forming a store gate structure comprising a semiconductor material doped to a second conductivity type in contact with the channel region; and forming a control gate terminal from at least a portion of a semiconductor layer deposited on a substrate surface in contact with the channel region, the portion of the semiconductor layer being doped to the second conductivity type.

Abstract: In order to form a storage electrode of a semiconductor memory device, an interlayer dielectric layer is formed on a semiconductor substrate having a bit line thereon. A contact hole exposing the semiconductor substrate is formed by patterning the interlayer dielectric layer. A polysilicon layer is etched to a predetermined thickness using polysilicon etching gas after the polysilicon layer is deposited. An over-etch process is performed relative to the polysilicon layer, and then a storage node contact having a planarized surface is formed in the contact hole by performing an etching process for planarizing the surface of the polysilicon layer. A mold insulating layer is formed on the resultant structure, in which the mold insulating layer exposes an area where the storage node contact is formed. A storage electrode coupled to the storage node contact is formed.

Abstract: DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

Abstract: A first electrode film, a ferroelectric film, and a second electrode film are accumulated above a semiconductor in this order, a hard mask is accumulated above the second electrode, scrub cleaning is performed on the surface of the hard mask with an surfactant, the hard mask on which the scrub cleaning is performed has been patterned according to a planar shape of a ferroelectric capacitor, and etching is performed by using as a hard mask the hard mask that has been patterned.

Abstract: In a method of fabricating a metal-insulator-metal (MIM) capacitor and a metal-insulator-metal (MIM) capacitor fabricated according to the method, the method comprises: forming an insulating-layer pattern on a semiconductor substrate, the insulating-layer pattern having a plurality of openings that respectively define areas where capacitor cells are to be formed; forming a lower electrode conductive layer on the insulating-layer pattern and on the semiconductor substrate; forming a first sacrificial layer that fills the openings on the lower electrode conductive layer; forming a second sacrificial layer on of the first sacrificial layer; planarizing the second sacrificial layer; exposing an upper surface of the lower electrode conductive layer; removing the exposed lower electrode conductive layer to form a plurality of lower electrodes that are separated from each other, each corresponding to a capacitor cell; and forming dielectric layers and upper electrodes, that are separated from each other, each corres

Abstract: A capacitor and a method of fabricating the capacitor are provided herein. The capacitor can be formed by forming two or more dielectric layers and a lower electrode, wherein at least one of the two or more dielectric layers is formed before the lower electrode is formed.

Abstract: A method of forming a structure in a phase changeable memory cell can include forming a bottom electrode having an interlayer dielectric layer thereon, the bottom electrode having a recess therein that extends beyond a boundary between the bottom electrode and the interlayer dielectric. A phase changeable layer can be formed in the recess including a protruding potion of the phase changeable layer that protrudes into the bottom electrode beyond the boundary.

Abstract: A manufacturing method of a semiconductor device having a highly reliable capacitor, and the semiconductor device are provided.

Abstract: A method of manufacturing a semiconductor device having a first memory cell array region and a second memory cell array region, the method includes forming an active region on a surface layer of a semiconductor substrate, forming a first word line extending in a first direction on the gate insulating film in the first memory cell array region, and forming a second word line extending in a second direction crossing the first direction on the gate insulating film in the second memory cell array region, wherein the ion implantation into the active region is performed from a direction that is inclined from a direction vertical to the surface of the semiconductor substrate and is oblique with respect to both the first direction and the second direction.

Abstract: The invention includes: multiple bit lines b1 to b5 arranged in parallel to each other at a first line pitch; multiple word lines w1 to w4 arranged in parallel to each other at a second line pitch greater than the first line pitch and intersecting with bit lines b1 to b5; and multiple capacitors. Respective center positions 4 of the multiple capacitors lie above the bit lines and are displaced by given distance C from the intersection of the bit line and the word line in a direction of arranging the word lines.

Abstract: HfO2 films and ZrO2 films are currently being developed for use as capacitor dielectric films in 85 nm technology node DRAM. However, these films will be difficult to use in 65 nm technology node or later DRAM, since they have a relative dielectric constant of only 20-25. The dielectric constant of such films may be increased by stabilizing their cubic phase. However, this results in an increase in the leakage current along the crystal grain boundaries, which makes it difficult to use these films as capacitor dielectric films. To overcome this problem, the present invention dopes a base material of HfO2 or ZrO2 with an oxide of an element having a large ion radius, such as Y or La, to increase the oxygen coordination number of the base material and thereby increase its relative dielectric constant to 30 or higher even when the base material is in its amorphous state. Thus, the present invention provides dielectric films that can be used to form DRAM capacitors that meet the 65 nm technology node or later.

Abstract: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.

Abstract: According to an aspect of the present invention, there is provided a semiconductor memory device, including a TC unit series-type FeRAM in which a plurality of memory cells, each of the memory cells comprising a memory transistor and a ferroelectric capacitor connected each other in parallel, are serially connected, including, a first electrode over and electrically connected to one of a source and a drain in the memory transistor, a second electrode opposed to the first electrode over and electrically connected to the other of the source and the drain in the memory transistor, a third electrode on both sidewalls of the second electrode other than an under portion of the second electrode, and a ferroelectric film between the first electrode and the two electrodes, the second electrode and the third electrode, wherein the ferroelectric capacitor comprises the first and the third electrode, and the ferroelectric film.