Abstract: A signal separation module includes a single-ended bidirectional pin coupled to a processing device, a single-ended unidirectional output pin coupled to a differential signal transceiver, a single-ended unidirectional input pin coupled to the differential signal transceiver, and signal separation logic. The signal separation logic is to detect a current flow condition that indicates the bidirectional pin is asserted by the processing device; assert, as a result of the existence of the current flow condition, the unidirectional output pin and prevent the unidirectional input pin from affecting the bidirectional pin; detect an opposite current flow condition that indicates that the unidirectional input pin is asserted by the differential signal transceiver; and assert, as a result of the existence of the opposite current flow condition, the bidirectional pin and prevent the assertion of the bidirectional pin from affecting the unidirectional output pin.

Abstract: A power control subsystem for controlling the supply of power transmitted to at least one node over communication cabling, the power control subsystem comprising: a plurality of references; a plurality of comparators, each of the comparators being associated with a particular one of the plurality of references; and a current limiter in communication with the plurality of comparators and arranged to limit current of the power transmitted over communication cabling responsive to the plurality of comparators.

Abstract: Flow control mechanisms avoid or eliminate retries of transactions in a coherency interconnect. A class of transaction (CoT) framework is defined whereby individual transactions are associated with CoT labels consistent with chains of dependencies that exist between transactions initiated by any of the cooperating devices that participate in a given operation. In general, coherency protocols create dependencies that, when mapped to physical resources, can result in cycles in a graph of dependencies and deadlock. To support architectural mechanisms for deadlock avoidance, CoT labels are applied to individual transactions consistent with a precedence order of those transactions both (i) with respect to the operations of which such transactions are constituent parts and (ii) as amongst the set of such operations supported in the coherency interconnect.

Abstract: A logic chip has a plurality of individually-addressable resource blocks, each comprising logic circuitry. The logic chip also has a bus comprising a plurality of bus information lines. A first of the resource blocks has a coupling between a first strict sub-set of the bus information lines and the logic circuitry of the first resource block. A second of the resource blocks, which is adjacent to the first resource block, has a coupling between a second strict sub-set of the bus information lines and the logic circuitry of the second resource blocks. The first and second sub-sets have different bus lines.

Abstract: A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits (12P, 12C) that are otherwise configured to communicate over an address-based network (18). Sync signals (46, 56) are generated for each of producer and consumer circuits (12P, 12C) from the address information encoded into requests that communicate the data streams output by the producer circuit (12P) and expected by the consumer circuit (12C). The sync signals (46, 56) for the producer and consumer circuits (12C) are then used to selectively modify the data stream output by the producer circuit (12P) to a format expected by the consumer circuit (12C). Typically, such modification takes the form of inserting data into the data stream when the consumer circuit (12C) expects more data than output by the producer circuit (12P), and discarding data communicated by the producer circuit (12P) when the consumer expects less data than that output by the producer circuit (12P).

Abstract: Various embodiments are described herein for a mobile communication device that utilizes a smart battery. The mobile device includes a main processor for controlling the operation of the mobile communication device. The smart battery is coupled to the main processor and provides supply power. The smart battery includes a battery processor for controlling the operation of the smart battery and communicating with the main processor, and a battery module having one or more batteries for providing the supply power. A battery interface is provided for coupling between the main processor and the battery processor for providing communication therebetween. The battery interface comprises a data communication line and protection circuitry for protecting the main processor from electrostatic discharge. A communication protocol is also provided for communication between the main processor and the battery processor.

Abstract: The computer system of the present invention has a plurality of SAS target devices, an SAS initiator device, and a service delivery subsystem that is connected to each SAS target device by means of a physical link that is physical wiring and connected to the SAS initiator device by means of a wide link constituted by a plurality of physical links. The SAS initiator device controls how many physical links in the wide link are allocated to a particular SAS target device, whereby access from the SAS initiator device to the SAS target device is made via a physical link that is allocated to the SAS target device and is not made via a physical link that is not allocated to the SAS target device.

Abstract: The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.

Abstract: An apparatus and method are disclosed for state sharing. A change module detects a change of a configuration state for at least one of a base and a detachable device. A connection module detects a connection between the base and the detachable device. The detachable device provides a display and a network connection for the base if the base and detachable device are connected. A synchronize module synchronizes the configuration state of the detachable device with the configuration state of the base in response to detecting the connection and detecting the change of configuration state.

Abstract: A communication system comprises a first and a second master unit and at least one slave unit, wherein the second master unit is switched into a data transmission chain reaching from the first master unit to the slave unit in order to continue data transmission if a link fault occurs.

Abstract: Methods and systems, including computer program products, consistent with the invention may manage invoices for a customer. For example, methods consistent with the invention may obtain customer transaction data reflecting transactions made by the customer. The method may then generate, from the obtained customer transaction data, compressed transaction data and detailed transaction data, wherein the compressed transaction data without the detailed transaction data is used to generate an invoice to the customer. The method may then provide the compressed transaction data to a service processor for performing invoice management functions based on the compressed transaction data.

Abstract: The present invention provides an intelligent, modular multimedia computer management system for coupling a series of remote computers to one or more user workstations to allow each user workstation to selectively access and control one or more remote computers. The computer management system incorporates a centralized switching system that receives keyboard, cursor control device, audio, and auxiliary peripheral device signals from the user workstation and transmits and applies the signals to the remote computer in the same manner as if the keyboard, cursor control device, audio input source, or auxiliary peripheral device of the user workstation were directly coupled to the remote computer. Also, the user workstation receives audio signals and auxiliary peripheral device signals from the remote computer. In addition, the multimedia computer management system transmits video signals from the remote computer over an extended range for display on the video monitor of the user workstation.

Abstract: In one embodiment, a method includes storing, in a storage unit, a number of data transfer requests to issue for a data request signal. Data transfer requests are issued to a direct memory access (DMA) controller of a system for transfer of data to a buffer unit. The stored number of data transfer requests is determined. The issuance of data transfer requests are stopped when the stored number of data transfer requests is met.

Abstract: A method for swapping peer-to-peer remote copy (PPRC) secondary device definitions from a subchannel set other than zero to subchannel set zero by the utilization of control block-field manipulation includes identifying a PPRC primary and secondary device pair, wherein a PPRC primary device definition resides at subchannel set zero and the PPRC secondary device definition resides at a subchannel set other than subchannel set zero; within operating system definitions of the PPRC pair, exchanging physical information associated with the PPRC primary and secondary devices, including pathing, node descriptor, device number, and a field cross referencing device numbers of the PPRC pair; and within channel subsystem definitions of the PPRC primary and secondary devices, via a SwapSubchannel instruction, exchanging physical information, including path and control unit information while retaining a subchannel identifier, a subchannel set identifier, and a subchannel interruption parameter pointing to the operating sy

Abstract: An integrated circuit includes a millimeter wave transceiver section that is coupled to generate a first modulated RF signal from a first outbound symbol stream and to convert a first inbound RF signal into a first inbound symbol stream. A wireless transceiver section is coupled to generate a second modulated RF signal from a second outbound symbol stream and to convert a second inbound RF signal into a second inbound symbol stream. A processing module is coupled to convert first outbound data into the first outbound symbol stream, convert second outbound data into the second outbound symbol stream, convert the first inbound symbol stream into first inbound data, and to convert the second inbound symbol stream into second inbound data.

Abstract: A process control system is provided having a plurality of I/O devices in communication using a bus. A primary redundant I/O device and a secondary redundant I/O device are coupled to the bus, where the secondary redundant I/O device is programmed to detect a primary redundant I/O device fault. The secondary redundant I/O device, upon detecting the primary redundant I/O device fault, publishes a primary redundant I/O device fault message on the bus. The controller may deactivate the primary redundant I/O device and activate the secondary redundant I/O device responsive to the primary redundant I/O device fault message.

Abstract: Described embodiments provide a transceiver for transferring data between a media controller and a host device through a communication link. The transceiver includes a first interrupt generator configured to i) generate a first interrupt when a command is received from the host device and ii) provide the received command to a receive buffer. A command processing module i) retrieves the received command from the receive buffer, ii) processes the received command, and iii) provides data request data in response to the received command to a transmit buffer. A datagram generator is configured to provide datagram data to the transmit buffer and a second interrupt generator is configured to generate a second interrupt when data in the transmit buffer is ready for transmission. The transmit buffer interleaves i) the data request data in response to the received command and ii) the datagram data, when provided to the communication link.

Abstract: An information processing system includes a master module for outputting a transfer state signal in correspondence to a data read instruction when the data read instruction is successively output plural times, the transfer state signal indicating that at least one data read instruction succeeds some one of the data read instructions; and a memory controller for, when receiving the some one of the data read instructions and the corresponding transfer state signal from the master module, supplying data corresponding to the some one of the data read instructions to the master module, while reading data corresponding to the at least one data read instruction, which succeeds the some one of the data read instructions, from a memory and holding the read data in accordance with the received transfer state signal.

Abstract: An apparatus, system and method for providing health-care equipment in a plurality of customizable configurations. A configuration includes a selection and arrangement of health-care equipment modules that each provide specialized support for the provision of health care, including the measurement of physiological parameters. Various types of configurations include those adapted to be mounted upon a desk top or a wall surface, or adapted for wheel mounting or hand-carriable mobile configurations.

Abstract: A method and computer program product for sending a data request from a host bus adapter logic processor to a hard disk drive, setting a standard time out period for receiving a reply from the hard disk drive, sensing vibration in the hard disk drive, sending a vibration alert signal from the hard disk drive to the host bus adapter logic processor in response to the sensed vibration exceeding a predetermined amount of vibration, and, in response to receiving the vibration alert signal from the hard disk drive, the host bus adapter logic processor establishing an extended time out period for receiving the reply. The rotational vibration sensor used by the hard disk drive for repositioning the read/write head may also be used to sense the vibration and form the basis for the vibration alert signal, such as a vibration error code. By extending the time out period during high vibration events, the hard disk drive can ride out the event without being tagged as having failed.

Abstract: A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first terminal and a data terminal connected to the third terminal. In a case of performing communication by the first interface circuit, a fixed signal fixed at a predetermined level is input into the first terminal, a clock signal is input into the second terminal, and a data signal is input into the third terminal, and in a case of performing communication by the second interface circuit, the clock signal is input into the first terminal and the data signal is input into the third terminal.

Abstract: A disclosed semiconductor integrated circuit interfaces an external circuit and a host for controlling the external circuit and obtains data used to interface the external circuit and the host from a rewritable external memory. The disclosed semiconductor integrated circuit includes external terminals to which an external signal line group is connected, the external signal line group including signal lines connecting the external circuit and the external memory in parallel; an external terminal interface circuit configured to interface the semiconductor integrated circuit and the external circuit or the external memory connected via the external signal line group; and a control circuit configured to activate or deactivate the external circuit and the external memory. The control circuit is configured to activate either the external circuit or the external memory that is to be accessed via the external terminal interface circuit.

Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: Embodiments of the invention are generally directed to adaptive interconnection for multimedia devices. An embodiment of an apparatus includes an apparatus that includes one or more ports, the one or more ports including one or more adaptable ports, where each adaptable port includes a receptacle to accept a plug of a connector element, the receptacle including multiple electrical contacts. The apparatus further includes an adaptable port device to process data including multimedia data received at the one or more adaptable ports, where the adaptable port device is to detect a multimedia signal format for multimedia data received at each of the adaptable ports, and adapt each of the adaptable ports to be compatible with the detected multimedia signal format for the adaptable port.

Abstract: A semiconductor device capable of connecting plurality of external devices. When an interface with a first external device that can be connected to the semiconductor device is tested, a packet to be transferred from the first external device to another second external device is artificially generated. The generated packet is transferred to the second external device, and a response is monitored. Thus, the interface for connection to the first external device is tested while avoiding an actual packet transfer between the semiconductor device and the first external device.

Abstract: A computer switching device is disclosed which enables switching between a local computer and a secure computer connected through a network. The device sits like a keyboard-video-mouse (KVM) and optionally audio device between the local computer and the local input/output devices, but connects to the secure computer through a network. Access to the secure computer is pre-configured in the switching device through access and security settings for a specific user to the specific secure computer. The switching device specifically prevents access to the secure computer by the local computer, printer, or storage devices such as fixed or removable media drives. Tamper detection is included to disable secure access on any tampering with the switching device.

Abstract: A controller is provided that receives a single enclosure management (EM) serial bit stream from an expander or other device and divides the EM serial bit stream into multiple EM serial bit streams for delivery to multiple respective midplanes or backplanes. In this way, a separate EM serial bit stream is provided to each midplane or backplane without having to increase the number of ports that are available on the expander or other device that interfaces with the backplane or midplane.

Abstract: Described embodiments provide a host subsystem that generates a host context corresponding to a received host data transfer request. A programmable sequencer generates one or more sequencer contexts based on the host context. Each of the sequencer contexts corresponds to at least part of the host data transfer request. The sequencer contexts are provided to a buffer subsystem of the media controller. For host read requests, the buffer subsystem retrieves the data associated with the sequencer contexts of the read request from a corresponding buffer or a storage media and transmits the data associated with the sequencer contexts to the host device. For host write requests, the buffer subsystem receives the data associated with the host context from the host device and stores the data associated with the sequencer contexts of the write request to a corresponding buffer or the storage media.

Abstract: A clock divider circuitry and method for use in a dynamic random access memory device. The method may include receiving a clock input signal having a first frequency from a clock input receiver at clock divider circuitry, the clock divider circuitry including a flip-flop configured to generate an output signal, based at least in part, on an inverted output signal and the clock input signal. The output signal may have a second frequency that is a fraction of the first frequency. The method may further include receiving the clock input signal and the output signal at a multiplexer and generating a multiplexed output. The method may additionally include receiving the multiplexed output at a first bus configured to receive the multiplexed output and to reduce an operational frequency of the first bus in response to an increase in an operational frequency of a second bus associated with the memory device.

Abstract: User is allowed to designate a desired mode defining the respective numbers of channels and mixing buses, and processing for mixing input signals of the number of channels corresponding to the designated mode is performed repetitively to generate signals for the individual buses. The time of arrival of the last step in the mixing processing for the number of channels, corresponding to the designated mode, is detected to output an accumulation result obtained at the last step, and new accumulation is started with a digital audio signal inputted at a step following the last step. Digital audio signals processed by a first signal processing circuit are stored into a memory and transmitted to a second signal processing circuit via a cascade-connection. The second signal processing circuit adds the audio signal, processed for each of the steps, to audio signals input via the cascade-connection and writes added signal into the memory.

Abstract: According to one embodiment, a data transfer device is provided. The data transfer device is configured to transfer data between a plurality of data transceivers and at least one memory having a first memory area. When one of the data transceivers has acquired an exclusive access right to the first memory area of the memory, the data transfer device stores address information corresponding to the first memory area.

Abstract: A hybrid in-vehicle infotainment network includes a core high-speed network having a number of high-speed nodes, each of which may be connected to at least one other high-speed node via a high-speed backbone link. At least some high-speed nodes may be hybrid nodes. Hybrid nodes may communicate with one or more low-speed devices via one or more low-speed links. Each hybrid node, along with any connected low-speed devices, forms a respective local low-speed network. In some embodiments, hybrid nodes may conform with a 1394 specification for high-speed backbone link communications and may conform with a universal serial bus (USB) specification for low-speed link communications. Communications via the high-speed backbone links and the low-speed links may use a common application layer having defined therein a same maximum packet size and a same set of commands and vendor-specific identifiers.

Abstract: An operating method for an integrated interface of a PDA and a wireless communication system includes the following steps. Firstly, when the wireless communication system starts to operate from a standby mode, a state signal is transmitted from the wireless communication system to the PDA. Then, if the PDA receives the state signal when the PDA is in a sleep state, the PDA is wakened and an input source of an audio element inside the PDA is switched to the wireless communication system. An electromagnetic wave signal is received by a wireless communication element and converted into audio data. Afterwards, the audio data is transmitted from the wireless communication system to the PDA and outputted by the audio element.

Abstract: A system and method are described for converting a circuit description into transaction-based description at a higher level of abstraction. Thus, a designer can readily view a series of transactions that occurred in the simulation of a circuit. In one aspect, the simulated signals are analyzed and converted into messages of a protocol used by the design. A combination of the messages represents a transaction. Thus, the simulated signals are then converted into a series of protocol transactions. In another aspect, a message recognition module performs the analysis of the simulated signals and converts the simulated signals into messages (e.g., request for bus, bus acknowledge, etc.). A transaction recognition module analyzes the messages and converts the messages into transactions (e.g., Read, Write, etc.). Using both the system and method the circuit description is converted into a higher level of abstraction that allows more comprehensive system-level analysis.

Abstract: There is provided an apparatus including a plurality of modules. Each module includes a storage unit configured to store a waiting ID and a specific ID of the module, a communication unit configured to transmit and receive packets to and from a bus, and a processing unit configured to process data of a packet which includes a valid flag indicating that the packet is valid, wherein the communication unit takes in data held by a packet which has an ID that coincides with the waiting ID, and stores the processed data in a packet which includes the valid flag indicating invalid and an ID coincident with the specific ID, and transmits the packet.

Abstract: The present invention pertains to a configurable PCI-Express switch. The configurable PCI-Express switch includes a differential I/O interface capable of being configured in a first configuration or a second configuration. In the first configuration, the differential I/O interface implements a PCI-Express interface with a coupled device. In the second configuration, the differential I/O interface implements a differential interface other than PCI-Express with the coupled device. The configurable PCI-Express switch also includes a switching unit capable of configuring the differential I/O interface in the first configuration or the second configuration.

Abstract: In one embodiment, a receiver on a credit-based flow-controlled interface is configured to free one or more data credits early when a data payload is received that incurs fewer unused data credits within a buffer memory that is allocated at a coarser granularity than the data credits. In another embodiment, header credits and data credits are dynamically adjusted based on actual packet data payload sizes.

Abstract: In an MFP, a system controller is connected to an engine via a universal transmission line and a dedicated transmission line. When MFP is powered, the system controller sends a mode signal to the engine via the dedicated signal line. If the mode signal indicates that the power mode is to be set to a normal mode, the engine activates predetermined components. The system controller and the engine then establish communication via the universal bus. After establishing the communication, if the mode signal indicates that the power mode is to be set to a mode other than the normal mode, the system controller sends a setting command to the engine via the bus to set the power mode to any of a plurality of power-saving modes.

Abstract: The information processing system includes a plurality of information processing apparatuses connected via a network. Each apparatus includes one or more modules interconnected via a system bus. At least one of the modules is a network module having a network communication function. The information processing apparatus that inputs an external timing signal functions as a timing master, and the other information processing apparatuses function as a timing slave. The module in the timing master generates time synchronization information in the form of a packet and in the form of a command according to the timing signal and transmits the command to another module and transmits the packet to the timing slave via the network. The network module in the timing slave receives the packet from the timing master, converts the packet to the command to transmit to another module connected to the system bus and included in the timing slave.

Abstract: A multi-motherboard server system, having a management board and a plurality of motherboards, is disclosed. The multi-motherboard server system is applicable to a sever system. The management board has a BMC, and the motherboards are respectively connected to the management board. The BMC can transmit data to a far-end control system through sideband communication.

Abstract: Various methods, computer-readable mediums, articles of manufacture and systems are disclosed. In one aspect, a method is provided that includes generating a packet with a first semiconductor chip. The packet is destined to transit a first substrate and be received by a node of a second semiconductor chip. The packet includes a packet header and packet body. The packet header includes an identification of a first exit point from the first substrate and an identification of the node. The packet is sent to the first substrate and eventually to the node of the second semiconductor chip.

Abstract: Provided is a microcomputer simulator capable of quickly dealing with change of a target microcomputer to thereby enable a speedy development of software. The microcomputer simulator is a microcomputer simulator for simulating a microcomputer including therein a CPU and a peripheral circuit of the CPU, and includes a mother board including a CPU for executing application software to be processed by the CPU provided in the microcomputer, and an IO board for executing, at an FPGA thereof, processing of the peripheral circuit provided in the microcomputer and IO processing executed by the CPU provided in the microcomputer. The FPGA includes a common memory portion so that the microcomputer simulator updates data stored in the common memory portion through a communication bus provided between the mother board 10 and the IO board, and causes data to be exchanged between the CPU provided in the mother board and the FPGA.

Abstract: Location data is exchanged between a portable media device and an accessory. If the portable media player is equipped with location determining capability, the portable media device can communicate its location data to the accessory, and the accessory can use this location data to perform various tasks. If the accessory is equipped with location assistance capability, the accessory can communicate location data to the portable media device, and the portable media device can use this location data to perform various tasks.

Abstract: Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

Abstract: A wireless USB hub for connecting a plurality of remote peripheral devices to a computer for communication therewith without the need to physically connect the peripheral devices to the hub via a cable connection. The wireless USB hub includes a receiver for receiving wireless data transmissions from one or more remote peripheral devices. The wireless USB hub further includes a hub controller for passing appropriate peripheral device information to a USB upstream port and then to a computer.

Abstract: At least one downstream interface may be configured to be simultaneously connected to both a USB 3.0 compliant device and a USB 2.0 compliant device. The interface may be used for communicating with a USB 3.0 compliant device via a downstream port and simultaneously communicating with a USB 2.0 compliant device via the downstream port.

Abstract: A semiconductor memory apparatus includes an input data bus inversion unit configured to determine whether or not to invert a plurality of input data depending upon levels of the plurality of input data, and generate a plurality of conversion data; data input lines configured to transmit the plurality of conversion data; a data recovery unit configured to receive the plurality of conversion data and generate a plurality of storage data; and a memory bank configured to store the plurality of storage data.

Abstract: An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.

Abstract: One embodiment of the present invention relates to a method for communicating NOR-type flash specific memory commands from a DRAM memory controller to a NOR-type flash memory array without disrupting DRAM operation. In this embodiment flash specific commands are channeled from the DRAM controller to the flash device by using the DRAM protocol as a transport layer. Data to be written to the NOR-type flash memory array are loaded into a data register and a sequence of programming commands are loaded into a mode register as a series of mode register write operations. Once the entire sequence of programming commands is loaded the NOR-type flash memory array the data in the data register is loaded into the NOR-type flash memory array. Other methods and circuits are also disclosed.

Abstract: In a memory system using a removable recording medium and data stored in the recording medium, identifying information for identifying each recording medium from others is held in the recording medium, and when data stored in the recording medium is used, the identifying information of the recording medium is required. As a result, when a flash memory card, etc. is used, a copyright is reliably protected.