Abstract: An error checking and correcting (ECC) circuit is connected with nonvolatile memories via a plurality of channels. The ECC circuit calculates a first syndrome according to first read data and stores the first syndrome in a first syndrome register block, and calculates a second syndrome according to second read data and stores the second syndrome in a second syndrome register block.

Abstract: A memory system and method using at least one memory device die stacked with and coupled to a logic die by interconnects, such as through silicon vias. One such logic die includes an ECC system generating error checking and correcting (“ECC) bits corresponding to write data. The write data are transmitted to the memory device dice in a packet containing a serial burst of a plurality of parallel data bits. The ECC bits are transmitted to the memory device dice using through silicon vias that are different from the vias through which data are coupled. Such a logic die could also include a data bus inversion (“DBI”) system encoding the write data using a DBI algorithm and transmitting to the memory device dice DBI bits indicating whether the write data have been inverted. The DBI bits are transmitted using through silicon vias that are shared with the ECC bits when they are unused for transferring the ECC bits.

Abstract: A code generating device includes a code word generating section which generates a code word with a predetermined code word length by applying a second matrix Gq of a second error detection method with regard to an information word A? which has been input, and a code word conversion section which converts the code word generated by the code word generating section based on an added fixed value (Qa+Pa) which is formed from respective code words Qa and Pa which are obtained by the second matrix Gq and a first matrix Gp of a first error detection method being respectively applied to an information word A which is formed from a specific data string.

Abstract: An access control apparatus for controlling an access to a storage device, the access control apparatus includes a measuring unit configured to measure the time to erase data stored in the storage device, and a determination unit configured to determine a data size of an error correcting code added to data stored in the storage device in accordance with the time measured by the measuring unit. The access control apparatus includes a generation unit configured to generate the error correcting code having the data size determined by the determination unit, and an access controller configured to write the data and the error correcting code generated by the generation unit into the storage device.

Abstract: A method for forward error correction decoding is disclosed. The method generally includes steps (A) to (D). Step (A) may calculate a plurality of metrics of a codeword using a forward error correction process on a trellis having a plurality of stages. Step (B) may update the metrics over each of the stages. Step (C) may permute the metrics in each of the stages. Step (D) may generate a signal carrying a plurality of decoded bits of the codeword.

Abstract: A storage subsystem monitors one or more conditions related to the probability of a data error occurring. Based on the monitored condition or conditions, the storage subsystem adjusts an error correction setting, and thus the quantity of ECC data used to protect data received from a host system. To enable blocks of data to be properly checked when read from memory, the storage subsystem stores ECC metadata indicating the particular error correction setting used to store particular blocks of data. The storage subsystem may be in the form of a solid-state non-volatile memory card or drive that attaches to the host system.

Abstract: An apparatus and method for fault tolerant Firmware-Over-The-Air (FOTA) update are provided. The method includes computing a checksum for each sector of a partially updated firmware, for each sector of the partially updated firmware, determining a last instruction in an update package that was applied to that sector, based on checksums included in the update package and the computed checksums of the sectors of the partially updated firmware, determining a last instruction of the update package that was applied to the partially updated firmware prior to the interruption based on the last instruction applied to each sector, and resuming the update procedure starting from an instruction immediately following the last applied instruction.

Abstract: An apparatus generally including a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) receive a configuration signal that identifies a current one of a plurality of communications standards and (ii) generate a plurality of matrix elements based on the configuration signal. The second circuit may include a plurality of matrixes. The second circuit may be configured to (i) fill the matrixes with the matrix elements and (ii) generate an encoded signal by forward error correction encoding an input signal using the matrixes. The encoded signal generally complies with the current communications standard.

Abstract: Briefly, techniques to provide varying levels of enhanced forward error correction without modifying a line rate of a frame.

Abstract: A method for decoding tail-biting convolutional codes. The method includes initializing a correction depth, selecting a first starting state from a set of encoding states, and initializing a metric value for the selected starting state as zero and the other states as infinity. The input bit stream is read and a Search Depth Viterbi algorithm (SDVA) is performed to determine path metrics and identify a minimum-metric path. The ending state for the minimum-metric path is determined and the output for this ending state is identified as “previous output.” A second starting state is set to the ending state of the minimum-metric path, and symbols equal to the correction depth from the previous output are read. The SDVA is performed on the second set of read symbols to generate a corrected output. A decoded output is generated by replacing symbols at the beginning of the previous output with the corrected output.

Abstract: To derive a Hamming code to manage data errors a set of at least four parity bit positions is selected for parity bits which will protect a set of data bits (where each data bit has a data bit position in the data bit set). A syndrome is determined for each data bit position. This involves selecting a unique sub-set of at least three parity bit positions. The unique sub-set shares at least one parity bit position with at least one other unique sub-set of at least three parity bit positions. A parity bit value may then be calculated for each parity bit position based on the determined syndromes. The header of a packet may be provided with a word which defines the length of the packet and an error management code generated utilizing this word so that errors in the word may be detected and, possibly, corrected.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.

Abstract: According to one embodiment, a receiving apparatus includes a data packet receiver, a quality reinforcement packet receiver, an information setting module, a packet processor, a recovery processor. The data packet receiver is configured to receive a data packet comprising a data portion. The quality reinforcement packet receiver is configured to receive a quality reinforcement packet comprising a quality reinforcement portion. The information setting module is configured to set the data portion corresponding to a part of information included in the data packet as a recovery process target. The packet processor is configured to determine whether there is a lost data packet based on the received data packet and the quality reinforcement packet.

Abstract: Digital communication coding methods are shown, which generate certain types of low-density parity-check (LDPC) codes built from protographs. A first method creates protographs having the linear minimum distance property and comprising at least one variable node with degree less than 3. A second method creates families of protographs of different rates, all structurally identical for all rates except for a rate-dependent designation of certain variable nodes as transmitted or non-transmitted. A third method creates families of protographs of different rates, all structurally identical for all rates except for a rate-dependent designation of the status of certain variable nodes as non-transmitted or set to zero. LDPC codes built from the protographs created by these methods can simultaneously have low error floors and low iterative decoding thresholds.

Abstract: A method for correcting at least one error in a data transmission over a packet-based communication network includes the steps of: generating a sequence of data packets for transmission over the packet-based communication network, the sequence of data packets being arranged into a plurality of packet frames, each of at least a subset of the packet frames including at least a primary data packet and a number of redundant data packets which is a function of a prescribed redundancy pattern, the subset of packet frames having a non-uniform distribution of redundant data packets therein; transmitting the sequence of data packets over the communication network; and recovering at least one missing data packet in the sequence of data packets using at least one corresponding redundant data packet in at least one subsequently received packet frame when the missing data packet is identified in a receiver of the sequence of data packets.

Abstract: A computer-readable medium storing a program causing a computer to execute a process includes, acquiring a plurality of data units that belong to a first block in a certain hierarchy among hierarchical blocks defined by a plurality of hierarchies; generating error correction information corresponding to the first block that equals to an exclusive-OR of the plurality of data units; generating, in each individual hierarchy of one or more individual hierarchies that are continuous from and are lower than the certain hierarchy, error correction information corresponding to each individual block that equals to the exclusive-OR of all data units that belong to the individual block among the plurality of data units, where the individual block is one or more individual blocks other than one specific block in two or more blocks in the individual hierarchy that are included in the same block in a hierarchy.

Abstract: A method and apparatus are provided for modulating a binary source sequence including of a plurality of source words to generate modulated symbols. The method implements error-correction encoding of the plurality of source words, implementing one or more encoding modules, each implementing a separate error-correction code to generate a plurality of code words, the source words being encoded in series. The code words are interlaced to generate an interlaced sequence. The interlaced sequence is differentially modulated to generate modulated symbols. Each code word is broken down into at least one group with a number of bits equal to the base-2 logarithm of a number of states of a modulation implemented by the step of differentially modulating. The interlacing step distributes the groups such that two adjacent groups in the interlaced sequence belong to separate code words.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit, a noise predictive filter circuit, a data detector circuit, a data reconstruction circuit, and an adaptation circuit. The equalizer circuit is operable to receive a data input and to provide an equalized output based at least in part on an equalizer coefficient. The noise predictive filter circuit is operable to receive the equalized output and to provide a noise whitened output based at least in part on a noise predictive filter coefficient. The data detector circuit is operable to apply a data detection algorithm to the noise whitened output to yield a detected output. The data reconstruction circuit is operable to receive the detected output and to provide a reconstructed output corresponding to the equalized output based at least in part on a target polynomial.

Abstract: Systems and methods of providing error tolerant robust simplex wireless data for systems employing time correlated data transfer are provided. In one embodiment, a system comprises: sensors that produce samples of time correlated data; and a node coupled to the sensors by a wireless link. The link comprises a primary stream for simplex transmission of data packets, and a secondary stream for simplex transmission of delayed data packets, the delayed data packets a delayed retransmission of the time correlated data. When the node receives a first data packet from a first sensor via the primary stream, the data receiving node check validity. When the first data packet is corrupted, the node validity checks a second data packet received via the secondary stream. When both packets contain corrupted data, the node builds a reconstructed plurality of sequential time correlated data samples based on non-corrupted data samples from within the data packets.

Abstract: A parameterized interleaver design process is provided, which optimizes the design for interleavers of any size, and can be completely specified using only a few design parameters. According to the parameterized interleaver design process an interleaver ?(i) of a length N is generated. A number of subpermutation masks are defined, and a first intermediate interleaver permutation is partitioned into a number of subgroups, wherein the number of subgroups corresponds with the number of subpermutation masks. Each of the subgroups of the first intermediate interleaver permutation is partitioned into a number of further subgroups, and each of the subpermutation masks is applied to each of the further subgroups of a corresponding subgroup of the first intermediate interleaver permutation, resulting in a corresponding portion of a second intermediate interleaver permutation. The resulting interleaver ?(i) is generated based at least in part on the first and second intermediate interleaver permutations.

Abstract: Data digits and correction digits are received in each of a number of integrated circuit (IC) devices. Apparatus, systems, and methods are disclosed that operate to check the data digits for error in each IC device according to an algorithm associated with the IC device, the algorithm being different for each IC device. Each IC device will act in response to the data digits if no error is detected in the data digits. Additional apparatus, systems, and methods are disclosed.

Abstract: Disclosed herein is a coding apparatus, including: a calculation section adapted to calculate, based on information of a transmission object, a linear code to be used for error detection of the information; a production section adapted to produce coded data including a plurality of sets of the information and the linear code calculated by the calculation section; and a transmission section adapted to transmit the coded data to a reception apparatus.

Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Abstract: A receiver apparatus can identify a plurality of patterns corresponding to scrambled synchronization bytes of a transport stream in a number of successive signal frames containing FEC code blocks, determine a pattern distribution into which most of the patterns identified in the successive signal frames map, and generate a synchronization signal locked to a distribution of the FEC code blocks associated with the pattern distribution. With this synchronization signal, FEC code blocks can be timely handled in a reliable manner through a FEC decoder, making the receiver apparatus more efficient and robust. In other embodiments, methods of handling FEC code blocks in a receiver apparatus are also described.

Abstract: A receiver apparatus comprises a LDPC decoder that can apply an accelerated belief propagation method for iteratively decoding each code block. When the number of iterations reaches a certain threshold value, the accelerated belief propagation method can adjust the initial condition used in each iteration. The initial condition is adjusted so as to enhance the likelihood of convergence in the iterative method. As a result, performance of the decoder and receiver apparatus can be improved.

Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.

Abstract: If the number of bits at which 64-bit width data has changed at the same time has exceeded a threshold, the data is outputted, with the polarity of each bit inverted. Otherwise, the data is outputted. A 7-bit width error correcting code is given to the outputted data and the inversion instruction signal indicating whether the number of the changed bits has exceeded the threshold. Error code correction is performed for the data and the inversion instruction signal with the use of the transmitted error correcting code. If the inversion instruction signal for which the error code correction has been performed indicates that the number of the changed bits has exceeded the threshold, the data for which the error code correction has been performed is outputted, with the polarity of each bit inverted. Otherwise, the data for which the error code correction has been performed is outputted.

Abstract: A method of storing a plurality of blocks of data in a plurality of physically distinct non-volatile memory devices, each being independently written to or read from, wherein each block of data is the minimum amount of data that can be written to or read from the non-volatile memory device. The method includes generating one or more blocks of error checking data based upon the plurality of blocks of data; and storing the plurality of blocks of said data and the one or more blocks of error checking data in the plurality of distinct physical non-volatile memory devices, with a block of data in a different physical memory device. Further, the method links the address of the plurality of blocks of data and the one or more blocks of error checking data in a cyclical link so that any entry to one of the blocks will result in a link all of the other blocks.

Abstract: In a first aspect, an aggregated packet (A-MPDU) includes packets (MPDUs) and EC-Blocks (Error Correction Blocks) containing error correction coding information. A transmitter uses a Fountain coding scheme (for example, Raptor or RaptorQ) to generate the error correction coding information from the MPDUs. If a receiver detects an error in a received MPDU, then the receiver uses the error correction coding information from the EC-Blocks to correct the error. In a second novel aspect, a determination is made as to whether a change in error rate is more likely due to collisions or to a low SNR. If the determination is that the change is due to collisions then the MCS index is adjusted to restore a target error rate, whereas if the determination is that the change is due to a low SNR then the number of EC-Blocks per A-MPDU is adjusted to restore the target error rate.

Abstract: Low density parity check code (LDPC) base parity check matrices and the method for use thereof in communication systems. The method of expanding the base check parity matrix is described. Examples of expanded LDPC codes with different code lengths and expansion factors are also shown.

Abstract: An improved decoder and decoding method for low density parity check (LDPC) codes is provided. Decoding proceeds by repetitive message passing from a set of variable nodes to a set of check nodes, and from the check nodes back to the variable nodes. The variable node output messages include a “best guess” as to the relevant bit value, along with a weight giving the confidence in the, guess. The check node output messages have magnitudes selected from a predetermined set including neutral, weak, medium and strong magnitudes. The check node output messages tend to reinforce the status quo of the input variable nodes if the check node parity check is satisfied, and tend to flip bits in the input variable nodes if the check node parity check is not satisfied. The variable node message weights are used to determine the check node message magnitudes.

Abstract: A data structure for a flash memory and data reading/writing method thereof are disclosed. A 512 bytes data and a redundant code derived from the data encoded with a 6-bit error correcting code scheme are stored in a first sector and a second sector with sequential address in a block of the flash memory respectively. A logic block address information of this block is divided into two parts that are stored in the first sector and the second sector respectively.

Abstract: A transmission device in a communication system where a systematic code obtained by systematic encoding of information bits into which dummy bits are inserted and by deletion of the dummy bits from the results of the systematic encoding is transmitted. The transmission device inserts dummy bits into information bits based on an interleaving pattern of an interleaving portion in a turbo encoder; performs systematic encoding of the information bits into which the dummy bits are inserted, and then deletes the dummy bits from the results of the systematic encoding to generate a systematic code; and transmits the systematic code. By considering the interleaving pattern, original bit positions, which, after interleaving, exists within the ranges of stipulated numbers of bits at the beginning and at the end, are determined in advance, and the dummy bit insertion portion executes control so as not to insert dummy bits into the original bit positions.

Abstract: A digital broadcasting system and a method for controlling the same are disclosed. A method for controlling a digital broadcast receiving system includes the steps of receiving a broadcast signal having mobile service data and main service data multiplexed therein, extracting transmission parameter channel (TPC) signaling information and fast information channel (FIC) signaling information from a data group within the received mobile service data, by using the extracted fast information channel (FIC) signaling information, acquiring a program table describing virtual channel information and service of an ensemble, the ensemble being a virtual channel group of the received mobile service data, by using the acquired program table, detecting a descriptor defining basic information required for accessing the received service, and, by using the detected descriptor, controlling the receiving system to enable access to the corresponding service.

Abstract: Disclosed herein is a decoding device including: an extracting section, a storing section, an allocating section, and a decoding section. The extracting section acquires data containing plural code words and information other than the plural code words in one frame, and extracts the plural code words from the data every one code word. The storing section at least stores the one code word extracted by the extracting section. The allocating section sets time obtained by dividing time for the one frame by the number of code words contained in the one frame as time allocated to decoding of one code word. The decoding section decodes the code word within the time allocated by the allocating section.

Abstract: The invention relates to a method for encoding digital data, in particular of data processed in a microprocessor unit. In the method according to the invention for a respective data word (A, B, C) of a series of data words to be encoded subsequently a parity code (P(A), P(B), P(C)) is computed on the basis of the data of the respective data word (A, B, C). Further the respective data word (A, B, C) is altered with the aid of the data word (A, B, C) preceding it in the series, wherein the altered data word (Aa, Ba, Ca) and the parity code (P(A), P(B), P(C)) represent the encoded data word (Ac, Bc, Cc) and the encoded data word (Ac, Bc, Cc) can be decoded with the aid of the data word (A, B, C) preceding it in the series.

Abstract: A method in a memory device includes receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. An ECC operation is initiated to process the data block using the main ECC data. In response to the ECC operation indicating uncorrectable errors in the data, a first sub-block ECC operation is initiated to process the first sub-block of data using the first ECC data.

Abstract: Systems and methods for encoding and decoding for communications or storage systems utilizing coded modulation are provided. A first portion of data is encoded with a first at least one encoding scheme. A second portion of the data id encoded with a second encoding scheme. A coset is selected from a plurality of cosets based at least in part on the encoded first portion of the data, where the plurality of cosets corresponds to a partition of a signal constellation. A signal vector is selected within the selected coset based at least in part on the encoded second portion of the data.

Abstract: An error-correcting coding method generates code words of m bits from useful data blocks of n bits. The method adds k check bits to a block of n useful data bits in order to generate a code word of m=n+k bits, said check bits being defined according to the combination rules defined by a parity matrix H consisting of binary elements and having k rows and m columns such that H·V=0, V being a column matrix whose m elements are the m bits of the code word to be generated. The k check bits are separated into two groups, on the one hand a group of k1 bits called total parity bits PT and on the other hand a group of k2 bits called conventional check bits VC, the values of k, k1 and k2 satisfying the conditions k=k1+k2 and k>k1>2, the matrix H whose columns can be swapped being broken down into six submatrices A, B, C, D, E and F. Another method detects multiple errors in code words generated by the coding method.

Abstract: The present invention discloses a method for fast cyclic redundancy check (CRC) encoding, and includes: mapping a CRC encoding generator polynomial to generate an (r+1)-order transfer matrix J; deleting a first row and a first column of said (r+1)-order transfer matrix J to obtain an r-order transfer matrix; forming a r×1 column matrix by first columns of 2nd to r+1th rows of said (r+1)-order transfer matrix; obtaining a zero input transfer matrix and a zero state transfer matrix of CRC encoding by the r-order transfer matrix and the r×1 column matrix; adding dummy bits before an input bit stream; and obtaining a CRC encoding check sequence according to the zero input transfer matrix, the zero state transfer matrix and the input bit stream after adding the dummy bits. The present invention further discloses an apparatus for fast cyclic redundancy check encoding.

Abstract: In one embodiment, a wireless relay apparatus for replaying a signal processed by first encoding from a transmitting apparatus to a receiving apparatus is disclosed. The apparatus includes a demodulation unit, a decoding unit, a detection unit, an extraction unit, and an encoding unit. The demodulation unit demodulates a received signal. The decoding unit performs error correction decoding corresponding to the first encoding on the demodulated signal. The detection unit detects an error in a decoded signal. The extraction unit extracts a portion pertaining to information data from the demodulated signal by hard decision, if the detection unit detects an error. The encoding unit performs error correcting coding on the extracted portion pertaining to the information data with an error. The information data encoded by the encoding unit is transmitted.

Abstract: To improve performance of a decoder even in a system with the coder configuration determined by inserting a doping bit sequence known between a transmission apparatus and a reception apparatus in an information bit sequence to transmit, the transmission apparatus is a transmission apparatus that transmits radio signals to the reception apparatus, and is provided with a doping section 23 that inserts a doping bit sequence which is known between the transmission apparatus and the reception apparatus in an information bit sequence to transmit to the reception apparatus, coding sections 11a, 11b that performerror-correcting coding on a bit sequence with the doping bit sequence inserted therein, a puncturing section that performs puncturing on a bit sequence subjected to the error-correcting coding, and a wireless transmission section 24 that transmits a bit sequence subjected to the puncturing.

Abstract: Methods and systems for processing an optical signal in a communication system are disclosed. The disclosed methods yield benefits for estimation and tracking of carrier phase of received signals at a digital coherent receiver without the use of differential coding. Specifically, phase ambiguity is removed by calculating the slope of the CPE at a location where the CPE begins to lose track of the received carrier phase signal. As such, a CPE offset adjustment may be applied in accordance with the calculated slope to reduce the number of ones and zeros corrected by a FEC decoder. Thus, the FEC aided CPE scheme may be a feed forward scheme that requires no training.

Abstract: A method for detecting and correcting errors in a memory having a read/write paradigm is presented. In these implementations, various approaches to detect errors on a per word or per group of words basis and correct errors on a per group of words or per page basis, respectively, in relation to a memory and its associated differing read/write operations, are provided. For instance, in one implementation, errors are detected on a per word basis and corrected on a per page basis for a NOR Flash Memory having differing read/write operations of reading on a per word basis and writing on a per page basis. Advantageously, benefits of the various implementations include reduced encoder/decoder complexities, reduced parity overhead requirements, and reduced performance degradation.

Abstract: A method begins by a processing module dispersed storage error encoding fundamental component data of data in accordance with dispersed storage error coding parameters to produce a plurality of sets of encoded data slices, wherein the data includes the fundamental component data and enhancement component data. The method continues with the processing module transmitting a set of the plurality of sets of encoded data slices and transmitting a corresponding portion of the enhancement component data substantially concurrently with the transmitting of the set of the plurality of sets of encoded data slices.

Abstract: A method begins by a first device determining an error coding distributed routing protocol and transmitting a set of encoded data slices, identity of a second device, and the error coding distributed routing protocol to a network, wherein the set of encoded data slices represents data that has been dispersed storage error encoded. The method continues with the network routing a plurality of sub-sets of the set of encoded data slices via an initial plurality of routing paths towards the second, comparing anticipated routing performance with a desired routing performance, and altering the routing path to obtain a favorable comparison. The method continues with the second device receiving at least some of the set of encoded data slices from the network and decoding at least a threshold number of encoded data slices to reproduce the data when at least the threshold number of encoded data slices have been received.

Abstract: Provided is an encoding apparatus wherein a transmission data sequence is divided into L short sequences, each of which is then encoded by use of an m-stage pseudo-cyclic low-density parity check encoding system. Each of the L encoded sequences is further divided into shorter sequences, the number of which is identical to the number m of the stages of the pseudo-cyclic codes and each of which has a length m. The shorter sequences are rearranged in order by a replacing module, thereafter encoded, by use of the m-stage pseudo-cyclic low-density parity check encoding system, and outputted. Accordingly, a decoding apparatus with a simple structure where node processing circuits (e.g., minimum-value calculating circuits), the number of which is p that is a submultiple of the number m of the foregoing stages, are provided, can be employed to efficiently decode the codes having a large frame length and a large encoding gain.

Abstract: Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: Various embodiments of the present invention provide methods for generating a code format. Such methods include: receiving an indication of a low weight codeword having a trapping set; selecting an initial value for a base matrix; testing the low weight codeword after modification by the initial value to determine an updated weight of the low weight codeword; and testing the low weight codeword after modification by the initial value to determine whether the trapping set remains.

Abstract: Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matrix; testing the first column for trapping sets, wherein at least one trapping set is identified; selecting a value to mitigate the identified trapping set; and augmenting the first matrix with a second matrix to yield a composite matrix. The second matrix has the selected value in the first column, and wherein the identified trapping set is mitigated.

Abstract: Techniques for encoding and decoding data are described. In an aspect, multiple code rates for a forward error correction (FEC) code may be supported, and a suitable code rate may be selected based on packet size. A transmitter may obtain at least one threshold to use for code rate selection, determine a packet size to use for data transmission, and select a code rate from among the multiple code rates based on the packet size and the at least one threshold. In another aspect, multiple FEC codes of different types (e.g., Turbo, LDPC, and convolutional codes) may be supported, and a suitable FEC code may be selected based on packet size. The transmitter may obtain at least one threshold to use for FEC code selection and may select an FEC code from among the multiple FEC codes based on the packet size and the at least one threshold.