Abstract: A sacrificial memory bank is added to a block of regular banks in a memory to reduce dynamic power consumption of the memory. The sacrificial bank is accessed by a set of bit lines that is substantially shorter than corresponding bit lines extending through all of the regular memory banks. Memory read and write operations, which are addressed to one of the regular banks, are deliberately redirected to the sacrificial bank having the short bit lines. Tracking circuitry identifies the regular bank that was addressed for each location in the sacrificial bank. Data is moved from the sacrificial bank to a regular bank only when a new write operation does not match the bank of the previous write operation. Dynamic power is reduced because locality of reference causes access to the sacrificial bank without having to access a regular bank for most memory read and write operations.

Abstract: Methods of reading data from memory cells. Such methods include subjecting an analog storage device to a voltage level indicative of a threshold voltage of a memory cell to store a charge to the analog storage device, and generating an analog voltage from the stored charge.

Abstract: A resistance variable layer has a characteristic in which the resistance variable layer changes to a second resistance state (RL) in such a manner that its resistance value stops decreasing when an interelectrode voltage reaches a first voltage (V1) which is a negative voltage, the resistance variable layer changes to a first resistance state (RH) in such a manner that its resistance value starts increasing when the interelectrode voltage reaches a second voltage (V2) which is a positive voltage which is equal in absolute value to the first voltage, the resistance variable layer changes to the first resistance state in such a manner that the resistance variable layer flows an interelectrode current such that the interelectrode voltage is maintained at a third voltage (V3) higher than the second voltage, when the interelectrode voltage reaches the third voltage, and the resistance variable layer changes to the first resistance state in such a manner that its resistance value stops increasing when the interelec

Abstract: A memory device is provided. The memory device includes a first semiconductor chip including a memory element and a peripheral circuit configured to write or read data in or from the memory element; and a second semiconductor chip configured to perform an input/output function of data or signals exchanged between an external device and the first semiconductor chip.

Abstract: A replica circuit includes: a first conductivity type first transistor; a first current path including a first conductivity type second transistor and a second conductivity type third transistor; a second current path including a first conductivity type fourth transistor configured so that current equivalent to a current flowing through the first transistor flows through the fourth transistor, and a second conductivity type fifth transistor configured so that current equivalent to a current flowing through the third transistor flows through the fifth transistor, the fourth transistor and the fifth transistor being connected in series; a second conductivity type sixth transistor configured so a current equivalent to a current flowing through the third transistor flows through the sixth transistor; a first control configured to supply a reference voltage to the drain of the first transistor; and a second control configured to supply the reference voltage to the drain of the fourth transistor.

Abstract: Techniques for providing a direct injection semiconductor memory device having ganged carrier injection lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region coupled to a bit line and a second region coupled to a source line. The apparatus may also comprise a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The apparatus may further comprise a third region coupled to a constant voltage source via a carrier injection line configured to inject charges into the body region through the second region.

Abstract: A nonvolatile semiconductor memory device in which a memory cell life can be prolonged while making it possible to perform writing in units of bits. When command information represents writing, a comparing unit 37 compares written data in a target memory cell with write target data to give a comparison result to a write/read control unit 40, when the comparison result represents matching, the write/read control unit 40 does not instruct a decoder unit (51A, 51B, and 53) to perform writing in the target memory cell, and when the comparison result represents mismatching, the write/read control unit 40 instructs the decoder unit to write the write target data in the target memory cell.

Abstract: An interleaver or deinterleaver comprises a memory having M logical memory units arranged in groups of N memory units such that accesses to memory units within a group are faster after a first access to a memory in that group using first access. An address generator is arranged to write consecutive data items a number of memory units apart that is less than the size of groups N of memory units so that two or more data items are written within groups. The arrangement provides fast interleaving without increasing memory size.

Abstract: A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.

Abstract: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

Abstract: Various aspects of the invention provide memory devices, methods of storing and reading data, and silver/molecular-layer/metal (SMM) junctions. One aspect of the invention provides a memory device including a plurality of SMM junctions and an electrical structure configured to permit application of electricity across one or more of the plurality of SMM junctions. Another aspect of the invention provides a method of storing data on a memory device including a plurality of SMM junctions. The method includes applying electrical energy across a subset of the SMM junctions to switch the junction to a more conductive state. Another aspect of the invention provides an SMM junction including a silver layer, a copper layer, and a molecular layer positioned between the silver layer and the copper layer.

Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.

Abstract: A memory device is provided comprising a transistor having a floating body positioned between source and drain regions, the floating body being sandwiched between first and second insulated gates each comprising a gate electrode. A control circuit is arranged to program the state of said floating body to have an accumulation or depletion of majority carriers by applying one of first and second voltage levels between the first gate and at least one of the source and drain regions, and to retain the programmed state of said floating body by applying a third voltage level to the second gate. The voltages are switched over a time duration shorter than 100 ns.

Abstract: In embodiments of the present invention improved capabilities are described for a passive radio frequency identification (RFID) tag, where the passive RFID tag contains an RF network node and communication facility. The RF network node includes an RF and analog block for receiving and transmitting an RFID reader signal, a data processing and controller block for digital information processing, a memory store, and a power management block for managing power requirements of the RF network node. The communication facility communicates at least in part with an external display facility. The distribution of power to the RF network node functional blocks is controlled using the power management block to select between an extended operational time and an increase in available functionality.

Abstract: A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is stored in a non-volatile manner as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.

Abstract: A high voltage generation circuit includes a plurality of pumps configured to generate a final pump voltage, a plurality of switches configured to couple the pumps to various nodes, a voltage division circuit configured to divide the final pump voltage from the pumps interconnected by the switches, and outputting a divided voltage, a section signal generation circuit configured to generate a plurality of section signals by comparing the divided voltage with each of different reference voltages, and a section signal combination circuit configured to generate enable signals for controlling the switches by combining the section signals.

Abstract: A semiconductor apparatus includes a normal data line, an auxiliary data line and a data line selection unit. The normal data line is connected with a data selection unit. The auxiliary data line is connected with the data selection unit. The data line selection unit outputs data to one of the normal data line and the auxiliary data line in response to a command signal.

Abstract: Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links.

Abstract: Techniques and corresponding circuitry are presented for the detection of broken wordlines in a memory array. An “inter-word-line” comparison where the program loop counts of different word-lines are compared in order to determine whether a word-line may be defective. The number of programming pulses needed for the cells along a word-line WLn is compared to the number needed for a preceding word-line, such as WLn or WL(n?1), to see whether it exceeds this earlier value by a threshold value. If the word-line requires an excessive number of pulses, relative the earlier word-line, to complete programming, it is treated as defective.

Abstract: Methods and apparatus are provided that include reading a plurality of sets of program pulse tuning instructions from a memory page, the memory page including a plurality of memory cells; and creating a plurality of program pulses in accordance with the plurality of sets of program pulses to program the plurality of memory cells. The plurality of sets of program pulse tuning instructions may be different from one another in at least one respect.

Abstract: A method of performing a holding operation to a semiconductor memory array having rows and columns of memory cells by applying an electrical signal to collector regions of multiplicity of said memory cells in parallel, wherein said collector region of said memory cells in a row of said memory array is connected to a common control line, wherein each of said memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein at least one of said memory cells further comprises another memory cell on top thereof; and wherein said holding operation maintains charges stored in said floating body region of multiplicity of memory cells connected to said common control line.

Abstract: Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.

Abstract: A flash memory controller includes a controllable delay circuit configured to receive a read strobe signal from a flash memory device and to delay the read strobe signal, a data latch, coupled to the controllable delay circuit, configured to receive the delayed read strobe signal, and to capture data from the flash memory device using the delayed read strobe signal, and a calibration circuit coupled to the controllable delay circuit, configured to instruct the controllable delay circuit to delay the read strobe signal at one of a plurality of delay settings, to receive the captured data from the data latch, to determine an accuracy of the captured data, and to determine an adjustment factor for the controllable delay circuit based on the accuracy of the data captured at the data latch.

Abstract: According to one embodiment, a transfer circuit includes a first inverter, a second inverter, a first line, a second line, a first holder, and a second holder. The first inverter inverts data at a first node and transfers the inverted data to a second node. The second inverter inverts the data at the second node and transfers the inverted data to the first node. The first line connected to the first node. The second line connected to the second node. The first holder may output data to the first node. The second holder may output data to the second node. When the first holder outputs the data to the first line, the first and second inverters are turned off. When the second holder outputs the data to the first line through the second node, the first inverter is turned off.

Abstract: An object is to provide a semiconductor device having a novel structure. A first wiring; a second wiring; a third wiring, a fourth wiring; a first transistor including a first gate electrode, a first source electrode, and a first drain electrode; a second transistor including a second gate electrode, a second source electrode, and a second drain electrode are included. The first transistor is provided over a substrate including a semiconductor material and a second transistor includes an oxide semiconductor layer.

Abstract: A circuit includes a memory (130) coupled to an analog line coverage circuit (104). The analog line coverage circuit includes a plurality of buffers (151-154) in which each buffer is coupled to one memory location of the memory, a plurality of bin cells (161-164) in which each bin cell is coupled to a buffer, a multiplexer (170), each input terminal of which is coupled to a bin cell, and an analog-to-digital converter (180) coupled to the multiplexer and to an output terminal of the analog line coverage circuit. The analog line coverage circuit stores an analog voltage that is representative of a number of occasions that a memory location is accessed, and outputs a signal indicative thereof. A processor (102) is coupled to the memory and to the analog line coverage circuit, and the processor enables the analog line coverage circuit when the processor is in a debug mode.

Abstract: A first copier acquires data and determines a plurality of recipients to deliver split data. A data splitter 308 splits data into a plurality of data blocks and a dummy data generator 315 generates dummy data. A data delivery unit 310 delivers the data blocks and dummy data to the plurality of recipients. At the same time, the data delivery unit 310 outputs restoration information including information about the recipients of the data. Based on the restoration information, a second copier collects the plurality of data blocks and the dummy data from the plurality of recipients and discards the dummy data, acquiring the plurality of data blocks. The second copier reconstructs a set of data from the plurality of data blocks.

Abstract: Integrated circuits may include memory elements that are provided with voltage overstress protection. One suitable arrangement of a memory cell may include a latch with two cross-coupled inverters. Each of the two cross-coupled inverters may be coupled between first and second power supply lines and may include a transistor with a gate that is connected to a separate power supply line. Another suitable memory cell arrangement may include three cross-coupled circuits. Two of the three circuits may be powered by a first positive power supply line, while the remaining circuit may be powered by a second positive power supply line. These memory cells may be used to provide an elevated positive static control signal and a lowered ground static control signal to a corresponding pass gate. These memory cells may include access transistors and read buffer circuits that are used during read/write operations.

Abstract: A method includes receiving a memory code identifying a number of logic zeroes and logic ones to be stored in a semiconductor memory, determining a number of bit cells of a first type that are to be coupled to a first bit line of the semiconductor memory from the memory code, and selecting a first keeper circuit from a plurality of keeper circuits based on the number of bit cells of the first type that are to be coupled to the first bit line. An electronic representation of a layout of the semiconductor memory is stored in a non-volatile machine readable storage medium.

Abstract: The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein a memory unit includes termination circuitry, and a memory unit does not include termination circuitry.

Abstract: At the time of reading, an unselected word line voltage is fixed to a first predetermined voltage (0 V or 3 V), and when selecting a word line, a selected word line voltage is set to a second predetermined voltage (?3.5 V or 0 V). This configuration eliminates an application of a pulsed voltage to the word line at the time of reading, making it possible to reduce an influence of read disturbance. In addition, even when a voltage in a range from a power source voltage to a ground voltage or a voltage over the power source voltage is required at the time of reading, it becomes a voltage about 1.5 times an absolute value of the power source voltage. Therefore, a voltage step-up circuit having a large number of stages is not required, and as a result, it is possible to achieve a reduced operation time with a low power consumption.

Abstract: Provided is a delay adjustment device for adjusting delay of a strobe signal, which specifies when to read a data signal on a data line, with respect to the data signal in order to perform data transfer with an external memory. A testing unit 150 included in a delay adjustment unit is provided with a memory bandwidth monitoring unit 212 that monitors memory bandwidth in use on the data line used for data transfer with a memory circuit. The testing unit 150 performs delay adjustment when the memory bandwidth in use is lower than a predetermined threshold. Delay adjustment is performed by delaying the strobe signal from the data signal by a variety of predetermined delays and determining whether data transfer is successful at each delay, calculating an optimal delay, and thereafter delaying the strobe signal by the calculated delay.

Abstract: An anti-fuse circuit including a programmable module, a read module, and a control module is provided. The programmable module has a plurality of data cells. The read module is coupled to the programmable module. During a normal operation, the read module distinguishes which one or more of the data cells are stressed. The control module is coupled to the programmable module. During a stress operation, the control module controls each stressed data cell to be coupled to a high voltage, a low voltage, and a control voltage. The first end of each stressed data cells is coupled to the low voltage, the second end of each stressed data cells is coupled to the high voltage, and the control end of each stressed data cells is coupled to the control voltage during the stress operation.

Abstract: An improved memory array architecture and cell design is disclosed. In one embodiment, a memory array for an integrated circuit may comprise a plurality of memory cells. Each of the memory cells may comprise a material capable of holding a logic state and two access transistors coupled to the material. The two access transistors may be configured to access the logic state of the material, and may be independently selectable by two word lines of a plurality of word lines parallel to a first dimension.

Abstract: A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter.

Abstract: A non-volatile semiconductor memory device includes a memory cell array and a control circuit. A control circuit performs an erase operation providing a memory cell with a first threshold voltage level for erasing data of a memory cell, and then perform a plurality of first write operations providing a memory cell with a second threshold voltage level, the second threshold voltage level being higher than the first threshold voltage level and being positive level. When the control circuit receives a first execution instruction from outside during the first write operations, the first execution instruction being for performing first function operation except for the erase operation and the first write operations, the circuit performs the first function operation during the first write operations.

Abstract: A method of operating a semiconductor device according to an embodiment of the present invention includes programming selected memory cells by applying a first program voltage, which gradually rises, to a selected word line and applying a first pass voltage, which is constant, to remaining unselected word lines; and programming the selected memory cells while applying a second program voltage, which is constant, to the selected word line and applying a second pass voltage, which gradually rises, to first unselected word lines adjacent to the selected word line, when a difference between the first program voltage and the first pass voltage reaches a critical voltage difference.

Abstract: A semiconductor device is operated by, inter alia: programming selected memory cells by applying a first program voltage which is increased by a first step voltage to a selected word line and by applying a first pass voltage having a constant level to unselected word lines, and when a voltage difference between the first program voltage and the first pass voltage reaches a predetermined voltage difference, programming the selected memory cells by applying a second program voltage which is increased by a second step voltage lower than the first step voltage to the selected word line and by applying a second pass voltage which is increased in proportion to the second program voltage to first unselected word lines adjacent to the selected word line among the unselected word lines.

Abstract: A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.

Abstract: The data read circuit includes a variable current generation circuit and a data sensing circuit. The variable current generation circuit is configured to generate a variable current that varies in response to an external temperature. The data sensing circuit is configured to sense and amplify data on a bit line connected to a non-volatile memory cell according to the variable current and to configured to output the sensed and amplified data. The data sensing circuit controls a margin for sensing the data according to the variable current.

Abstract: Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.

Abstract: Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented.

Abstract: Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array.

Abstract: An electrically identifiable medical electrode lead. The lead includes a flexible lead body having a distal end and a connector end. The lead also includes a plurality of electrodes disposed near the distal end of the flexible lead body. The lead further includes a connector disposed at the connector end of the flexible lead body, the connector including a plurality of contacts. The lead additionally includes a plurality of conductors supported by and passing through the flexible lead body, the plurality of conductors including electrical conductors that provide paths for electrical current from the connector to the plurality of electrodes. Finally, the lead includes a memory circuit supported by the flexible lead body and being in electrical communication with a contact of the plurality of contacts in the connector.

Abstract: An apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core. The periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core.

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode comprising hafnium oxide and having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a material including metal titanium and having a second thickness that is less than 25 percent of the first thickness.

Abstract: Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.

Abstract: A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

Abstract: A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

Abstract: A static random access memory (SRAM) cell includes a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio. A static random access memory (SRAM) array includes a plurality of SRAM cells, an SRAM cell including a first read port, the first read port having a first beta ratio; and a write port, the write port having a second beta ratio that is substantially lower than the first beta ratio.