Abstract: In sophisticated semiconductor devices, an efficient adjustment of an intrinsic stress level of dielectric materials, such as contact etch stop layers, may be accomplished by selectively exposing the dielectric material to radiation, such as ultraviolet radiation. Consequently, different stress levels may be efficiently obtained without requiring sophisticated stress relaxation processes based on ion implantation, which typically leads to significant device failures.

Abstract: A method of manufacturing a silicon wafer, an oxygen concentration in a surface layer to be maintained more than a predetermined value while promoting a defect-free layer. Strength of the surface layer can be made higher than that of an ordinary annealed sample as a COP free zone is secured. A method of manufacturing a silicon wafer doped with nitrogen and oxygen, includes growing a single crystal silicon doped with the nitrogen by Czochralski method, slicing the grown single crystal silicon to obtain a single crystal silicon wafer; heat treating the sliced single crystal silicon wafer in an ambient gas including a hydrogen gas and/or an inert gas; polishing the heat treated single crystal silicon wafer, after the heat treatment, such that an obtained surface layer from which COP defects have been removed by the heat treatment is polished away until an outermost surface has a predetermined oxygen concentration.

Abstract: An ion implantation is performed to implant ions into a silicon substrate, and a microwave irradiation is performed to irradiate the silicon substrate with microwaves after the ion implantation. After the microwave irradiation, the silicon substrate is transferred to a heat-treatment apparatus, where the silicon substrate is treated with heat by being irradiated with light having a pulse width ranging from 0.1 milliseconds to 100 milliseconds, both inclusive.

Abstract: A method of manufacturing a semiconductor device including: mounting a substrate on a substrate mounting member that is disposed in a reaction container; heating the substrate at a predetermined processing temperature and supplying a first gas and a second gas to the substrate to process the substrate; stopping supply of the first gas and the second gas, and supplying an inert gas into the reaction container; and unloading the substrate to outside the reaction container.

Abstract: Methods of transferring a layer of semiconductor material from a first donor structure to a second structure include forming a generally planar weakened zone within the first donor structure defined by implanted ions therein. At least one of a concentration of the implanted ions and an elemental composition of the implanted ions may be formed to vary laterally across the generally planar weakened zone. The first donor structure may be bonded to a second structure, and the first donor structure may be fractured along the generally planar weakened zone, leaving the layer of semiconductor material bonded to the second structure. Semiconductor devices may be fabricated by forming active device structures on the transferred layer of semiconductor material. Semiconductor structures are fabricated using the described methods.

Abstract: First flash irradiation from flash lamps is performed on an upper surface of a semiconductor wafer supported on a temperature equalizing ring of a holder to cause the semiconductor wafer to jump up from the temperature equalizing ring into midair. While the semiconductor wafer is in midair above the temperature equalizing ring, second flash irradiation from the flash lamps is performed on the upper surface of the semiconductor wafer to increase the temperature of the upper surface of the semiconductor wafer to a treatment temperature. Cracking in the semiconductor wafer is prevented because the second flash irradiation is performed while the semiconductor wafer is in midair and subject to no restraints.

Abstract: When the single crystal semiconductor layer is melted, the outward diffusion of oxygen is promoted. Specifically, an SOI substrate is formed in such a manner that an SOI structure having a bonding layer including oxygen provided over a base substrate and a single crystal semiconductor layer provided over the bonding layer including oxygen is formed, and part of the single crystal semiconductor layer is melted by irradiation with a laser beam in a state that the base substrate is heated at a temperature of higher than or equal to 500° C. and lower than a melting point of the base substrate.

Abstract: A method of annealing a semiconductor and a semiconductor. The method of annealing including heating the semiconductor to a first temperature for a first period of time sufficient to remove physically-adsorbed water from the semiconductor and heating the semiconductor to a second temperature, the second temperature being greater than the first temperature, for a period of time sufficient to remove chemically-adsorbed water from the semiconductor. A semiconductor device including a plurality of metal conductors, and a dielectric including regions separating the plurality of metal conductors, the regions including an upper interface and a lower bulk region, the upper interface having a density greater than a density of the lower bulk region.

Abstract: An annealing method to reduce defects of epitaxial films and epitaxial films formed therewith. The annealing method includes features as follows: apply a pressure ranged from 10 MPa to 6,000 MPa to an epitaxial film grown on a substrate through a vapor phase deposition process and heat the epitaxial film at a temperature lower than the melting temperature of the epitaxial film. Through applying pressure to the epitaxial film, the lattice strain of the epitaxial film is alleviated, and therefore the defect density of the epitaxial film also decreases.

Abstract: Defects in a semiconductor substrate due to ion implantation are minimized by forming an implant region in the semiconductor substrate and subjecting the semiconductor substrate to a first anneal to recrystallize the semiconductor substrate. The semiconductor substrate is subjected to a second anneal to suppress diffusion of implanted ions in the semiconductor substrate. The first anneal being at a lower temperature and longer duration than the second anneal.

Abstract: Embodiments of the invention provide an improved apparatus and methods for nitridation of stacks of materials. In one embodiment, a remote plasma system includes a remote plasma chamber defining a first region for generating a plasma comprising ions and radicals, a process chamber defining a second region for processing a semiconductor device, the process chamber comprising an inlet port formed in a sidewall of the process chamber, the inlet port being in fluid communication with the second region, and a delivery member disposed between the remote plasma chamber and the process chamber and having a passageway in fluid communication with the first region and the inlet port, wherein the delivery member is configured such that a longitudinal axis of the passageway intersects at an angle of about 20 degrees to about 80 degrees with respect to a longitudinal axis of the inlet port.

Abstract: Disclosed herein are a method for fabricating an organic thin film transistor, including treating the surfaces of a gate insulating layer and source/drain electrodes with a self-assembled monolayer (SAM)-forming compound through a one-pot reaction, and an organic thin film transistor fabricated by the method. According to example embodiments, the surface-treatment of the gate insulating layer and the source/drain electrodes may be performed in a single vessel through a single process.

Abstract: A method for curing defects associated with the implantation of atomic species into a semiconductor layer transferred onto a receiver substrate, wherein the semiconductor layer is thermally insulated from the receiver substrate by a low thermal conductivity layer having thermal conductivity that is lower than that of the transferred semiconductor layer. The method includes applying a selective electromagnetic irradiation to the semiconductor layer to heat that layer to a temperature lower than its temperature of fusion to cure defects without causing an increase in the temperature of the receiver substrate beyond 500° C.

Abstract: The present invention generally relates to methods for thermally processing substrates. In one embodiment, a substrate having an amorphous thin film thereon is subjected to a first pulse of electromagnetic energy having a first fluence insufficient to complete thermal processing. After a predetermined amount of time, the substrate is then subjected to a second pulse of electromagnetic energy having a second fluence greater than the first fluence. The second fluence is generally sufficient to complete the thermal processing. Exposing the substrate to the lower fluence first pulse before the second pulse reduces damage to a thin film disposed on the substrate. In another embodiment, a substrate is exposed to a plurality of electromagnetic energy pulses. The plurality of electromagnetic energy pulses are spaced at increasing intervals to reduce the rate of recrystallization of a film on the substrate, thus increasing the size of the crystals formed during the recrystallization.

Abstract: The invention provides a wafer-bonded semiconductor device wherein warpage generated when wafers are bonded is reduced at a low cost ad through a simple process. In a method for manufacturing a wafer-bonded semiconductor device by bonding a first wafer substrate and a second wafer substrate together, the method of the invention includes a first step of forming in advance bonding members having a bonding function when heated on the wafer-bonded surface sides of the first wafer substrate and the second wafer substrate, respectively; a second step of supplying flux paste containing two or more kinds of powdery materials having reactivity to the surfaces of the bonding members formed in the first step; and a third step of causing excitation to have the flux paste supplied in the second step start reacting.

Abstract: It is an object of the present invention is to provide a method of manufacturing an SOI substrate provided with a single-crystal semiconductor layer which can be practically used even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like, is used, and further, to manufacture a semiconductor device with high reliability by using such an SOI substrate. A semiconductor layer which is separated from a semiconductor substrate and bonded to a supporting substrate having an insulating surface is irradiated with electromagnetic waves, and the surface of the semiconductor layer is subjected to polishing treatment. At least part of a region of the semiconductor layer is melted by irradiation with electromagnetic waves, and a crystal defect in the semiconductor layer can be reduced. Further, the surface of the semiconductor layer can be polished and planarized by polishing treatment.

Abstract: An embodiment of the invention provides a laser annealing method, including the steps of radiating a laser beam to an amorphous film on a substrate while scanning the laser beam for the amorphous film, crystallizing the amorphous film, detecting a light quantity of laser beam reflected from the substrate and a scanning speed of the laser beam while the radiation and the scanning of the laser beam are carried out for the amorphous film, and controlling a radiation level and the scanning speed of the laser beam based on results of comparison of the light quantity of laser beam reflected from the substrate, and the scanning speed of the laser beam with respective preset references.

Abstract: A substrate processing apparatus capable of increasing the life span of a lamp for heating a substrate is provided. The substrate processing apparatus includes: a light receiving chamber for processing a substrate; a substrate support unit inside the light receiving chamber; a lamp including an electrical wire, and a seal accommodating the electrical wire to hermetically seal the lamp with a gas therein, the lamp irradiating the substrate with a light; a lamp receiving unit outside the light receiving chamber to accommodate the lamp therein, the lamp receiving unit including a lamp connector connected to the lamp to supply an electric current through the electrical wire, a heat absorption member including a material having a thermal conductivity higher than that of the seal, and a base member fixing the heat absorption member; and an external electrical wire connected to the lamp connector to supply current to the lamp connector.

Abstract: Some embodiments include methods in which microwave radiation is used to activate dopant and/or increase crystallinity of semiconductor material during formation of a semiconductor construction. In some embodiments, the microwave radiation has a frequency of about 5.8 gigahertz, and a temperature of the semiconductor construction does not exceed about 500° C. during the exposure to the microwave radiation.

Abstract: The present invention related to a method for manufacturing a semiconductor, comprising steps of: providing a growing substrate; forming on the growing substrate to have plural grooves; forming a semiconductor element layer on the growing substrate; and changing the temperature of the growing substrate and the semiconductor element layer so as to separate the semiconductor element layer from the growing substrate.

Abstract: In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.

Abstract: Provided is a substrate placement stage or substrate processing apparatus which can suppress thermal deformation of the substrate placement stage when the substrate placement stage on which a substrate is placed is heated in a process chamber. The substrate placement stage includes: a heating element; a first member surrounding the heating element; and a second member covering a surface of the first member and including a placing surface for placing a substrate thereon, wherein the first member is made of a first material containing ceramics and aluminum, and the second member is made of a second material containing ceramics and aluminum, a content of the ceramics in the second material being lower than that of the first material.

Abstract: In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur (?f). At least some shots in the plurality of shots overlap other shots. In some embodiments, ?f is reduced by controlling the amount of shot overlap in the plurality of shots, either during initial shot determination, or in a post-processing step. The reduced sensitivity to ?f expands the process window for the charged particle beam lithography process.

Abstract: A substrate holder has two holder constituting bodies, each having a plurality of columns arranged on an imaginary circle, and substrate holding sections that hold circumferential portions of respective substrates. The holder constituting bodies hold the substrates so that either their front surfaces or their back surfaces face upward with a substrate having an upward facing front and a substrate having an upward facing rear being alternately arranged in a vertical direction. At least one of the holder constituting bodies moves in the vertical direction to change the positions of the holder constituting bodies relative to each other. A distance between a first pair of vertically adjacent substrates with their respective front surfaces facing each other is set to ensure treatment uniformity, and to be larger than a distance between a second pair of vertically adjacent substrates with their respective back surfaces facing each other.

Abstract: The invention provides an IGZO-based oxide material and a method of producing the same, the IGZO-based oxide material being represented by a composition formula of In2-xGaxZnO4-?, where 0.75<x<1.10 and 0<??1.29161×exp(?x/0.11802)+0.00153, and being formed from a single phase of IGZO having a crystal structure of YbFe2O4.

Abstract: A method for manufacturing a semiconductor device includes irradiating light to an effective region of a semiconductor substrate. A wavelength of the light is a wavelength adapted so that light absorptance of the semiconductor substrate increases if an intensity of the light increases. The light is irradiated so that a focus point of the light is made within the semiconductor substrate in the irradiating.

Abstract: A substrate processing method and apparatus which can remove an anti-drying liquid, which has entered a three-dimensional pattern with recessed portions formed in a substrate, in a relatively short time. The substrate processing method includes the steps of: carrying a substrate, having a three-dimensional pattern formed in a surface, into a processing container, said pattern being covered with an anti-drying liquid that has entered the recessed portions of the pattern; heating the substrate and supplying a pressurizing gas or a fluid in a high-pressure state into the processing container, thereby forming a high-pressure atmosphere in the processing container before the anti-drying liquid vaporizes to such an extent as to cause pattern collapse and bringing the anti-drying liquid into a high-pressure state while keeping the liquid in the recessed portions of the pattern; and thereafter discharging a fluid in a high-pressure state or a gaseous state from the processing container.

Abstract: A method for producing a hybrid substrate includes preparing a first substrate including a mixed layer and an underlying electrically insulating continuous layer, the mixed layer made up of first single-crystal areas and second adjacent amorphous areas, the second areas making up at least part of the free surface of the first substrate. A second substrate is bonded to the first substrate, the second substrate including on the surface thereof, a reference layer with a predetermined crystallographic orientation. The first substrate is bonded to the second substrate by hydrophobic molecular bonding of at least the amorphous areas. A recrystallization of at least part of the amorphous areas to solid phase is carried out according to the crystallographic orientation of the reference layer, and the two substrates are separated at the bonding interface.

Abstract: Methods and apparatus for rapid thermal processing of a planar substrate including axially aligning the substrate with a substrate support or with an empirically determined position are described. The methods and apparatus include a sensor system that determines the relative orientations of the substrate and the substrate support.

Abstract: Embodiments of the invention contemplate a method, apparatus and system that are used to support and position a substrate on a surface that is at a different temperature than the initial, or incoming, substrate temperature. Embodiments of the invention may also include a method of controlling the transfer of heat between a substrate and substrate support positioned in a processing chamber. The apparatus and methods described herein generally may also provide an inexpensive and simple way of accurately positioning a substrate on a substrate support that is positioned in a semiconductor processing chamber. Substrate processing chambers that can benefit from the various embodiments described herein include, but are not limited to RTP, CVD, PVD, ALD, plasma etching, and/or laser annealing chambers.

Abstract: Structures and methods for forming the same. A semiconductor chip includes a substrate and a transistor. The chip includes N interconnect layers on the substrate, N being a positive integer. The chip includes a cooling pipes system inside the N interconnect layers. The cooling pipes system does not include any solid or liquid material. Given any first point and any second point in the cooling pipes system, there exists a continuous path which connects the first and second points and which is totally within the cooling pipes system. A first portion of the cooling pipes system overlaps the transistor. A second portion of the cooling pipes system is higher than the substrate and lower than a top interconnect layer. The second portion is in direct physical contact with a surrounding ambient.

Abstract: A semiconductor substrate processing system includes a processing chamber and a substrate support defined to support a substrate in the processing chamber. The system also includes a plasma chamber defined separate from the processing chamber. The plasma chamber is defined to generate a plasma. The system also includes a plurality of fluid transmission pathways fluidly connecting the plasma chamber to the processing chamber. The plurality of fluid transmission pathways are defined to supply reactive constituents of the plasma from the plasma chamber to the processing chamber. The system further includes a plurality of power delivery components defined to deliver power to the plurality of fluid transmission pathways, so as to generate supplemental plasma within the plurality of fluid transmission pathways. The plurality of fluid transmission pathways are defined to supply reactive constituents of the supplemental plasma to the processing chamber.

Abstract: A semiconductor substrate processing system includes a processing chamber and a substrate support defined to support a substrate in the processing chamber. The system also includes a plasma chamber defined separate from the processing chamber. The plasma chamber is defined to generate a plasma. The system also includes a plurality of fluid transmission pathways fluidly connecting the plasma chamber to the processing chamber. The plurality of fluid transmission pathways are defined to supply reactive constituents of the plasma from the plasma chamber to the processing chamber. The system further includes an electron injection device for injecting electrons into the processing chamber to control an electron energy distribution within the processing chamber so as to in turn control an ion-to-radical density ratio within the processing chamber. In one embodiment, an electron beam source is defined to transmit an electron beam through the processing chamber above and across the substrate support.

Abstract: A method for amorphizing a layer on a substrate is described. In one embodiment, the method includes treating the substrate with a first gas cluster ion beam (GCIB) using a first beam energy selected to yield an amorphous sub-layer within the substrate of a desired thickness, which produces a first interfacial roughness of an amorphous-crystal interface between the amorphous sub-layer and a crystalline sub-layer of the substrate. The method further includes treating the substrate with a second GCIB using a second beam energy, less than the first beam energy, to reduce the first interfacial roughness of the amorphous-crystal interface to a second interfacial roughness.

Abstract: The embodiments of methods and structures disclosed herein provide mechanisms of performing doping an inter-level dielectric film, ILD0, surrounding the gate structures with a dopant to reduce its etch rates during the processes of removing dummy gate electrode layer and/or gate dielectric layer for replacement gate technologies. The ILD0 film may be doped with a plasma doping process (PLAD) or an ion beam process. Post doping anneal is optional.

Abstract: A semiconductor processing apparatus includes: a stage on which a substrate having a semiconductor film to be processed is to be mounted; a supply section that supplies a plurality of energy beams onto the semiconductor film mounted on the stage in such a way that irradiation points of the energy beams are aligned at given intervals; and a control section that moves the plurality of energy beams and the substrate relative to each other in a direction not in parallel to alignment of the irradiation points of the plurality of energy beams supplied by the supply section, and scans the semiconductor film with the irradiation points of the plurality of energy beams in parallel to thereby control a heat treatment on the semiconductor film.

Abstract: Systems and methods are disclosed herein for forming defects on graphitic materials. The methods for forming defects include applying a radiation reactive material on a graphitic material, irradiating the applied radiation reactive material to produce a reactive species, and permitting the reactive species to react with the graphitic material to form defects. Additionally, disclosed are methods for removing defects on graphitic materials.

Abstract: The present invention related to a method for manufacturing a semiconductor, comprising steps of: providing a growing substrate; forming a semiconductor substrate on the growing substrate; forming a first structure with plural grooves and between the growing substrate and the semiconductor substrate; and changing the temperature of the growing substrate and the semiconductor substrate.

Abstract: A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method includes providing a silicon oxide layer with a thickness of less than or equal to 25 nanometers on one of a donor substrate or a receiver substrate or on both substrates, heat treating the substrate(s) that contains the silicon oxide layer at 900° C. to 1,200° C. under a neutral or reducing atmosphere that contains at least one of argon or hydrogen to form layer trapping through-holes inside the silicon oxide, bonding the substrates together at a bonding interface with the silicon oxide layer(s) positioned between them, reinforcing the bonding by annealing the substrates at 25° C. to 500° C. such that the trapping holes retaining gas species at the bonding interface, and transferring an active layer as a portion of the donor substrate onto the receiver substrate to obtain the heterostructure.

Abstract: An annealing method irradiates a target object, having a film formed on its surface, with a laser beam to perform an annealing process to the target object. The surface of the target object is irradiated with the laser beam obliquely at an incident angle that is determined to achieve an improved laser absorptance of the film.

Abstract: A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ?5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization.

Abstract: The present invention relates to a process for smoothing the surface of a semiconductor wafer by fusion. The process includes defining a reference length which dimensions wafer surface roughness that is to be reduced or removed, and scanning the surface with a fusion beam while adjusting parameters of the fusion beam so as to fuse, during the scanning of the surface, a local surface zone of the wafer whose length is greater than or equal to the reference length, with the scanning continued to smooth the entire surface of the wafer by eliminating surface roughnesses of period lower than the reference length. The present invention also relates to a semiconductor wafer having a surface layer made of a semiconducting material that is smoothed by the process and that does not exhibit any roughness of period lower than the reference length.

Abstract: Various embodiments may be used for laser-based modification of target material of a workpiece while advantageously achieving improvements in processing throughput and/or quality. Embodiments of a method of processing may include focusing and directing laser pulses to a region of the workpiece at a pulse repetition rate sufficiently high so that material is efficiently removed from the region and a quantity of unwanted material within the region, proximate to the region, or both is reduced relative to a quantity obtainable at a lower repetition rate. Embodiments of an ultrashort pulse laser system may include a fiber amplifier or fiber laser. Various embodiments are suitable for at least one of dicing, cutting, scribing, and forming features on or within a semiconductor substrate. Workpiece materials may include metals, inorganic or organic dielectrics, or any material to be micromachined with femtosecond, picosecond, and/or nanosecond pulses.

Abstract: A unique family of nanoparticles characterized by their nanometric size and cage-like shapes (hollow structures), capable of holding in their hollow cavity a variety of materials is disclosed herein.

Abstract: A system and method for reducing warpage of a semiconductor wafer. The system includes a device for securing the semiconductor wafer in a heating area. The device includes a holding mechanism for securing an edge of the semiconductor wafer. The device further includes a pressure reducing device that reduces the pressure underneath the semiconductor device, which further secures the semiconductor device in the heating area. The heating area includes a plurality of heating and cooling zones in which the semiconductor wafer is subjected to various temperatures.

Abstract: When forming a metal silicide within contact openings in complex semiconductor devices, a silicidation of sidewall surface areas of the contact openings may be initiated by forming a silicon layer therein, thereby reducing unwanted diffusion of the refractory metal species into the laterally adjacent dielectric material. In this manner, superior reliability and electrical performance of the resulting contact elements may be achieved on the basis of a late silicide process.

Abstract: A method of cleaving a substrate is disclosed. A species, such as hydrogen or helium, is implanted into a substrate to form a layer of microbubbles. The substrate is then annealed a pressure greater than atmosphere. This annealing may be performed in the presence of the species that was implanted. This diffuses the species into the substrate. The substrate is then cleaved along the layer of microbubbles. Other steps to form an oxide layer or to bond to a handle also may be included.

Abstract: A semiconductor integrated-circuit device using the copper wiring having increased electromigration resistance, low resistivity, and a line width of 70 nm or less, is provided. The present invention is characterized by the annealing treatment wherein a copper wiring having a line width of 70 nm or less is heated with a heating rate of 1 K to 10 K per second, and then the temperature is constantly maintained for a prescribed time duration.

Abstract: This invention describes a semiconductor material of general formula (I) Me12Me21-xMe3xMe4(C11-yC2y)4, in which x stands for a numeric value from 0 to 1, and y stands for a numeric value of 0 to 1, as well as its use as an absorber material in a solar cell. The metal Mel is a metal which is selected from the metals in group 11 of the periodic table of the elements (Cu, Ag or Au). The metals Me2 and Me3 are selected from the elements of the 12th group of the periodic table of elements (Zn, Cd & Hg). The metal Me4 is a metal which is selected from the 4th main group of the periodic table of elements (C, Si, Ge, Sn and Pb). The non-metals C1 and C2 are selected from the group of chalcogenides (S, Se and Te).

Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In general, the ohmic contact structure has a root-mean-squared (RMS) surface roughness of less than 10 nanometers, and more preferably less than or equal to 7.5 nanometers, and more preferably less than or equal to 5 nanometers, and more preferably less than or equal to 2 nanometers, and even more preferably less than or equal to 1.5 nanometers.