Abstract: A mark used in the determination of overlay error comprises sub-features, the sub-features having a smallest pitch approximately equal to the smallest pitch of the product features. The sensitivity to distortions and aberrations is similar as that for the product features. When the mark is developed the sub-features merge and the outline of the larger feature is developed.

Abstract: Embodiments of a method are provided for fabricating a non-planar semiconductor device including a substrate having a plurality of raised crystalline structures formed thereon. In one embodiment, the method includes the steps of amorphorizing a portion of each raised crystalline structure included within the plurality of raised crystalline structures, forming a sacrificial strain layer over the plurality of raised crystalline structures to apply stress to the amorphized portion of each raised crystalline structure, annealing the non-planar semiconductor device to recrystallize the amorphized portion of each raised crystalline structure in a stress-memorized state, and removing the sacrificial strain layer.

Abstract: Provided are a heating device, a substrate processing apparatus, and a method of manufacturing a semiconductor device. The heating device comprises: a heating element including a mountain part and a valley part that are alternately connected in plurality in a meander shape with both ends being fixed; holding body receiving parts respectively installed at ends of the valley parts and formed as cutout parts having a width larger than a width of the valley part; an insulating body installed at an outer circumference of the heating element; a holding body disposed in the holding body receiving part and fixed to the insulating body; the heating element having a ring shape; the insulating body installed in a manner of surrounding the outer circumference of the heating element; and a fixation part configured to fix the heating element to an inner wall of the insulating body.

Abstract: Provided are a heating device, a substrate processing apparatus, and a method of manufacturing a semiconductor device, which can suppress differences between heating bodies, and simultaneously, can suppress shearing of a holder due to thermal deformation of the heating element. The heating device comprises: a heating element including a mountain part and a valley part that are alternately connected in plurality in a meander shape with both ends being fixed; holding body receiving parts respectively installed at ends of the valley parts and formed as cutout parts having a width larger than a width of the valley part; an insulating body installed at an outer circumference of the heating element; and a holding body disposed in the holding body receiving part and fixed to the insulating body.

Abstract: A projection illumination installation for EUV microlithography includes an EUV synchrotron light source for producing EUV used light. An object field is illuminated with the used light using illumination optics. The object field is mapped into an image field using projection optics. A scanning device is used to illuminate the object field by deflecting the used light in sync with a projection illumination period. The result is a projection illumination installation in which the output power from an EUV synchrotron light source can be used as efficiently as possible for EUV projection illumination.

Abstract: An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

Abstract: A substrate heating apparatus includes a top plate arranged above a hot plate so that a vertical space is formed between the hot plate and the top plate. The top plate has an evacuated internal chamber serving as a vacuum insulating layer that suppresses heat transfer from a first surface of the top plate facing the hot plate to a second surface of the top plate opposite to the first surface. When heating the substrate, a gas flow flowing through the space between the hot plate and the top plate is generated.

Abstract: A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer.

Abstract: Disclosed is a method of manufacturing a semiconductor device including: forming a photothermal conversion layer in a second area where a semiconductor layer is formed other than a first area where line is formed; and heating the semiconductor layer with the photothermal conversion layer by irradiating light on the first area and the second area.

Abstract: A surface emitting semiconductor laser which can perform laser oscillation in a single peak beam like that in a single lateral mode and a manufacturing method which can easily manufacture such a laser at a high yield are provided. When a surface emitting semiconductor laser having a post type mesa structure is formed on an n-type semiconductor substrate, a mesa portion is formed and up to a p-side electrode and an n-side electrode are formed. Thereafter, a voltage is applied across the p-side and n-side electrodes and the laser is subjected to a steam atmosphere while extracting output light, thereby forming an Al oxide layer onto a p-type AlwGa1-wAs layer as a top layer of a p-type DBR layer and forming refractive index distribution like that of a concave lens.

Abstract: It is an object of the present invention to provide a laser irradiation apparatus being able to irradiate the irradiation object with the laser beam having homogeneous energy density without complicating the optical system. The laser irradiation apparatus of the present invention comprises a laser oscillator, an optical system for scanning repeatedly a beam spot of the laser beam emitted from the laser oscillator in a uniaxial direction over the surface of the irradiation object, and a position controlling means for moving the position of the irradiation object relative to the laser beam in a direction perpendicular to the uniaxial direction.

Abstract: A semiconductor device includes an alignment mark. A probe beam is scanned on the alignment mark so as to detect a position coordinate of the alignment mark, and the alignment mark comprises a plurality of bar marks which are arranged in a first predetermined interval along a first direction of scanning the detection beam. Each of the plurality of bar marks comprises a plurality of interconnection marks which are arranged along a second direction orthogonal to the first direction, and a first space between adjacent two of the plurality of interconnection marks is shorter than a wavelength of the detection beam within a range of a design constraint.

Abstract: The invention provides an IGZO-based oxide material and a method of producing the same, the IGZO-based oxide material being represented by a composition formula of In2-xGaxZnO4-?, where 0.75<x<1.10 and 0<??1.29161×exp(?x/0.11802)+0.00153, and being formed from a single phase of IGZO having a crystal structure of YbFe2O4.

Abstract: Disclosed herein is an irradiation apparatus including: laser light source; a polarization splitting section configured to split laser light emitted from the laser light source into first linearly polarized light and second linearly polarized light different in polarization direction; a light beam dividing section configured to divide the first or second linearly polarized light into a plurality of light beams; a quarter-wave plate array composed of a plurality of first quarter-wave plates for converting some of the light beams into right circularly polarized light and a plurality of second quarter-wave plates for converting the other of the light beams into left circularly polarized light, the first quarter-wave plates and the second quarter-wave plates being alternately arranged in a first direction perpendicular to an optical axis; and a projection optical system for condensing the right circularly polarized light and the left circularly polarized light toward a work surface to be irradiated.

Abstract: A method of manufacturing a semiconductor device includes performing heat treatment for activating impurities of a transistor having a gate electrode over a gate insulating film with a higher relative permittivity than a silicon oxynitride film or a silicon oxide film. In the heat treatment, a first heat treatment, in which a wafer surface is heated at a temperature of 800 to 1000° C. in 5 to 50 milliseconds by low-output flash lamp annealing or laser annealing, and a second heat treatment, in which the wafer surface is heated at a temperature equal to or more than of 1100° C. in 0.1 to 10 milliseconds by flash lamp annealing or laser annealing with a higher output than in the first heat treatment, are performed in this order.

Abstract: A method of producing an epitaxial substrate for a solid-state imaging device, comprising: forming a gettering sink by injecting laser beam to a semiconductor substrate through one surface thereof, condensing the laser beam to an arbitrarily selected portion of the semiconductor substrate, thereby causing multi-photon absorption process to occur in the portion, and forming a gettering sink having a modified crystal structure; and epitaxially growing at least two epitaxial layers on the semiconductor substrate in which the gettering sink is formed.

Abstract: Laser based processes are used alone or in combination to effectively process doped domains for semiconductors and/or current harvesting structures. For example, dopants can be driven into a silicon/germanium semiconductor layer from a bare silicon/germanium surface using a laser beam. Deep contacts have been found to be effective for producing efficient solar cells. Dielectric layers can be effectively patterned to provide for selected contact between the current collectors and the doped domains along the semiconductor surface. Rapid processing approaches are suitable for efficient production processes.

Abstract: A laser processing method for a semiconductor wafer including a groove forming step of applying a pulsed laser beam having an absorption wavelength to the semiconductor wafer along a division line formed on the semiconductor wafer to thereby form a laser processed groove along the division line on the semiconductor wafer, wherein the pulse width of the pulsed laser beam to be applied in the groove forming step is set to 2 ns or less, and the peak energy density per pulse of the pulsed laser beam is set less than or equal to an inflection point where the depth of the laser processed groove steeply increases with an increase in the peak energy density.

Abstract: A top plate, disposed on an upper portion of a vacuum container so as to face a substrate-placing area of a sample electrode, is provided with an impurity-containing film that contains an impurity, and is formed on a top plate peripheral edge portion area that is a face exposable to a plasma generated in the vacuum container, and is located on a peripheral edge of a top plate center portion area that faces the center portion of the substrate-placing area.

Abstract: A method of electrically connecting an element to wiring includes the steps of forming a conductive fixing member precursor layer at least on wiring provided on a base; and arranging an element having a connecting portion on the wiring such that the connecting portion contacts the conductive fixing member precursor layer, and then heating the conductive fixing member precursor layer to form a conductive fixing member latter, thereby fixing the connecting portion of the element to the wiring, with the conductive fixing member layer therebetween, wherein the conductive fixing member precursor layer is composed of a solution-tape conductive material.

Abstract: Methods for implanting ions into a substrate by a plasma immersion ion implanting process are provided. In one embodiment, a method for implanting ions into a substrate includes providing a substrate into a processing chamber, generating a plasma from a gas mixture including a reacting gas and a etching gas in the chamber, adjusting the ratio between the reacting gas and the etching gas in the supplied gas mixture and implanting ions from the plasma into the substrate. In another embodiment, the method includes providing a substrate into a processing chamber, supplying a gas mixture including reacting gas and a halogen containing reducing gas into the chamber, forming a plasma from the gas mixture, gradually increasing the ratio of the etching gas in the gas mixture, and implanting ions from the gas mixture into the substrate.

Abstract: A method for dividing a wafer into a plurality of chips is provided. The method includes providing recesses in a surface of the wafer at positions along boundaries between regions to become the individual chips, providing fragile portions having a predetermined width inside the wafer at positions along the boundaries by irradiation of the other surface of the wafer with a laser beam whose condensing point is placed inside the wafer, the fragile portions including connected portions at least at one of the surfaces of the wafer, and dividing the wafer at the fragile portions into the individual chips by applying an external force to the wafer.

Abstract: Embodiments of the invention contemplate a method, apparatus and system that are used to support and position a substrate on a surface that is at a different temperature than the initial, or incoming, substrate temperature. Embodiments of the invention may also include a method of controlling the transfer of heat between a substrate and substrate support positioned in a processing chamber. The apparatus and methods described herein generally may also provide an inexpensive and simple way of accurately positioning a substrate on a substrate support that is positioned in a semiconductor processing chamber. Substrate processing chambers that can benefit from the various embodiments described herein include, but are not limited to RTP, CVD, PVD, ALD, plasma etching, and/or laser annealing chambers.

Abstract: A device comprises a substrate, a micro electro-mechanical systems (MEMS) structure, and a dielectric film. The substrate has a first side and a second side, the second side opposite the first side. The MEMS structure is formed on the first side of the substrate. The cavity is formed in the substrate directly opposite the MEMS structure. The cavity has an opening formed on the second side. The dielectric film is attached to the second side of the substrate and completely covering the opening. In one embodiment, the MEMS structure is a diaphragm for a microphone. Another embodiment includes a method for forming the device.

Abstract: A method for forming patterns on a wafer includes forming a fence having a sloped face in an edge portion of the wafer. The sloped face is direct to an inside of the wafer. A first photoresist layer is formed which extends to cover the fence on the wafer. First photoresist patterns are formed by performing a first exposure and development on the first photoresist layer. An etch process is performed using the first photoresist patterns and the fence as an etch mask. The fence is formed by selectively exposing a negative resist using a light shielding blade, and at this time, the first photoresist layer is formed including a positive resist.

Abstract: A semiconductor wafer in which a carbon thin film is formed on a surface of a silicon substrate implanted with impurities is irradiated with flash light emitted from flash lamps. Absorbing the flash light causes the temperature of the carbon thin film to increase. The surface temperature of the silicon substrate implanted with impurities is therefore increased to be higher than that in a case where no thin film is formed, and the sheet resistance value can be thereby decreased. When the semiconductor wafer with the carbon thin film formed thereon is irradiated with flash light in high concentration oxygen atmosphere, since the carbon of the thin film is oxidized to be vaporized, removal of the thin film is performed concurrently with flash heating.

Abstract: A method and apparatus for thermally processing a substrate is provided. A substrate is disposed within a processing chamber configured for thermal processing by directing electromagnetic energy toward a surface of the substrate. An energy blocker is provided to block at least a portion of the energy directed toward the substrate. The blocker prevents damage to the substrate from thermal stresses as the incident energy approaches an edge of the substrate.

Abstract: A manufacturing method of laser processed parts in which at least a pressure-sensitive adhesive layer is provided on a base material as a pressure-sensitive adhesive sheet for laser processing, using a material having specified physical properties. This method comprises adhering the pressure-sensitive adhesive sheet for laser processing to the laser beam exit side of the work by way of the pressure-sensitive adhesive layer, processing the work by irradiating the work with a laser beam of within 2 times of the irradiation intensity for forming a through-hole in the work, at higher than the irradiation intensity of threshold for inducing ablation of the work, and peeling the pressure-sensitive adhesive sheet for laser processing from the work after the machining. Therefore, contamination of the work surface by decomposition products can be effectively suppressed, and laser processed parts can be manufactured easily and at high production efficiency.

Abstract: Methods of producing high uniformity in thin film transistor devices fabricated on laterally crystallized thin films are described. A thin film transistor (TFT) includes a channel area disposed in a crystalline substrate, which has grain boundaries that are approximately parallel with each other and are spaced apart with approximately equal spacings. The shape of the channel area includes a non-equiangular polygon that has two opposing side edges that are oriented substantially perpendicular to the grain boundaries. The polygon further has an upper edge and a lower edge. At least a portion of each of the upper and lower edges is oriented at a tilt angle with respect to the grain boundaries. The tilt angles are selected such that the number of grain boundaries covered by the polygon is independent of the location of the channel area within the crystalline substrate.

Abstract: To provide a substrate treatment apparatus capable of performing temperature control in a reaction tube with accuracy. A substrate treatment apparatus 100 includes: a reaction tube 42 for treating a substrate 54; a heater 46 for heating the substrate 54 in the reaction tube 42; a cooling air channel 72 for circulating cooling air 70 outside the reaction tube 42; and a thermocouple 82 for detecting temperature around the reaction tube 42. The thermocouple 82 is disposed in the cooling air channel 72 for circulating cooling air 70 in a state where the thermocouple 82 is covered with a protection tube 86, and a cover 88 for intercepting flow toward the protection tube 86 of the cooling air 70 is disposed outside the protection tube 86.

Abstract: Methods and apparatus for providing a process gas to a substrate in a processing system are disclosed herein. In some embodiments, the substrate processing system may include a process chamber having a substrate support disposed therein; a light source disposed above the process chamber to direct energy towards the substrate support; and a window assembly disposed between the light source and the substrate support to allow light energy provided by the light source to enter the process chamber towards the substrate support, wherein the window assembly includes an inlet to receive a process gas and one or more outlets to distribute the process gas into the process chamber.

Abstract: A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method includes providing a silicon oxide layer with a thickness of less than or equal to 25 nanometers on one of a donor substrate or a receiver substrate or on both substrates, heat treating the substrate(s) that contains the silicon oxide layer at 900° C. to 1,200° C. under a neutral or reducing atmosphere that contains at least one of argon or hydrogen to form layer trapping through-holes inside the silicon oxide, bonding the substrates together at a bonding interface with the silicon oxide layer(s) positioned between them, reinforcing the bonding by annealing the substrates at 25° C. to 500° C. such that the trapping holes retaining gas species at the bonding interface, and transferring an active layer as a portion of the donor substrate onto the receiver substrate to obtain the heterostructure.

Abstract: There is provided a method of forming a pattern on a group III nitride semiconductor substrate. A method of forming a pattern on a group III nitride semiconductor substrate according to an aspect of the invention may include: irradiating a laser beam onto at least one first region for preventing etching in a group III nitride semiconductor substrate; and etching at least one second region exclusive of the first region using the first region irradiated with the laser beam as a mask.

Abstract: A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ?5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization.

Abstract: A plasma processing apparatus includes a process chamber, a platen positioned in the process chamber for supporting a workpiece, a source configured to generate a plasma in the process chamber having a plasma sheath adjacent to the front surface of the workpiece, and an insulating modifier. The insulating modifier has a gap, and a gap plane, where the gap plane is defined by portions of the insulating modifier closest to the sheath and proximate the gap. A gap angle is defined as the angle between the gap plane and a plane defined by the front surface of the workpiece. Additionally, a method of having ions strike a workpiece is disclosed, where the range of incident angles of the ions striking the workpiece includes a center angle and an angular distribution, and where the use of the insulating modifier creates a center angle that is not perpendicular to the workpiece.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include forming an identification mark on a portion of a backside of an individual die of a wafer by utilizing laser assisted CVD, wherein the formation of the identification mark is localized to a focal spot of the laser.

Abstract: Rapid thermal processing of freestanding gallium nitride wafers is used to form semiconductor devices. This high speed process is enabled by the low thermal inertia of the growth substrate and the use of a low thermal inertia susceptor. The use of a low thermal inertia susceptor consisting of, but not limited to, silicon carbide, silicon carbide coated graphite, and/or other platen materials. Infrared (IR) heating is a preferred approach for increasing the temperature of the freestanding gallium nitride films via the susceptor but Radio Frequency (RF) and other methods are also approaches.

Abstract: The present invention provides a residue-removing solution for use after a dry process, the residue-removing solution being capable of preventing minute cracks on a Cu surface, which has heretofore been unresolved with known polymer-removing solutions; and a method for manufacturing semiconductor devices using the residue-removing solution. More specifically, the invention relates to a residue-removing solution for removing residues present on semiconductor substrates after dry etching and/or ashing, the solution containing water and at least one component selected from the group consisting of (a) a keto acid, (b) a keto acid salt, and (c) an aldehyde acid salt; and a method for removing residues using the residue-removing solution.

Abstract: A method for fabricating a photovoltaic element with stabilised efficiency is proposed. The method comprises the following steps: preparing a boron-doped, oxygen-containing silicon substrate; forming an emitter layer on a surface of the silicon substrate; and a stabilisation treatment step. The stabilisation treatment step comprises keeping the temperature of the substrate during a treatment time within a selectable temperature range having a lower temperature limit of 50° C., preferably 90° C., more preferably 130° C. and even more preferably 160° C. and an upper temperature limit of 230° C., preferably 210° C., more preferably 190° C. and even more preferably 180° C., and generating excess minority carriers in the silicon substrate during the treatment time, for example, by illuminating the substrate or by applying an external voltage. This method can be used to fabricate a photovoltaic element, e.g.

Abstract: The present invention provides an apparatus and method for rapid and uniform thermal treatment of semiconductor workpieces in two closely arranged thermal treatment chambers with a retractable door between them. The retractable door moves in between two thermal treatment chambers during heating or cooling process, and additional heating and cooling sources are provided for double-side thermal treatment of the semiconductor workpiece.

Abstract: A semiconductor furnace suitable for chemical vapor deposition processing of wafers. The furnace includes a thermal reaction chamber having a top, a bottom, a sidewall, and an internal cavity for removably holding a batch of vertically stacked wafers. A heating system is provided that includes a plurality of heaters arranged and operative to heat the chamber. The heating system includes at least one top heater; at least one bottom heater, and a plurality of sidewall heaters spaced along the height of the reaction chamber to control temperature variations within in the chamber and promote uniform film deposit thickness on the wafers.

Abstract: A method of repairing a nonvolatile semiconductor memory device to eliminate defects includes monitoring a memory endurance indicator for a nonvolatile semiconductor memory device contained in a semiconductor package. It is determined whether that the memory endurance indicator exceeds a predefined limit. Finally, in response to determining that the memory endurance indicator exceeds the predefined limit, the device is annealed.

Abstract: Disclosed herein is a rapid annealing method in a mixed structure composed of a heat treatment-requiring material, dielectric layer and conductive layer, comprising that during rapid annealing on a predetermined part of the heat treatment-requiring material, by instantaneously generated intense heat due to Joule heating by application of an electric field to the conductive layer, the potential difference between the heat treatment-requiring material and the conductive layer is set lower than the dielectric break-down voltage of the dielectric layer, thereby preventing generation of arc by dielectric breakdown of the dielectric layer during the annealing.

Abstract: A method for producing an integrated circuit including a semiconductor is disclosed. In one embodiment, crystal defects are produced by irradiation in the material of the underlying semiconductor substrate which crystal defects form an inhomogeneous crystal defect density distribution in the vertical direction of the semiconductor component and lead to a corresponding inhomogeneous distribution of the carrier lifetime.

Abstract: A semiconductor product including a substrate, a semiconductor chip fitted to the substrate, and a layer, which contains coated particles, located adjacent to the semiconductor chip, wherein the coated particles have a ferromagnetic, ferrimagnetic or paramagnetic core and a coating.

Abstract: An apparatus includes a process chamber configured to perform an ion implantation process. A cooling platen or electrostatic chuck is provided within the process chamber. The cooling platen or electrostatic chuck is configured to support a semiconductor wafer. The cooling platen or electrostatic chuck has a plurality of temperature zones. Each temperature zone includes at least one fluid conduit within or adjacent to the cooling platen or electrostatic chuck. At least two coolant sources are provided, each fluidly coupled to a respective one of the fluid conduits and configured to supply a respectively different coolant to a respective one of the plurality of temperature zones during the ion implantation process. The coolant sources include respectively different chilling or refrigeration units.

Abstract: Oxygen is selectively removed from metal-containing materials in a partially-fabricated integrated circuit. In some embodiments, the partially-fabricated integrated circuit has exposed silicon and metal-containing materials, e.g., as part of a transistor. The silicon and metal-containing material are oxidized. Oxygen is subsequently removed from the metal-containing material by an anneal in an atmosphere containing a reducing agent. Advantageously, the silicon oxide formed by the silicon oxidation is maintained while oxygen is removed from the metal-containing material, thereby leaving a high quality metal-containing material along with silicon oxide.

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches.

Abstract: An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.

Abstract: A method for manufacturing the compound semiconductor substrate having a reduced dislocation density at an interface between a Si substrate. Contaminants, such as organic matter and metal, on a surface of a Si substrate are removed whereby a flat oxide film is formed. The oxide film on the surface is removed by using an aqueous hydrogen fluoride solution, whereby hydrogen termination treatment is performed. Immediately after being subjected to the hydrogen termination treatment the temperature of the Si substrate is raised in a vacuum apparatus. If the substrate temperature is raised without any operation, the termination hydrogen is released. Before the hydrogen is released, pre-irradiation with As is performed. Thus, an interface between the Si substrate and the compound semiconductor layer is prepared. Several minutes later, irradiation with Ga and As is performed. Thereby, the compound semiconductor is formed.