Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.

Abstract: Provided are a substrate processing apparatus and a method of manufacturing a semiconductor device that are capable of uniformly heating a substrate while reducing an increase in substrate temperature to reduce a thermal budget. The substrate processing apparatus includes a process chamber configured to process a substrate; a substrate support unit installed in the process chamber to support the substrate; a microwave supply unit configured to supply a microwave toward a process surface of the substrate supported by the substrate support unit, the microwave supply unit including a microwave radiating unit radiating the microwave supplied from a microwave source to the process chamber while rotating; a partition installed between the microwave supply unit and the substrate support unit; a cooling unit installed at the substrate support unit; and a control unit configured to control at least the substrate support unit, the microwave supply unit and the cooling unit.

Abstract: Methods and apparatus provide for: a first source of plasma, wherein the plasma includes a first species of ions; a second source of plasma, wherein the plasma includes a second species of ions; selection of the plasma from the first and second sources; and acceleration the first species of ions or the second species of ions toward a semiconductor wafer.

Abstract: The present invention generally relates to methods of controlling UV lamp output to increase irradiance uniformity. The methods generally include determining a baseline irradiance within a chamber, determining the relative irradiance on a substrate corresponding to a first lamp and a second lamp, and determining correction or compensation factors based on the relative irradiances and the baseline irradiance. The lamps are then adjusted via closed loop control using the correction or compensation factors to individually adjust the lamps to the desired output. The lamps may optionally be adjusted to equal irradiances prior to adjusting the lamps to the desired output. The closed loop control ensures process uniformity from substrate to substrate. The irradiance measurement and the correction or compensation factors allow for adjustment of lamp set points due to chamber component degradation, chamber component replacement, or chamber cleaning.

Abstract: Embodiments of the invention contemplate a method, apparatus and system that are used to support and position a substrate on a surface that is at a different temperature than the initial, or incoming, substrate temperature. Embodiments of the invention may also include a method of controlling the transfer of heat between a substrate and substrate support positioned in a processing chamber. The apparatus and methods described herein generally may also provide an inexpensive and simple way of accurately positioning a substrate on a substrate support that is positioned in a semiconductor processing chamber. Substrate processing chambers that can benefit from the various embodiments described herein include, but are not limited to RTP, CVD, PVD, ALD, plasma etching, and/or laser annealing chambers.

Abstract: A thin film transistor array panel includes: a substrate; a gate line and a storage electrode that are disposed on the substrate; a data line that crosses the gate line and storage electrode line; a thin film transistor that is connected with the gate line and data line; and a pixel electrode that is connected to the thin film transistor. The storage electrode includes a first storage electrode that is parallel to the gate line, second storage electrodes that extend on opposing sides of the data line from the first storage electrode, a connection part that crosses the data line and connects pairs of the second storage electrodes, and a connection bridge that crosses the gate line and connects a second storage electrode to a second storage electrode of an adjacent pixel.

Abstract: A substrate processing apparatus includes a processing chamber configured to process a substrate, a substrate support member provided within the processing chamber to support the substrate, a microwave generator provided outside the processing chamber, a waveguide launch port configured to supply a microwave generated by the microwave generator into the processing chamber, wherein the central position of the waveguide launch port is deviated from the central position of the substrate supported on the substrate support member and the waveguide launch port faces a portion of a front surface of the substrate supported on the substrate support member, and a control unit configured to change a relative position of the substrate support member in a horizontal direction with respect to the waveguide launch port.

Abstract: Embodiments of the present invention generally relate to an apparatus and methods for uniformly heating substrates in a processing chamber. In one embodiment, an apparatus generally includes a substrate supporting structure that is able to help minimize the temperature variation across each of the substrates during thermal processing. In one configuration, a substrate supporting structure is adapted to selectively support a substrate carrier to control the heat lost from regions of each of the substrates disposed on the substrate carrier. The substrate supporting structure is thus configured to provide a uniform temperature profile across each of the plurality of substrates during processing.

Abstract: Provided is a method for manufacturing a film structure. The method for manufacturing the film structure n includes forming a layer of a precursor material on a substrate, preheating the precursor material, and irradiating the precursor material with microwave radiation to form the film structure.

Abstract: The invention relates to a process for fabricating a heterostructure. This process comprises heating an intermediate heterostructure. The intermediate heterostructure comprises a crystalline strain relaxation layer interposed directly between a first substrate and a strained layer of crystalline semiconductor material. The process further comprises causing plastic deformation of the crystalline strain relaxation layer and elastic deformation of the strained layer of crystalline semiconductor material to at least partially relax the strained layer of crystalline semiconductor material.

Abstract: A semiconductor device manufacturing method includes loading a substrate, on which a high-k film is formed, into a processing chamber, performing a reforming process by heating the high-k film through irradiation of a microwave on the substrate, and unloading the substrate from the processing chamber.

Abstract: The embodiment provides a semiconductor MP wafer process including processing a plurality of MP wafers in a lot or batch with a first process step. The plurality of the MP wafers is split into an MP wafer group-1 and an MP wafer group-2. At least one of the MP wafers of the MP wafer group-1 is processed with a second process step-1 and at least one of the MP wafers of the MP wafer group-2 is processed with a second process step-2 to form different device components on the MP wafers of the MP wafer group-1 and group-2, respectively. At least one of the MP wafers of the MP wafer group-1 is processed with a third process step-3 and at least one of the MP wafers of the MP wafer group-2 is processed with a third process step-4 to form a substantially same device component on the MP wafers.

Abstract: A process is disclosed for annealing a single crystal silicon wafer having a front surface and a back surface, and an oxide layer disposed on the front surface of the wafer extending over substantially all of the radial width. The process includes annealing the wafer in an annealing chamber having an atmosphere comprising oxygen. The process also includes maintaining a partial pressure of water above a predetermined value such that the wafer maintains the oxide layer through the annealing process. The annealed front surface is substantially free of boron and phosphorus.

Abstract: Rapid thermal annealing methods and systems for annealing patterned substrates with minimal pattern effect on substrate temperature non-uniformity are provided. The rapid thermal annealing system includes a front-side heating source and a backside heating source. The backside heating source of the rapid thermal annealing system supplies a dominant amount of heat to bring the substrate temperature to the peak annealing temperature. The front-side heating source contributes to heat up the environment near the front-side of the substrate to a temperature lower than about 100° C. to about 200° C. less than the peak annealing temperature. The asymmetric front-side and backside heating for rapid thermal annealing reduce or eliminate pattern effect and improve WIW and WID device performance uniformity.

Abstract: Defects in a semiconductor substrate due to ion implantation are minimized by forming an implant region in the semiconductor substrate and subjecting the semiconductor substrate to a first anneal to recrystallize the semiconductor substrate. The semiconductor substrate is subjected to a second anneal to suppress diffusion of implanted ions in the semiconductor substrate. The first anneal being at a lower temperature and longer duration than the second anneal.

Abstract: A method of reducing the roughness profile in a plurality of patterned resist features. Each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall, wherein each patterned resist feature comprises a mid frequency line width roughness and a low frequency linewidth roughness. A plurality of ion exposure cycles are performed, wherein each ion exposure cycle comprises providing ions at a tilt angle of about five degrees or larger upon the first sidewall, and providing ions at a tilt angle of about five degrees or larger upon the second sidewall. Upon the performing of the plurality of ion exposure cycles the mid frequency and low frequency linewidth roughness are reduced.

Abstract: Disclosed are methods of manufacturing a semiconductor device. The method of manufacturing one semiconductor device includes forming a transistor structure on a semiconductor substrate, forming a metal interconnection layer on the transistor structure, forming a protective layer on the metal interconnection layer, and implanting hydrogen ions into the semiconductor substrate having the protective layer by using a hydrogen ion implanter. Hydrogen ions are stably and effectively implanted into a selected region by using a hydrogen ion implanter in the manufacturing process of the semiconductor device, thereby facilitating the manufacturing process and improving the performance of the semiconductor device.

Abstract: A copper line having self assembled monolayer for use in ULSI semiconductor devices and methods of making the same are presented. The copper line includes an interlayer dielectric, a self-assembled monolayer, catalytic particles on the monolayer, and a copper layer on the monolayer with the catalytic particles. The method includes the steps of forming an interlayer dielectric on a semiconductor substrate having a metal line forming region; forming a self-assembled monolayer on the metal line forming region; adsorbing catalytic particles on the self-assembled monolayer; forming using an electroless process a copper seed layer on the self-assembled monolayer having the catalytic particles adsorbed thereto; and forming a copper layer on the copper seed layer to fill in the metal line forming region.

Abstract: A GaN sample in a sealed enclosure is heated very fast to a high temperature above the point where GaN is thermodynamically stable and is then cooled down very fast to a temperature where it is thermodynamically stable. The time of the GaN exposure to a high temperature range above its thermodynamic stability is sufficiently short, in a range of few seconds, to prevent the GaN from decomposing. This heating and cooling cycle is repeated multiple times without removing the sample from the enclosure. As a result, by accumulating the exposure time in each cycle, the GaN sample can be exposed to a high temperature above its point of thermodynamic stability for a long time but the GaN sample integrity is maintained (i.e., the GaN doesn't decompose) due to the extremely short heating duration of each single cycle.

Abstract: Provided are systems and methods for processing the surface of substrates that scan a laser beam at one or more selected orientation angles. The orientation angle or angles may be selected to reduce substrate warpage. When the substrates are semiconductor wafers having microelectronic devices, the orientation angles may be selected to produce controlled strain and to improve electronic performance of the devices.

Abstract: The present invention provides a method of processing a substrate and a method of manufacturing a silicon carbide (SiC) substrate in which, when annealing processing is performed on a crystalline silicon carbide (SiC) substrate, the occurrence of surface roughness is suppressed. A substrate processing method according to an embodiment of the present invention includes a step of performing plasma irradiation on a single crystal silicon carbide (SiC) substrate (1) and a step of performing high temperature heating processing on the single crystal silicon carbide (SiC) substrate (1) in which the plasma irradiation is performed.

Abstract: A method of depositing a metal film on a substrate with patterned features includes placing a substrate with patterned features into a photo-induced chemical vapor deposition (PI-CVD) process chamber. The method also includes depositing a metal film by PI-CVD to fill the patterned features from bottom up.

Abstract: The present invention relates to a stress-enhanced transistor and a method for forming the same. The method for forming the transistor according to the present invention comprises the steps of forming a mask layer on a semiconductor substrate on which a gate has been formed, so that the mask layer covers the gate and the semiconductor substrate; patterning the mask layer so as to expose at least a portion of each of a source region and a drain region; amorphorizing the exposed portions of the source region and the drain region; removing the mask layer; and annealing the semiconductor substrate so that a dislocation is formed in the exposed portion of each of the source region and the drain region.

Abstract: The present invention provides a semiconductor device having an improved silicon oxide film as a gate insulation film of a Metal Insulator Semiconductor structure and a method of making the same.

Abstract: Embodiments of the present invention provide apparatus and method for improving gas distribution during thermal processing. One embodiment of the present invention provides an apparatus for processing a substrate comprising a chamber body defining a processing volume, a substrate support disposed in the processing volume, wherein the substrate support is configured to support and rotate the substrate, a gas inlet assembly coupled to an inlet of the chamber body and configured to provide a first gas flow to the processing volume, and an exhaust assembly coupled to an outlet of the chamber body, wherein the gas inlet assembly and the exhaust assembly are disposed on opposite sides of the chamber body, and the exhaust assembly defines an exhaust volume configured to extend the processing volume.

Abstract: A system, method and masking arrangement are provided of enhancing the width of polycrystalline grains produced using sequential lateral solidification using a modified mask pattern is disclosed. One exemplary mask pattern employs rows of diamond or circular shaped areas in order to control the width of the grain perpendicular to the direction of primary crystallization.

Abstract: There is provided a method of forming a pattern on a group III nitride semiconductor substrate. A method of forming a pattern on a group III nitride semiconductor substrate according to an aspect of the invention may include: irradiating a laser beam onto at least one first region for preventing etching in a group III nitride semiconductor substrate; and etching at least one second region exclusive of the first region using the first region irradiated with the laser beam as a mask.

Abstract: Sapphire substrates are used chiefly for epitaxial growth of nitride semiconductor layers, to provide a sapphire substrate of which the shape and/or amount of warping can be controlled efficiently and precisely and of which substrate warping that occurs during layer formation can be suppressed and substrate warping behavior can be minimized, to provide nitride semiconductor layer growth bodies, nitride semiconductor devices, and nitride semiconductor bulk substrates using such substrates, and to provide a method of manufacturing these products. Reformed domain patterns are formed within a sapphire substrate and the warp shape and/or amount of warping of the sapphire substrate are controlled by means of multiphoton absorption by condensing and scanning a pulsed laser through a polished surface of the sapphire substrate.

Abstract: A plasma processing apparatus includes a process chamber, a platen positioned in the process chamber for supporting a workpiece, a source configured to generate a plasma in the process chamber having a plasma sheath adjacent to the front surface of the workpiece, and an insulating modifier. The insulating modifier has a gap, and a gap plane, where the gap plane is defined by portions of the insulating modifier closest to the sheath and proximate the gap. A gap angle is defined as the angle between the gap plane and a plane defined by the front surface of the workpiece. Additionally, a method of having ions strike a workpiece is disclosed, where the range of incident angles of the ions striking the workpiece includes a center angle and an angular distribution, and where the use of the insulating modifier creates a center angle that is not perpendicular to the workpiece.

Abstract: A semiconductor device and a method of manufacturing are provided. In some embodiments, a backside annealing process such that a first heat source is placed along a backside of the substrate. In other embodiments, the first heat source is used in combination with an anti-reflection dielectric (ARD) layer is deposited over the substrate. In yet other embodiments, a second heat source is placed along a front side of the substrate in addition to the first heat source placed on the backside of the substrate. In yet other embodiments, a heat shield may be placed between the substrate and the second heat source on the front side of the substrate. In yet further embodiments, a single heat source may be used on the front side of the substrate in combination with the ARD layer. A reflectivity scan may be performed to determine which anneal stage (RTA or MSA or both) to place thermal leveling solution.

Abstract: Embodiments of the invention contemplate a method, apparatus and system that are used to support and position a substrate on a surface that is at a different temperature than the initial, or incoming, substrate temperature. Embodiments of the invention may also include a method of controlling the transfer of heat between a substrate and substrate support positioned in a processing chamber. The apparatus and methods described herein generally may also provide an inexpensive and simple way of accurately positioning a substrate on a substrate support that is positioned in a semiconductor processing chamber. Substrate processing chambers that can benefit from the various embodiments described herein include, but are not limited to RTP, CVD, PVD, ALD, plasma etching, and/or laser annealing chambers.

Abstract: The disclosure relates to using magnetic fields for the purposes of modifying the absorption characteristics of materials, such as semiconductor materials, to both tune the materials to specific wavelengths and to enhance the absorption of the materials by concentrating the continuum of states of the conduction and valence bands into magnetic field-dependent Landau levels.

Abstract: A memristor with a switching layer that includes a composite of multiple phases is disclosed. The memristor comprises: a first electrode; a second electrode spaced from the first electrode; and a switching layer positioned between the first electrode and the second electrode, the switching layer comprising the multi-phase composite system that comprises a first majority phase comprising a relatively insulating matrix of a switching material and a second minority phase comprising a relatively conducting material for forming at least one conducting channel in the switching layer during a fabrication process of the memristor. A method of making the memristor and a crossbar employing the memristor are also disclosed.

Abstract: An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a plurality areas defined laterally in the substrate through a bottom surface of the substrate; and a light source facing a top surface of the substrate, configured to irradiate a pulsed light at a pulse width of about 0.1 ms to about 100 ms on the entire top surface of the substrate.

Abstract: Embodiments of this doping method may be used to improve junction formation. An implant species, such as helium or another noble gas, is implanted into a workpiece to a first depth. A dopant is deposited on a surface of the workpiece. During an anneal, the dopant diffuses to the first depth. The noble gas ions may at least partially amorphize the workpiece during the implant. The workpiece may be planar or non-planar. The implant and deposition may occur in a system without breaking vacuum.

Abstract: In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.

Abstract: A composition and method for formation of ohmic contacts on a semiconductor structure are provided. The composition includes a TiAlxNy material at least partially contiguous with the semiconductor structure. The TiAlxNy material can be TiAl3. The composition can include an aluminum material, the aluminum material being contiguous to at least part of the TiAlxNy material, such that the TiAlxNy material is between the aluminum material and the semiconductor structure. The method includes annealing the composition to form an ohmic contact on the semiconductor structure.

Abstract: A method and apparatus for implanting a semiconductor substrate with boron clusters. A substrate is implanted with octadecaborane by plasma immersion or ion beam implantation. The substrate surface is then melted, resolidified, and annealed to completely dissociate and activate the boron clusters.

Abstract: A method of forming a polycrystalline silicon layer and an atomic layer deposition apparatus used for the same. The method includes forming an amorphous silicon layer on a substrate, exposing the substrate having the amorphous silicon layer to a hydrophilic or hydrophobic gas atmosphere, placing a mask having at least one open and at least one closed portion over the amorphous silicon layer, irradiating UV light toward the amorphous silicon layer and the mask using a UV lamp, depositing a crystallization-inducing metal on the amorphous silicon layer, and annealing the substrate to crystallize the amorphous silicon layer into a polycrystalline silicon layer. This method and apparatus provide for controlling the seed position and grain size in the formation of a polycrystalline silicon layer.

Abstract: An object is to provide a single crystal semiconductor layer with extremely favorable characteristics without performing CMP treatment or heat treatment at high temperature. Further, an object is to provide a semiconductor substrate (or an SOI substrate) having the above single crystal semiconductor layer. A first single crystal semiconductor layer is formed by a vapor-phase epitaxial growth method on a surface of a second single crystal semiconductor layer over a substrate; the first single crystal semiconductor layer and a base substrate are bonded to each other with an insulating layer interposed therebetween; and the first single crystal semiconductor layer and the second single crystal semiconductor layer are separated from each other at an interface therebetween so as to provide the first single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween. Thus, an SOI substrate can be manufactured.

Abstract: A thermal processing chamber with a dielectric barrier discharge (DBD) lamp assembly and a method for using the same are provided. In one embodiment, a thermal processing chamber includes a chamber body and a dielectric barrier discharge lamp assembly. The dielectric barrier discharge lamp assembly further comprises a first electrode, a second electrode and a dielectric barrier. The dielectric barrier discharge lamp assembly is positioned between the first electrode and the second electrode. The dielectric barrier defines a discharge space between the dielectric barrier and the second electrode. A circuit arrangement is coupled to the first and second electrodes, and is adapted to operate the dielectric barrier discharge lamp assembly.

Abstract: A deflecting mirror which deflects a laser beam emitted from a laser oscillator, a transfer lens, a cylindrical lens array which divides the laser beam having passed through the transfer lens into a plurality of laser beams, and a condensing lens which superposes the laser beams formed in the cylindrical lens array are included. The following formula is satisfied: 1/f=1/(a+b)+1/c, when: “a” is a distance between an emission opening of the laser oscillator and the deflecting mirror; “b” is a distance between the deflecting mirror and the transfer lens; “c” is a distance between the transfer lens and an incidence plane of the cylindrical lens array; and “f” is a focal length of the transfer lens.

Abstract: A semiconductor wafer is set in a laser irradiation apparatus, and laser beam irradiation is performed while the semiconductor wafer is moved. At this time, a laser beam emitted from a laser generating apparatus is condensed by a condensing lens so that the condensing point (focal point) is positioned at a depth of several tens of gm or so from one surface of the semiconductor wafer. Thereby, the crystal structure of the semiconductor wafer in the position having such a depth is modified, and a gettering sink is formed.

Abstract: A method for manufacturing an organic light emitting diode (OLED) array is provided that includes applying an energizing signal to at least one of the OLED pixels in the array. The energizing signal exceeds a threshold level. The method also includes reducing the energizing signal and identifying an OLED in the array that continues to remain energized. The method further includes irradiating the identified OLED to degrade the organic material in the OLED. A method of performing quality control in a manufacturing process of an OLED array is provided. The method includes determining an intensity, a time and a wavelength of radiation sufficient to render an OLED of the OLED array inoperative by degrading organic material in the OLED. A system of performing quality control in a manufacturing process of an OLED array is provided. A computer-readable medium having stored thereon computer-executable instructions is provided.

Abstract: A method of forming an integrated circuit structure includes providing a silicon substrate, and implanting a p-type impurity into the silicon substrate to form a p-type region. After the step of implanting, performing an anneal to form a silicon oxide region, with a portion of the p-type region converted to the silicon oxide region.

Abstract: A method of manufacturing a functional film by which a functional film formed on a film formation substrate can be easily peeled from the film formation substrate. The method includes the steps of: (a) forming a separation layer on a substrate by using an inorganic material which is decomposed to generate a gas by being applied with an electromagnetic wave; (b) forming a layer to be peeled containing a functional film, which is formed by using a functional material, on the separation layer; and (c) applying the electromagnetic wave toward the separation layer so as to peel the layer to be peeled from the substrate or reduce bonding strength between the layer to be peeled and the substrate.

Abstract: There are provided a plasma doping method and an apparatus which have excellent reproducibility of the concentration of impurities implanted into the surfaces of samples. In a vacuum container, in a state where gas is ejected toward a substrate placed on a sample electrode through gas ejection holes provided in a counter electrode, gas is exhausted from the vacuum container through a turbo molecular pump as an exhaust device, and the inside of the vacuum container is maintained at a predetermined pressure through a pressure adjustment valve, the distance between the counter electrode and the sample electrode is set to be sufficiently small with respect to the area of the counter electrode to prevent plasma from being diffused outward, and capacitive-coupled plasma is generated between the counter electrode and the sample electrode to perform plasma doping. The gas used herein is a gas with a low concentration which contains impurities such as diborane or phosphine.

Abstract: An epitaxial growth substrate includes: a surface not roughening over a surface roughness of 10 nm during a temperature-rise process by which a temperature increases until reaching a growth temperature of a nitride-based compound semiconductor layer, the growth temperature being 900° C. to 1050° C., wherein the nitride-based compound semiconductor layer is epitaxially grown directly on the epitaxial growth substrate at the growth temperature.

Abstract: Provided is technology for preventing breakage of an induction target part of a substrate processing apparatus using an induction heating method.

Abstract: The invention relates to a method for preparing a self-supporting crystallized silicon thin film having a grain size of more than 1 mm. The invention also relates to the use of said method for preparing self-supporting silicon bands and to the bands thus obtained.