Abstract: A method of fabricating a semiconductor integrated circuit device uses a mold which is provided with a plurality of air vents and movable pins which are formed such that the movable pins include grooves in the distal ends thereof which project into the air vents. By clamping the mold in a state such that the distal ends of the movable pins are pushed against a multi-cavity board at the time of clamping the mold, resin can be filled while leaking air inside the cavity through the grooves formed in the distal ends of the movable pins by setting the depths of the respective air vents to a fixed value irrespective of the irregularities in thickness of the multi-cavity boards. Accordingly, it is possible to prevent insufficient filling of resin in the cavity, the leaking of resin or defective welding, whereby the yield rate of products can be enhanced.

Abstract: The present invention relates to a semiconductor component that has a substrate and a projecting electrode. The projecting electrode has a substrate face, which faces the substrate and which comprises a first substrate-face section separated from the substrate by a gap. The gap allows a stress-compensating deformation of the projecting electrode relative to the substrate. The substrate face of the projecting electrode further comprises a second substrate-face section, which is in fixed mechanical and electrical connection with the substrate. Due to a smaller footprint of mechanical connection between the projecting electrode and the substrate, the projecting electrode can comply in three dimensions to mechanical stress exerted, without passing the same amount of stress on to the substrate, or to an external substrate in an assembly. This results in an improved lifetime of an assembly, in which the semiconductor component is connected to an external substrate by the projecting electrode.

Abstract: There is provided a semiconductor device that suppresses the occurrence of resin burrs to ensure favorable electrical connectivity and bond strength, and a manufacturing method for such semiconductor device. Also provided is an LED device which ensures stronger adhesion between a silicone resin and a wiring lead and thus achieves favorable light emitting properties, and a manufacturing method for such LED device. Also provided is an LED device that can present superior luminous efficiency by the provision of a sufficient reflectivity even when emitting relatively short wavelength light, and a manufacturing method for such LED device. Also provided is a film carrier tape with which a superior Sn plating coat is formed, mechanical strength and connectivity are achieved. Also provided is a manufacturing method for such film carrier tape that can avoid damage to the wiring pattern layer during an Sn plating step while maintaining favorable manufacturing efficiency.

Abstract: A cavity semiconductor package has a pre-molded leadframe construction. The leadframe is formed by molding around a die pad, and plural terminal lands. The leadframe has a hole for an acoustic port, such that the package can be soldered on a back side of a printed circuit board and have air access to a sensor die in the package from a front side of the printed circuit board via the acoustic port. The leadframe may also have a hollow or concave recess that defines an acoustic cavity in conjunction with the sensor die or printed circuit board.

Abstract: A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias.

Abstract: A leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts protruding from a bottom surface of the encapsulation compound.

Abstract: A semiconductor apparatus including a semiconductor substrate having a first principal surface on which an electric circuit is formed and a second principal surface opposed to the first principal surface, and a through hole that penetrates the first principal surface and the second principal surface, a multilayered wiring layer having a plurality of conductive wiring layers connected to the electric circuit and a plurality of inter-layer insulating layers having an insulating layer opening of a same size and at a same position as a through hole opening which is an opening of the first principal surface of the through hole, an electrode pad that covers the insulating layer opening connected to the conductive wiring layer and a lead-out wiring layer having a through wiring layer connected to the electrode pad formed inside the through hole and a connection wiring layer formed integral with the through wiring layer.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a device to the substrate; providing interconnects on the substrate; and forming a flexible tape substantially conformal to the device and contacting the interconnects.

Abstract: A through-silicon via structure includes a substrate with a first side and a second side, a through-silicon hole connecting the first side and the second side and filled with a conductive material, a passivation layer disposed on and contacting the first side and covering the through-silicon hole, and a protection ring surrounding but not contacting the through-silicon hole and exposed by the first side and the second side. The protection ring is filled with an insulating material.

Abstract: An integrated circuit assembly comprises an integrated circuit die, and a routable metal layer comprising metal traces linking a plurality of wire bond pads to a plurality of external connection pads such that the metal traces are routable under the die area. An electrically nonconductive adhesive layer couples the integrated circuit die to the routable metal layer, and a plurality of wire bonds link circuitry on the integrated circuit die to the wire bond pads in the routable metal layer. An overfill material encapsulates at least the integrated circuit die and the plurality of wire bonds, and a plurality of solder balls are formed on the plurality of external connection pads.

Abstract: A method of fabricating a semiconductor package. In one embodiment the method includes forming a mold cavity about a portion of a first major surface of a leadframe, including about a mold lock opening extending through the leadframe between the first major surface and a second major surface. A spacer is inserted to fill at least a portion of the mold lock opening. The mold cavity is filled with an encapsulating material including filling a portion of the mold lock opening not occupied by the spacer.

Abstract: A process for forming semiconductor packages comprises partially etching a leadframe matrix, encapsulating it with mold compound, placing a semiconductor die in a leadframe unit and singulating the leadframe matrix. A system for forming semiconductor packages comprises means for partially etching a leadframe matrix, means for encapsulating it with mold compound, means for placing a semiconductor die in a leadframe unit and means for singulating the leadframe matrix.

Abstract: A method for manufacturing a semiconductor device package including an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface at the first package face and a second contact surface at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pad on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled using a lead frame having pre-formed leads, with or without taping, or using partially etched lead frames. A stack of the semiconductor device packages may be formed.

Abstract: A semiconductor device includes: a flat plate; a semiconductor chip which is disposed on one main surface of the flat plate and whose surface opposite an element circuit surface is fixedly bonded; a single layer of an insulating material layer formed continuously on the element circuit surface of the semiconductor chip and on the main surface of the flat plate; an opening formed at a position, in the insulating material layer, above an electrode disposed on the element circuit surface of the semiconductor chip; a conductive part formed in the opening so as to be connected to the electrode of the semiconductor chip; a wiring layer formed on the insulating material layer so as to be connected to the conductive part, and partly led out to a peripheral area of the semiconductor chip; and external electrodes formed on the wiring layer.

Abstract: Methods of bonding a structure fabricated in polydimethylsiloxane (PDMS) and an integrated circuit chip. The procedures for bonding include providing a substrate, affixing the integrated circuit to the substrate, as needed preparing the surface of the integrated circuit chip to permit bonding, aligning the PDMS structure and the features of the integrated circuit chip, and applying a bonding agent. The bonding agent is cured by exposure to a thermal regime for a suitable length of time. Depending on relative sizes, in some cases, a plural number of PDMS structures can be attached to one chip, or a single PDMS structure can be bonded to multiple chips. In some cases, the integrated circuit chip operates wirelessly. In other situations, the substrate provides electrical communication from the integrated circuit chip to electronic components.

Abstract: A semiconductor device includes an electronic component having a pad surface on which an electrode pad is formed, and having a back surface opposite the pad surface, a sealing resin disposed to cover side faces of the electronic component while exposing the pad surface at a first surface thereof and the back surface at a second surface thereof, a multilayer interconnection structure including insulating layers stacked one over another and interconnection patterns, having an upper surface thereof being in contact with the first surface, the electrode pad, and the pad surface, and having a periphery thereof situated outside a periphery of the sealing resin, and another pad disposed on the upper surface of the multilayer interconnection structure outside the periphery of the sealing resin, wherein the interconnection patterns include a first interconnection pattern directly connected to the electrode pad and a second interconnection pattern directly connected to said another pad.

Abstract: An apparatus having a three-dimensional integrated circuit structure is described herein. The apparatus include an interposer for carrying a plurality of high and low-power chips. The high-power chips are attached and connected to one side of the interposer, while the low-power chips are attached and connected to the other side of the interposer. In generally, the high-power chips produce more heat than does the low-power chip during their operations. The interposer further include through silicon vias and redistribution layers for connecting the chips on both surfaces. In addition, the interposer assembly is attached and connected to a substrate layer, which is in turn attached and connected to a printed circuit board. In order to provide improve thermal management, the interposer surface carrying the high-power chips are oriented away from the circuit board. A heat spreader is attached to the back sides of the high-power chips for dissipating the heat.

Abstract: Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a method for forming a microsystem and one or more passive devices in the microsystem. Layers of epoxy are sequentially deposited over a substrate to form multiple planarized layers of epoxy over the substrate. The epoxy layers are deposited by spin coating. At least some of the epoxy layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. An integrated circuit having multiple I/O bond pads is placed on an associated epoxy layer. At least one conductive interconnect layer is formed over an associated epoxy layer. A passive component is formed within at least one of the epoxy layers. The passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers. Multiple external package contacts are formed.

Abstract: A heat spreader for an LED can include a thermally conductive and optically transparent member. The bottom side of the heat spreader can be configured to attach to a light emitting side of the LED. The top and/or bottom surface of the heat spreader can have a phosphor layer formed thereon. The heat spreader can be configured to conduct heat from the LED to a package. The heat spreader can be configured to conduct heat from the phosphors to the package. By facilitating the removal of heat from the LED and phosphors, more current can be used to drive the LED. The use of more current facilitates the construction of a brighter LED, which can be used in applications such as flashlights, displays, and general illumination. By facilitating the removal of heat from the phosphors, desired colors can be better provided.

Abstract: A method of assembling an IC device package is provided. A leadframe is formed. At least one IC die is attached to a die attach pad portion of the leadframe. Wire bonds are coupled between the IC die and the leadframe. A cap is attached to the leadframe. A second surface of the cap includes a cavity formed therein. The cap and leadframe form an enclosure structure that substantially encloses the at least one IC die. An encapsulating material is applied to encapsulate at least the IC die. A perimeter support ring portion of the leadframe is trimmed.

Abstract: Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes a grounding element disposed adjacent to a periphery of a substrate unit and at least partially extending between an upper surface and a lower surface of the substrate unit. The grounding element includes an indented portion that is disposed adjacent to a lateral surface of the substrate unit. The semiconductor device package also includes an EMI shield that is electrically connected to the grounding element and is inwardly recessed adjacent to the indented portion of the grounding element.

Abstract: A processor/cache assembly has a processor die coupled to a cache die. The processor die has a plurality of processor units arranged in an array. There is a plurality of processor sets of contact pads on the processor units, one processor set for each processor unit. Similarly, the cache die has a plurality of cache units arranged in an array. There is a plurality of cache sets of contact pads on the cache die, one cache set for each cache unit. Each cache set is in contact with one corresponding processor set.

Abstract: Provided are a semiconductor package which is small in size but includes a large number of terminals disposed at intervals equal to or greater than a minimum pitch, and a method of fabricating the semiconductor package. The semiconductor package includes a semiconductor chip having a bottom surface on which a plurality of bumps are formed, redistribution layer patterns formed under the semiconductor chip and each including a first part electrically connected to at least one of the bumps and a second part electrically connected to the first part, an encapsulation layer surrounding at least a top surface of the semiconductor chip, and a patterned insulating layer formed below the redistribution layer patterns and exposing at least parts of the second parts of the redistribution layer patterns.

Abstract: A method for manufacturing a semiconductor package system includes: providing a die having a plurality of contact pads; forming a leadframe having a plurality of lead fingers with flat tops of predetermined lengths, the plurality of lead fingers having a fine pitch and each having a trapezoidal cross-section; attaching a plurality of bumps to the plurality of lead fingers, the plurality of bumps on the tops, extending beyond the widths of the trapezoidal cross-sections, and clamping down on the two sides of each of the plurality of lead fingers; attaching a plurality of bond wires to the plurality of contact pads; attaching the plurality of bond wires to the plurality of bumps; and forming an encapsulant over the plurality of lead fingers, the die, and the plurality of bond wires, the encapsulant leaving lower surfaces of the plurality of lead fingers exposed.

Abstract: A first multilayer wiring structure has a first surface and a second surface positioned on an opposite side to the first surface, a first wiring pattern formed on the second surface side and a housing portion penetrating through the first multilayer wiring structure from the first surface to the second surface. An electronic component has an electrode pad. The electronic component is accommodated in the housing portion in a state that an electrode pad formation surface at the side where the electrode pad is formed is positioned on the second surface side of the first multilayer wiring structure. A second multilayer wiring structure has an insulating layer and a second wiring pattern which are stacked on the second surface of the first multilayer wiring structure and the electrode pad formation surface of the electronic component. The second wiring pattern is electrically connected to the first wiring pattern and the electrode pad.

Abstract: A semiconductor component includes a plastic housing including: plastic outer surfaces; lower outer contact surfaces arranged on an underside of the housing; upper outer contact surfaces arranged on a top side of the housing that is opposite the underside; and outer interconnects electrically connecting the lower outer contact surfaces to the upper outer contact surfaces, the outer interconnects including a layer of solder arranged on conduction paths along an outer contour of the housing.

Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.

Abstract: A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly.

Abstract: The reliability of a semiconductor device is prevented from being reduced. A planar shape of a sealing body is comprised of a quadrangle having a pair of first sides, and a pair of second sides crossing with the first sides. Further, it has a die pad, a controller chip (first semiconductor chip) and a sensor chip (second semiconductor chip) mounted over the die pad, and a plurality of leads arranged along the first sides of the sealing body. The controller chip and the leads are electrically coupled to each other via wires (first wires), and the sensor chip and the controller chip are electrically coupled to each other via wires (second wires). Herein, the die pad is supported by a plurality of suspending leads formed integrally with the die pad and extending from the die pad toward the first sides of the sealing body. Each of the suspending leads has an offset part.

Abstract: A semiconductor chip package is disclosed comprising a semiconductor chip, a lead frame comprising at least one lead, and an encapsulating layer at least partially encapsulating the semiconductor chip and the lead frame. The lead comprises a first portion defining a lead frame pad at least partially exposed at an exterior surface of the package and a second portion extending from the first portion towards the semiconductor chip electrically connecting a surface portion of the semiconductor chip to the lead frame pad. The first portion has a first thickness and the second portion comprises a thinned portion, the thinned portion having a thickness smaller than the first thickness. The lead further comprises a bent portion, and wherein the thinned portion comprises at least part of the bent portion.

Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.

Abstract: Microelectronic package elements and packages having dielectric layers and methods of fabricating such elements packages are disclosed. The elements and packages may advantageously be used in microelectronic assemblies having high routing density.

Abstract: In a structure of a semiconductor device, a Si chip and a metal leadframe are jointed by metallic bond via a porous joint layer made of high conductive metal, having a three-dimensional network structure and using Ag as a bonding material, and a film containing Zn oxide or Al oxide is formed on a surface of a semiconductor assembly contacting to a polymer resin. In this manner, by the joint with the joint layer having the porous structure mainly made of Ag, thermal stress load of the Si chip can be reduced, and fatigue life of the joint layer itself can be improved. Besides, since adhesion of the polymer resin to the film can be enhanced by the anchor effect, occurrence of cracks in a bonding portion can be prevented, so that a highly-reliable Pb-free semiconductor device can be provided.

Abstract: A semiconductor component having wetable leadframe lead surfaces and a method of manufacture. A leadframe having leadframe leads is embedded in a mold compound. A portion of at least one leadframe lead is exposed and an electrically conductive material is formed on the exposed portion. The mold compound is separated to form singulated semiconductor components.

Abstract: A method of manufacturing a wafer level package can include: forming an indentation, by etching one side of a semiconductor chip, on one side of which a chip pad is formed; forming a rewiring pattern, which is electrically connected with the chip pad and which includes a post pad having a corrugated shape in correspondence with the indentation, by selectively adding a conductive material on one side of the semiconductor chip; forming a sacrificial layer on one side of the semiconductor chip such that a window is formed in the sacrificial layer that completely or partially uncovers the post pad; forming a conductive post on the post pad, by filling the window with a conductive material; and removing the sacrificial layer. This method can be used to produce a wafer level package having a post structure that provides greater strength against lateral shear stresses.

Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a substrate on the adhesive including aligning the post with an aperture in the substrate, then flowing the adhesive into and upward in a gap located in the aperture between the post and the substrate, solidifying the adhesive, then etching the post to form a cavity in the post, then mounting a semiconductor device on the post, wherein a heat spreader includes the post and the base and the semiconductor device extends into the cavity, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.

Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post into an opening in the adhesive, mounting a substrate on the adhesive including aligning the post with an aperture in the substrate, then flowing the adhesive into and upward in a gap located in the aperture between the post and the substrate, solidifying the adhesive, then etching the post and the base to form a cavity that extends through the adhesive into the base, then mounting a semiconductor device on the base, wherein a heat spreader includes the base and the semiconductor device extends into the cavity, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.

Abstract: A semiconductor package with wedge bonded chip. One embodiment provides a semiconductor chip, a wire bond and a metal element. The chip includes a bond pad with a copper layer. The wire bond is wedge bonded to the bond pad and ball bonded to the metal element.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: A semiconductor device, includes a lead frame including a die pad of which back side surface is exposed to the back side of a package, as well as a plurality of land terminals, a resin filled between the die pad and each of the land terminals so as to enable the die pad and each of the land terminals to be fastened mutually, and a semiconductor chip having a plurality of pads and being mounted on a top side of the die pad. The semiconductor device further includes an interposer having a bonding stitch on its top side, being disposed on the top side surface of the lead frame, and relaying an electrical connection of at least any one of the plurality of pads to at least any one of the land terminals, and a first bonding wire bonded to the bonding stitch of the interposer and one of the plurality of pads of the semiconductor chip.

Abstract: A system and method in which a semiconductor chip has electrically inactive metal-filled vias adjacent to a semiconductor device or devices to be cooled and the semiconductor device or devices are preferably surrounded by thermally insulating vias. The metal-filled vias are contacted with a thermoelectric cooler to remove excess heat from the semiconductor device or devices.

Abstract: A leadless semiconductor package with an electroplated layer embedded in an encapsulant and its manufacturing processes are disclosed. The package primarily includes a half-etched leadframe, a chip, an encapsulant, and an electroplated layer. The half-etched leadframe has a plurality of leads and a plurality of outer pads integrally connected to the leads. The encapsulant encapsulates the chip and the leads and has a plurality of cavities reaching to the outer pads to form an electroplated layer on the outer pads and embedded in the cavities. Accordingly, under the advantages of lower cost and higher thermal dissipation, the conventional substrates and their solder masks for BGA (Ball Grid Array) or LGA (Land Grid Array) packages can be replaced. The leads encapsulated in the encapsulant have a better bonding strength and the electroplated layer embedded in the encapsulant will not be damaged during shipping, handling, or storing the semiconductor packages.

Abstract: A semiconductor device includes a plurality of wiring lines which are provided on an upper side of a semiconductor substrate and which have connection pad portions, and columnar electrodes are provided on the connection pad portions of the wiring lines. A first sealing film is provided around the columnar electrodes on the upper side of the semiconductor substrate and on the wiring lines. A second sealing film is provided on the first sealing film. The first sealing film is made of a resin in which fillers are not mixed, and the second sealing film is made of a material in which fillers are mixed in a resin.

Abstract: Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. A microelectronic die can be carried by the support member and electrically coupled to the first packaged bond sites. A leadframe can be attached to the leadframe bond sites so as to extend adjacent to the microelectronic die, with the die positioned between the leadframe and the support member. The leadframe can include second package bond sites facing away from the first package bond sites. An encapsulant can at least partially surround the leadframe and the microelectronic die, with the first and second package bond sites accessible from outside the encapsulant.

Abstract: Provided is a light emitting device package. The light emitting device package comprises a housing, first and second lead frames, and a light emitting device. The housing comprises a front opening and side openings. The first and second lead frames pass through the housing to extend to an outside. A portion of each lead frame being exposed through the front opening. The light emitting device is in the front opening and electrically connected to the first and second lead frames. A protrusion protruding in a direction of the side opening is formed on an inner surface of the side opening.

Abstract: A method is disclosed which includes forming a layer of conductive material above a substrate, forming a masking layer above the layer of conductive material, performing a first etching process on the layer of conductive material with the masking layer in place, removing the masking layer and, after removing the masking layer, performing an isotropic etching process on the layer of conductive material to thereby define a plurality of piercing bond structures positioned on the substrate.

Abstract: In sophisticated semiconductor devices, a chip-package interconnect structure may be established on the basis of a metal pillar without using a solder bump material in the package. In this case, the complexity of the manufacturing process for forming the wiring system of the package may be significantly reduced, while also providing the possibility of increasing packing density of the pillar structure.

Abstract: A method of making a semiconductor chip assembly includes providing a thermal post, a signal post and a base, mounting an adhesive on the base including inserting the thermal post into a first opening in the adhesive and the signal post into a second opening in the adhesive, mounting a conductive layer on the adhesive including aligning the thermal post with a first aperture in the conductive layer and the signal post with a second aperture in the conductive layer, then flowing the adhesive into and upward in a first gap located in the first aperture between the thermal post and the conductive layer and in a second gap located in the second aperture between the signal post and the conductive layer, solidifying the adhesive, then providing a conductive trace that includes a pad, a terminal, the signal post and a selected portion of the conductive layer, mounting a semiconductor device on a heat spreader that includes the thermal post and the base, electrically connecting the semiconductor device to the conduct

Abstract: A method of manufacturing a semiconductor device includes a bonding step of bonding a chip on a wiring board by means of a bonding layer, and a wire bonding step of bonding a wire to a pad on the chip while applying ultrasonic vibration after the bonding step. A material having an elastic modulus of 100 MPa or higher at a process temperature in the wire bonding step is used as the bonding layer.

Abstract: A device and/or method relating to semiconductor technology. A semiconductor chip package may include dual line type input/output (I/O) pads. A semiconductor chip package may include a core area. A semiconductor chip package may include input/output (I/O) pads arranged on and/or over an outside of a core area, which may signal input/output to and/or from a core area. A semiconductor chip package may have input/output (I/O) pads including dual lines.