Abstract: A first wiring pattern is formed on a surface of a first support plate; a semiconductor chip is disposed on the first wiring pattern; and electrode terminals of the semiconductor chip are electrically connected to the first wiring pattern at required positions. Post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by a second support plate are collectively fixed and electrically connected to the first wiring pattern formed on the first support plate at predetermined positions. After sealing with resin, the first and second support plates are separated; a glass substrate is affixed on a front face side; and external electrodes connected to the second wiring pattern are formed on a back face side.

Abstract: The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.

Abstract: To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film.

Abstract: An electronic component capable of withstanding stress from a printed-circuit board or the like is provided. In an electronic component, a cavity hermetically sealed by a base and a lid is formed. In the cavity, a crystal resonator is supported by a supporting member over the top surface of the base. The base is made of glass. A stress buffer layer made of a conductive resin or the like is formed over the whole bottom surface of the base. An external electrode and an external electrode that are in continuity with the electrodes of the crystal resonator individually extend to the bottom surface of the stress buffer layer via the side surfaces of the base and stress buffer layer. The thus configured electronic component is surface-mounted by, for example, soldering the external electrode and external electrode formed on the bottom surface of the stress buffer layer to a printed-circuit board.

Abstract: The present invention relates to a wire bonding structure, and more particularly to a manufacturing method for said wire bonding structure. The wire bonding structure comprises a die that connects with a lead via a bonding wire. At least one bond pad is positioned on an active surface of the die, and a gold bump is provided on the bond pad; furthermore, a ball bond can be positioned upon the gold bump. The bond pad and the gold bump can separate the ball bond and the die, which can avoid damaging the die during the bonding process.

Abstract: A quad flat package (QDP) structure having an exposed heat sink is provided. The QDP structure includes a leadframe, a chip, a heat sink, an insulating layer and a molding compound. The leadframe includes a die pad and multiple leads surrounding the die pad. The chip is disposed on the die pad and electrically connected to the die pad and the leads. The heat sink has a top surface, a bottom surface opposite thereto, and a side surface connected to the top and the bottom surfaces. The die pad is disposed in a central area of the top surface of the heat sink and electrically connected to the heat sink. The molding compound encapsulates the chip, the die pad, an inner lead portion of each lead and heat sink, and exposes the bottom surface of the heat sink and an outer lead portion of each lead.

Abstract: A fabricating process of a thermal enhanced substrate is provided for fabricating thermal conduction blocks to increase the heat dissipation area. A metallic substrate having a first surface and a second surface opposite to the first surface is provided. A first shallow trench with a first depth is then formed on the first surface. A second shallow trench with a second depth is formed on the second surface, and a deep trench penetrating the first shallow trench and the second shallow trench is formed, where the metallic substrate is separated into many thermal conduction blocks by the deep trench. At least one metallic layer and at least one insulating material are laminated on the thermal conduction blocks, and the insulating material is filled into the deep trench and covers the thermal conduction blocks.

Abstract: A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks.

Abstract: A bonding plate forms high-performance, low-resistance interconnections between integrated circuit die and an electronic package lead frame. The bonding plate is made from copper, aluminum, or metalized silicon and is processed using standard semiconductor fabrication techniques to apply solder bumps and, optionally, copper pillars. The bonding plates are singulated from a wafer and applied to the die package using standard pick-and-place and solder reflow equipment and processes. This achieves high performance interconnect at low cost without the need for specialized tooling.

Abstract: A semiconductor component has a substrate and a projecting electrode on the substrate. The projecting electrode is configured suitably for electrically and mechanically connecting the semiconductor component to an external substrate. Furthermore, the projecting electrode is formed by a one-dimensional or two-dimensional array of projecting sub-electrodes, which are separated from each other by an electrically insulating fluid beginning from a substrate surface. The semiconductor component has an improved projecting-electrode. It provides the projecting electrode with a sub-structure, which achieves sufficient flexibility without introducing much constructive complexity and processing complexity during fabrication.

Abstract: A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting the first metallic bond part and the second metallic bond part.

Abstract: A semiconductor chip package is disclosed. One embodiment provides at least one semiconductor chip including contact elements on a first surface of the chip. An encapsulation layer covers the semiconductor chip. A metallization layer is applied above the first surface of the chip and the encapsulation layer. The metallization layer includes contact areas connected with the contact elements of the chip. External pins are connected with the contact areas.

Abstract: A method of manufacturing a semiconductor package that includes: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs.

Abstract: An integrated circuit package system and method of manufacture therefor includes providing a substrate with a beveled cavity, attaching a down-set conductive die pad with tapered sidewalls for matching with the beveled cavity in the substrate and having the down-set below a lower surface of the substrate, and attaching an integrated circuit over the down-set conductive die pad and electrically connected thereto.

Abstract: A method for making a quad flat non-lead (QFN) semiconductor package includes half etching a first side of a carrier to form top portions of a lead array and a die attach surface of a die attach pad, wherein the lead array includes at least one inner terminal lead disposed adjacent to the die attach pad, at least one extended, outer terminal lead disposed along periphery of the QFN semiconductor package, and at least one intermediary terminal disposed between the inner terminal lead and the extended, outer terminal lead, wherein the intermediary terminal is disposed between the inner terminal lead and the extended, outer terminal lead.

Abstract: A chip stack package includes a substrate, a plurality of chips, a plurality of adhesive layers and a plug. The substrate has a wiring pattern and a seed layer formed on the wiring pattern. Each of the chips has an electrode pad and a first through-hole that penetrates the electrode pad. The chips are stacked such that the first through-holes are aligned on the seed layer of the substrate. The adhesive layers are interposed between the substrate and one of the chips, as well as between the chips. Each of the adhesive layers has a second through-hole connected to the first through-hole. The plug fills up the first through-holes and the second through-holes and electrically connects the electrode pads to the wiring pattern of the substrate. A cross-sectional area of the plug in the second through-holes may be larger than that of the plug in the first through-holes.

Abstract: A ball grid array (BGA) package having a half-etched bonding pad and a cut plating line and a method of fabricating the same. In the BGA package, the plating line is cut to form a predetermined uneven bonding pad using half-etching, thereby increasing the contact area between the bonding pad and a solder ball. The BGA package includes a first external layer having a first circuit pattern and a wire bonding pad pattern wherein a chip is connected to a wire bonding pad using wire bonding. A second external layer includes a second circuit pattern, a cut plating line pattern, and a half-etched uneven solder ball pad pattern. In the second external layer, another chip is mounted on a solder ball pad. An insulating layer having a through hole interposed between the first and second external layers and electrically connects the first and second external layers therethrough.

Abstract: After a plurality of pads (2) are formed on an insulation film (1), a passivation film (3) is formed on the entire surface thereof, and opening parts (3a) which exposes all the pads (2) are formed in the passivation film (3). Next, another passivation film is formed on the entire surface and, for each of the pads (2), an opening part is formed in this passivation film to expose the central portion of the pad (2). According to the above method, the probing test can be performed with the opening parts (3a) formed in the passivation film (3). Performing the probing test in such a state increases the probability that the probe contacts the pad (2) since the entire surface of the pad (2) is exposed, thereby providing the test with a higher accuracy. Thus, the pad can be miniaturized and/or the pitch can be narrowed without requiring a higher accuracy of the probe.

Abstract: A simplified manufacturing process and the resultant bifacial solar cell (BSC) are provided, the simplified manufacturing process reducing manufacturing costs. The BSC includes a back surface contact grid and an overlaid blanket metal reflector. A doped amorphous silicon layer is interposed between the contact grid and the blanket layer.

Abstract: A semiconductor device 100 includes a semiconductor substrate 14, a connection electrode 12 disposed on an upper surface of the semiconductor substrate 14 and connected to an integrated circuit thereon, a through electrode 20 which penetrates the semiconductor substrate 14 and the connection electrode 20, and an insulation portion 30 interposed between the semiconductor substrate 14 and the through electrode 20. The through electrode 20 is integrally formed to protrude outward from upper surfaces of the semiconductor substrate 14 and the connection electrode 12, and connected to the connection electrode 12 in a region where the through electrode 20 penetrates the connection electrode 12.

Abstract: A method of manufacturing a plurality of stacked die semiconductor packages, including: placing a phase change material between a top surface of a substrate and a bottom surface of a first die; placing a phase change material between a top surface of the first die and a bottom surface of a second die; wherein the first and second dies have a plurality of conductive protrusions on the bottom surfaces of the dies; wherein the first die has a plurality of conductive vias extending from its conductive protrusions, through the first die, to the top surface of the first die; wherein the conductive vias of said first die are in alignment with the conductive protrusions of the second die; and heating the dies and the substrate to cause the second die to become electrically interconnected to the first die and the first die to become electrically connected to the substrate.

Abstract: A leadframe includes a die paddle and leads, in which the back side of the die paddle has a fillister. The fillister defines a rim surrounding a recess, and the recess accommodates protrusion of fusible material. Also, a package includes such a leadframe. Also, a method for making a leadframe includes patterning a sheet of metal to form a die paddle and leads, and forming a fillister in the back side of the die paddle.

Abstract: An electronic package and method and system for forming the electronic package. The electronic package has a first substrate including a first electronic device and including through-holes extending through an entire thickness of the first substrate. The electronic package has a second substrate bonded to the first substrate, metallizations formed in the through-holes of the first substrate to connect to components of the first electronic device, and a patternable substance disposed between the first substrate and the second substrate and adhering the first substrate and the second substrate together in regions apart from the metallizations.

Abstract: A circuit device includes an insulating base provided with a resin layer mixed with a fibrous filler, bumps provided in the insulating base and functioning as electrodes for connection, a semiconductor device that is flip-chip mounted, and an underfill filling a gap between the semiconductor device and the insulating base. By allowing the fibrous filler projecting through the top surface of the resin layer to be in contact with the underfill, strength of adhesion between the underfill and the insulating base is improved.

Abstract: A method for manufacturing an integrated circuit package system includes: providing a frame; attaching a leaded package having leads adjacent the frame wherein the leads extend towards a side opposite the frame; and applying a package encapsulant over the leaded package having the leads partially exposed opposite the frame.

Abstract: A wafer-level packaging process of a light-emitting diode is provided. First, a semiconductor stacked layer is formed on a growth substrate. A plurality of barrier patterns and a plurality of reflective layers are then formed on the semiconductor stacked layer, wherein each reflective layer is surrounded by one of the barrier patterns. A first bonding layer is then formed on the semiconductor stacked layer to cover the barrier patterns and the reflective layers. Thereafter, a carrying substrate having a plurality of second bonding layers and a plurality of conductive plugs electrically insulated from each other is provided, and the first bonding layer is bonded with the second bonding layer. The semiconductor stacked layer is then separated from the growth substrate. Next, the semiconductor stacked layer is patterned to form a plurality of semiconductor stacked patterns. Next, each semiconductor stacked pattern is electrically connected to the conductive plug.

Abstract: Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.

Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.

Abstract: The manufacturing method of advanced quad flat non-leaded packages includes performing a pre-cutting process prior to the backside etching process for defining the contact terminals. The pre-cutting process ensures the isolation of individual contact terminals and improves the package reliability.

Abstract: While an adhesive layer is provided over the rear surface of a semiconductor chip in die bonding, a lamination processing (main pressure bonding) is necessary for securing the adhesive state of the adhesive layer after the die bonding process (temporary pressure bonding). In this case, typically the hardening of the adhesive is developed by applying heat while pressing down the rear surface of the chip from above with a pressurization member. It has become clear that various problems exist in the lamination processing of the laminate chips by such a mechanical pressurization method as the chip becomes thinner. That is, the problems include chip damage at a part in an overhang state, a chip position shift caused by bending and non-uniform pressurization, and the like.

Abstract: The advanced quad flat non-leaded package structure includes a carrier, a chip, a plurality of wires, and a molding compound. The carrier includes a die pad and a plurality of leads. The inner leads of the leads electively have a plurality of locking grooves for enhancing the adhesion between the inner leads and the surrounding molding compound.

Abstract: To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.

Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.

Abstract: A semiconductor device has a sealing body formed of an insulating resin and a semiconductor chip positioned within the sealing body. A gate electrode and a source electrode are on a first main surface of the semiconductor chip and a back electrode (drain electrode) is on a second main surface thereof. An upper surface of a portion of a drain electrode plate that projects in a gull wing shape is exposed from the sealing body and a lower surface thereof is connected to the back electrode through an adhesive. A gate electrode plate projects in a gull wing shape on an opposite end side of the sealing body and is connected to the gate electrode within the sealing body. A source electrode plate projects in a gull wing shape on the opposite end side of the sealing body and is connected to the source electrode within the sealing body.

Abstract: An electronic device can include an interconnect level (16) including a bonding pad region (110). An insulating layer (18) can overlie the interconnect level (16) and include an opening (112, 24) over the bonding pad region (110). In one embodiment, a conductive stud (34) can lie within the opening (112, 24) and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer (22) lying along a side and a bottom of the opening (112, 24) and a conductive stud (34) lying within the opening (112, 24). The conductive stud (34) can substantially fill the opening (112, 24). A majority of the conductive stud (34) can lie within the opening (112, 24). In still another embodiment, a process for forming an electronic device can include forming a conductive stud (34) within the opening (112, 24) wherein the conductive stud (34) lies substantially completely within the opening (112, 24).

Abstract: A semiconductor device includes: a semiconductor element that has a first surface on which an electrode terminal is formed and a second surface opposite to the first surface; a resin mold portion in which the semiconductor element is embedded and that has a third surface exposing the first surface and a fourth surface opposite to the third surface; and a wiring layer formed on the third surface and the first surface, wherein a plurality of conducting portions are provided in the resin mold portion, which penetrate the resin mold portion along a thickness direction thereof to be electrically connected to the wiring layer.

Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.

Abstract: Provided are: a circuit device demonstrating an improved connection reliability while being mounted; and a method for manufacturing the same. The circuit device of the present invention includes: an island; leads arranged around the island, each lead having a lower surface and a side surface exposed to the outside; and a semiconductor element mounted on the island and electrically connected to the leads through thin metal wires. Furthermore, the exposed end portion of the lead is formed to spread toward the outside. By forming the lead in this manner, the area where the lead comes into contact with a brazing filler material is increased, thus improving the connection strength therebetween.

Abstract: A semiconductor device has a first conductive layer formed over a substrate. A first insulating layer is formed over the first conductive layer. A second conductive layer is formed over first insulating layer and first conductive layer. A third insulating layer is formed over the second insulating layer and second conductive layer. An under bump metallization layer (UBM) is formed over the third insulating layer and second conductive layer. A UBM build-up structure is formed over the UBM. The UBM build-up structure has a sloped sidewall and is confined within a footprint of the UBM. The UBM build-up structure extends above the UBM to a height of 2-20 micrometers. The UBM build-up structure is formed in sections occupying less than an area of the UBM. A solder bump is formed over the UBM and UBM build-up structure. The sections of the UBM build-up structure provide exits for flux vapor escape.

Abstract: An electronic component including at least one chip and/or one support, the chip configured to be transferred onto the support and linked, at a level of at least one connection site of the chip, formed by at least one portion of a layer of the chip, to at least one connection site of the support formed by at least one portion of a layer of the support, by at least one ball, the chip and/or the support including a mechanism for mechanical decoupling of the connection site of the chip and/or of the support with respect to the chip and/or to the support, which mechanism includes at least one cavity made in the layer of the chip and/or of the support, under the connection site of the chip and/or of the support, and at least one trench, made in the layer of the chip and/or of the support, communicating with the cavity.

Abstract: Provided are: a lead frame enabling efficient manufacturing of multiple circuit devices; and a method for manufacturing a circuit device using the same. In the lead frame of the present invention, units are arranged and frame-shaped first and second supporters are provided around the units to mechanically support the units. Moreover, a half groove is provided in the first supporter at a portion on an extended line of a dividing line defined at a boundary between each adjacent two of the units. Furthermore, a penetration groove penetrating a part of the second supporter at a portion on an extended line of another dividing line is provided.

Abstract: To improve the heat dissipation characteristics of a semiconductor device. The semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and a plurality of leads so as to surround the die pad, a plurality of members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate, wherein a semiconductor chip the outer shape of which is larger than the die pad is mounted over the die pad and the members. The top surface of the die pad and the top surface of the members at the part in opposition to the back surface of the semiconductor chip are bonded to the back surface of the semiconductor chip in their entire surfaces with a silver paste.

Abstract: A method of handling a thin wafer includes forming a support structure at the edge of a thinned wafer that is encapsulated by a protection layer. The support structure can be an adhesive layer enclosing the protection layer, a dielectric-filled trench embedded in the thinned wafer and surrounding the protection layer, or a housing affixing the edge of the thinned wafer.

Abstract: In a method for making a semiconductor module, a bump electrode and a recess are formed by etching a copper sheet. An insulating resin layer is formed, in the recess, up to a position lower than the height of the bump electrode, and then a semiconductor device and the copper sheet, including a wiring layer formed integrally with the bump electrode, are press-bonded together. The wiring layer is warped to protrude toward the semiconductor device, which assures the electrical connection between the bump electrodes and device electrodes.

Abstract: A method for manufacturing an integrated circuit package system includes: forming a first device unit, having first external interconnects arranged along a perimeter of the first device unit, and a second device unit, having second external interconnects arranged along a perimeter of the second device unit, in an array configuration; mounting an integrated circuit die over the first device unit; connecting the integrated circuit die and the first external interconnects; encapsulating with an encapsulation covering the integrated circuit die, the first device unit, and the second device unit with both the first external interconnects and the second external interconnects partially exposed; and forming a partial encapsulation cut in the encapsulation electrically isolating the first external interconnects and the second electrical interconnects.

Abstract: A layout structure and layout method are provided. The layout structure includes a first conductive via, a second conductive via, a die and eight pads. The first conductive via and the second conductive via pass through the die. The first conductive via has a first pad and a second pad, and the second conductive via has a third pad and a fourth pad. A fifth pad is conducted to the third pad. A sixth pad is conducted to the second pad. A seventh pad is conducted to the first pad. An eighth pad is conducted to the fourth pad. In a vertical direction of the die, the first pad and the second pad are overlapped, the third pad and the fourth pad are overlapped, the fifth pad and the sixth pad are overlapped, and the eighth pad and the seventh pad are overlapped, partially or totally.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting a device over an integrated circuit having a through via; attaching an interposer, having an opening, and the integrated circuit with the device within the opening; and forming an encapsulation at least partially covering the integrated circuit and the interposer facing the integrated circuit.

Abstract: A semiconductor device has a first layer pressing portion that is formed by crushing a ball neck formed by bonding an initial ball onto a first layer pad of a first layer semiconductor die and pressing the side of a wire folded onto the crushed ball neck, a first wire extended in the direction of a lead from the first layer pressing portion, and a second wire that is looped from a second layer pad of a second layer semiconductor die toward the first layer pressing portion and joined onto the second layer pad side of the first layer pressing portion. Thereby, the connection of wires is performed at a small number of times of bonding, while reducing damages caused on the semiconductor dies.

Abstract: Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader.

Abstract: An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias.