Abstract: At least a first capacitor is formed on a substrate and connected to a first differential node of a differential circuit, and the first capacitor may be variable in capacitance. A second capacitor is formed on the substrate and connected to a second differential node of the differential circuit, and the second capacitor also may be variable. A third capacitor is connected between the first differential node and the second differential node, and is formed at least partially above the first capacitor. In this way, a size of the first capacitor and/or the second capacitor may be reduced on the substrate, and capacitances of the first and/or second capacitor(s) may be adjusted in response to a variable characteristic of one or more circuit components of the differential circuit.

Abstract: A device using an inductor with one or more through vias, and a method of manufacture is provided. In an embodiment, an inductor is formed in one or more of the metallization layers. One or more through vias are positioned directly below the inductor. The through vias may extend through one or more dielectric layers interposed between a substrate and the inductors. Additionally, the through vias may extend completely or partially through the substrate.

Abstract: A semiconductor device and method of manufacturing a semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate and forming a dielectric layer over the substrate. The method further includes forming a first trench within the dielectric layer, wherein the first trench extends through the dielectric layer and epitaxially (epi) growing a first active layer within the first trench and selectively curing with a radiation energy the dielectric layer adjacent to the first active layer.

Abstract: Method of forming a semiconductor device includes providing a substrate with defined NMOS and PMOS device regions and an interface layer on the NMOS and PMOS device regions, depositing a high-k film on the interface layer, depositing a first cap layer on the high-k film, and removing the first cap layer from the high-k film in the PMOS device region. The method further includes depositing a second cap layer on the first cap layer in the NMOS device region and on the high-k film in the PMOS device region, performing a heat-treating process to diffuse a first chemical element into the high-k film in the NMOS device region and to reduce or eliminate the interface layer by oxygen diffusion from the interface layer into the second cap layer, removing the first and second cap layers from the high-k film, and depositing a gate electrode film over the high-k film.

Abstract: A layout configuration for a memory cell array includes at least a comb-like doped region having a first conductivity type and a fishbone-shaped doped region having a second conductivity type. The second conductivity type and the first conductivity type are complementary. Furthermore, the comb-like doped region and the fishbone-shaped doped region are interdigitated.

Abstract: A three-dimensional semiconductor device includes stacked structures arranged two-dimensionally on a substrate, a first interconnection layer including first interconnections and disposed on the stacked structures, and a second interconnection layer including second interconnections and disposed on the first interconnection layer. Each of the stacked structures has a lower region including a plurality of stacked lower word lines, and an upper region including a plurality of stacked upper word lines disposed on the stack of lower word lines. Each of the first interconnections is connected to one of the lower word lines and each of the second interconnections is connected to one of the upper word lines.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.

Abstract: A structure and method for replacement metal gate (RMG) field effect transistors is disclosed. Silicide regions are formed on a raised source-drain (RSD) structure. The silicide regions form a chemical mechanical polish (CMP) stopping layer during a CMP process used to expose the gates prior to replacement. Protective layers are then applied and etched in the formation of metal contacts.

Abstract: Disclosed is a silicon interposer that can reduce the entire area of a semiconductor package and increase the degree of integration by forming inductors at a lower part in addition to an upper part of a silicon substrate. The silicon interposer includes a silicon substrate, an upper inductor layer formed at the upper part of the silicon substrate and a lower inductor layer formed at the lower part of the silicon substrate.

Abstract: An embodiment of an electronic device includes first and second semiconductor bodies. The first semiconductor body houses a first conductive strip having a first end portion and a second end portion, and houses a first conduction terminal electrically coupled to the first end portion and facing a surface of the first semiconductor body. The second semiconductor body houses a second conductive strip having a third end portion and a fourth end portion, and houses a second conduction terminal electrically coupled to the third end portion and facing a surface of the second semiconductor body. The first and second semiconductor bodies are arranged relative to one another so that the respective surfaces face one another, and the first conduction terminal and the second conduction terminal are coupled to one another by means of a conductive element so as to form a loop of an inductor.

Abstract: A semiconductor device includes a semiconductor chip having a multilayer interconnect, a first spiral inductor and a second spiral inductor formed in the multilayer interconnect, and an interconnect substrate formed over the semiconductor chip and having a third spiral inductor and a fourth spiral inductor. The third spiral inductor overlaps the first spiral inductor in a plan view. The fourth spiral inductor overlaps the second spiral inductor in the plan view. The third spiral inductor and the fourth spiral inductor collectively include a line, the line being spirally wound in a same direction in the third spiral inductor and the fourth spiral inductor.

Abstract: An array of vertically constructed, electronic switches is disclosed having three, four or more contacts and having a common bottom contact and a plurality of common middle contacts. This switch array will find use in memory devices or display devices.

Abstract: A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening.

Abstract: A circuit structure includes a substrate having an array region and a peripheral region. The substrate in the array and peripheral regions includes insulator material over first semiconductor material, conductive material over the insulator material, and second semiconductor material over the conductive material. The array region includes vertical circuit devices which include the second semiconductor material. The peripheral region includes horizontal circuit devices which include the second semiconductor material. The horizontal circuit devices in the peripheral region individually have a floating body which includes the second semiconductor material. The conductive material in the peripheral region is under and electrically coupled to the second semiconductor material of the floating bodies. Conductive straps in the array region are under the vertical circuit devices.

Abstract: A power semiconductor device comprises: a high-voltage side switching element and a low-voltage side switching element which are totem-pole-connected in that order from a high-voltage side between a high-voltage side potential and a low-voltage side potential; a high-voltage side drive circuit that drives the high-voltage side switching element; a low-voltage side drive circuit that drives the low-voltage side switching element; a capacitor which has a first end connected to a connection point between the high-voltage side switching element and the low-voltage side switching element and a second end connected to a power supply terminal of the high-voltage side drive circuit and supplies a drive voltage to the high-voltage side drive circuit; and a diode which has an anode connected to a power supply and a cathode connected to the second end of the capacitor and supplies a current from the power supply to the second end of the capacitor, wherein the diode includes a P-type semiconductor substrate, an N-type ca

Abstract: The invention concerns a conducting layer having a thickness of between 1 and 5 atoms, an insulated gate being formed over a part of the conducting layer.

Abstract: Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

Abstract: A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.

Abstract: A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).

Abstract: A memory device includes an access device including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type. Both the first and the second doped semiconductor regions are formed in a single-crystalline semiconductor body, and define a p-n junction between them. The first and second doped semiconductor regions are implemented in isolated parallel ridges formed in the single-crystal semiconductor body. Each ridge is crenellated, and the crenellations define semiconductor islands; the first doped semiconductor region occupies a lower portion of the islands and an upper part of the ridge, and the second doped semiconductor region occupies an upper portion of the islands, so that the p-n junctions are defined within the islands.

Abstract: A three-dimensional semiconductor device includes a semiconductor substrate, a plurality of conductive layers and insulating layers, and a plurality of contacts. The plurality of conductive layers and insulating layers are stacked alternately above the semiconductor substrate. The plurality of contacts extend in a stacking direction of the plurality of conductive layers and insulating layers. The plurality of conductive layers form a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer. The plurality of contacts are connected respectively to each of steps of the stepped portion. The stepped portion is formed such that, at least from an uppermost conductive layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is.

Abstract: A semiconductor device is made by forming an oxide layer over a substrate and forming a first conductive layer over the oxide layer. The first conductive layer is connected to ground. A second conductive layer is formed over the first conductive layer as a plurality of segments. A third conductive layer is formed over the second conductive layer as a plurality of segments. If the conductive layers are electrically isolated, then a conductive via is formed through these layers. A first segment of the third conductive layer operates as a first passive circuit element. A second segment operates as a second passive circuit element. A third segment is connected to ground and operates as a shield disposed between the first and second segments. The shield has a height at least equal to a height of the passive circuit elements to block cross-talk between the passive circuit elements.

Abstract: There is provided a technique capable of reducing a layout area of a standard cell configuring a digital circuit even under a circumstance that a new layout rule introduced in accordance with microfabrication of a MISFET is provided. For example, a protruding wiring PL1A protrudes from a power supply wiring L1A at each corner of both ends of a standard cell CL toward an inside of the standard cell CL (in a Y direction), and a bent portion BD1A which is bent from the protruding wiring PL1A in an X direction is formed. And, this bent portion BD1A and a p-type semiconductor region PDR are connected to each other via a plug PLG.

Abstract: A semiconductor structure and a method of forming the same are provided in which the gate induced drain leakage is controlled by introducing a workfunction tuning species within selected portions of a pFET such that the gate/SD (source/drain) overlap area of the pFET is tailored towards flatband, yet not affecting the workfunction at the device channel region. The structure includes a semiconductor substrate having at least one patterned gate stack located within a pFET device region of the semiconductor substrate. The structure further includes extension regions located within the semiconductor substrate at a footprint of the at least one patterned gate stack. A channel region is also present and is located within the semiconductor substrate beneath the at least one patterned gate stack.

Abstract: A galvanic-isolated coupling of circuit portions is accomplished on the basis of a stacked chip configuration. The semiconductor chips thus can be fabricated on the basis of any appropriate process technology, thereby incorporating one or more coupling elements, such as primary or secondary coils of a micro transformer, wherein the final characteristics of the micro transformer are adjusted during the wafer bond process.

Abstract: A Ge and Si hybrid material accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a circular-shaped cross section and are formed of p-type Ge and n-type Si, respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. In an accumulation mode, current flows through the overall cylindrical channel, so as to achieve high carrier mobility, reduce low-frequency noises, prevent polysilicon gate depletion and short channel effects and increase the threshold voltage of the device.

Abstract: A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects.

Abstract: Some embodiments include cross-point memory structures. The structures may include a line of first electrode material extending along a first horizontal direction, a multi-sided container of access device materials over the first electrode material, a memory element material within the multi-sided container, and a line of second electrode material over the memory element material and extending along a second horizontal direction that is orthogonal to the first horizontal direction. Some embodiments include methods of forming memory arrays. The methods may include forming a memory cell stack over a first electrode material, and then patterning the first electrode material and the memory cell stack into a first set of spaced lines extending along a first horizontal direction. Spaced lines of second electrode material may be formed over the first set of spaced lines, and may extend along a second horizontal direction that is orthogonal to the first horizontal direction.

Abstract: A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.

Abstract: A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric element, a conductive line, and conductive islands. The stacked structure is formed on the substrate. The stacked structure includes conductive strips and insulating strips stacked alternately. The conductive strips are separated from each other by the insulating strips. The dielectric element is formed on the stacked structure. The conductive line is formed on the dielectric element. The conductive line is extended in a direction perpendicular to a direction which the stacked structure is extended in. The conductive islands are formed on the dielectric element. The conductive islands on the opposite sidewalls of the single stacked structure are separated from each other.

Abstract: A system for performing bonding of a first substrate including a first plurality of solder pads to a second substrate including a second plurality of solder pads comprises a first alignment mark set and a first plurality of dots on the first substrate. The system further comprises a second alignment mark set and a second plurality of dots on the second substrate. The second plurality of dots are configured to interlock and form an interlocking key with the first plurality of dots. The first alignment mark set is aligned with the second alignment mark set corresponding to the first and second plurality of dots being aligned and the first and second plurality of solder pads being aligned. The first and second plurality of dots are configured to remain substantially solid during a reflow of the first plurality of solder pads.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation different than the first crystallographic orientation. A first field effect device having a first gate electrode is located and formed within and upon the first active region and a second field effect device having a second gate electrode is located and formed within and upon the second active region. Upper surfaces of the first gate electrode and the second gate electrode are coplanar. The structure and method allow for avoidance of epitaxial defects generally encountered when using hybrid orientation technology substrates that include coplanar active regions.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array unit and an alignment mark unit. The cell array unit includes a first memory string, a second memory string and a device isolation insulating layer. The first string is provided on a major surface of a semiconductor layer. The second string is juxtaposed with the first memory string. The device isolation insulating layer partitions the first and second memory strings from each other. The mark unit juxtaposed with the array unit includes a mark unit semiconductor layer and a mark unit insulating layer. The mark unit semiconductor layer is a part of the semiconductor layer. The mark unit insulating layer is juxtaposed with the mark unit semiconductor layer. An upper surface of the mark unit semiconductor layer is included in a plane different from a plane including an upper surface of the mark unit insulating layer.

Abstract: Each of the first bit lines of a device has an upper surface and a lower surface, with the upper surface being more outwardly located over a semiconductor surface than the lower surface. A second bit line of the device has an upper surface and a lower surface, with the upper surface thereof being more outwardly located over the semiconductor surface than the lower surface. The upper surface of the second bit line is more outwardly located over the semiconductor surface than the upper surfaces of the first bit lines. The first bit lines are each adjacent to the second bit line and the second bit line is configured to be selectively coupled to a memory cell other than memory cells to which the first bit lines are configured to be selectively coupled. The second bit line does not overlap any of the first bit lines.

Abstract: [Problem to be Solved] A semiconductor element having fine pitch electrodes is mounted on a substrate at low cost without reducing the number of input-output terminals. [Solution] Electrodes 1 for electrical connection and first inductors 2, arranged between the electrodes 1 in a manner neighboring the electrodes 1, for electromagnetic coupling are arranged on one main surface of the semiconductor element 3. On a substrate 5, second inductors 4 for electromagnetically coupling with the first inductors 2 are arranged in positions corresponding to the first inductors 2. The semiconductor element 3 is mounted on the substrate 5 so that the first and second inductors 2 and 4 face each other. Only desired input/output signals among input/output signals of the semiconductor element 3 are inputted or outputted from the external electrodes 11 of the substrate 5 in a manner being transmitted contactlessly by electromagnetic coupling between the first and second inductors 2 and 4 without going through the electrodes 1.

Abstract: A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract: Disclosed is a method to construct a device that includes a plurality of nanowires (NWs) each having a core and at least one shell. The method includes providing a plurality of radially encoded NWs where each shell contains one of a plurality of different shell materials; and differentiating individual ones of the NWs from one another by selectively removing or not removing shell material within areas to be electrically coupled to individual ones of a plurality of mesowires (MWs). Also disclosed is a nanowire array that contains radially encoded NWs, and a computer program product useful in forming a nanowire array.

Abstract: A 3D memory device includes a plurality of ridge-shaped stacks, in the form of multiple strips of conductive material separated by insulating material, arranged as strings which can be coupled through decoding circuits to sense amplifiers. Diodes are connected to the bit line structures at either the string select of common source select ends of the strings. The strips of conductive material have side surfaces on the sides of the ridge-shaped stacks. A plurality of conductive lines arranged as word lines which can be coupled to row decoders, extends orthogonally over the plurality of ridge-shaped stacks. Memory elements lie in a multi-layer array of interface regions at cross-points between side surfaces of the conductive strips on the stacks and the conductive lines.

Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.

Abstract: A memory-array is disclosed in which an array of non-linear conductors such as diodes is constructed having an area per memory cell of 4F2 and comprises a plurality of conductors fabricated as doped semiconductor conducting lines in the substrate such that, during normal operation, an unselected conductor has a zero bias to the substrate and a selected conductor has a reverse bias to the substrate for minimizing current leakage

Abstract: A module substrate may include a substrate body on which a plurality of chip mounting regions having connection pads are defined. Repair structures may be respectively formed, or placed, in the chip mounting regions. Each repair structure includes conductive layer patterns formed over the connection pads in each chip mounting region, an insulation layer pattern formed over the substrate body in each chip mounting region in such a way as to expose the conductive layer patterns, plastic conductive members formed between the connection pads and the conductive layer patterns, and a plastic insulation member formed between the substrate body and the insulation layer pattern in each chip mounting region.

Abstract: A method for manufacturing a semiconductor device includes forming at least one stripe-shaped protection film over a multilayer film in a scribe region of a semiconductor substrate having a plurality of semiconductor element regions formed therein, the protection film having a thickness larger in a center portion thereof than at an end surface thereof and being made of a member which transmits a laser beam, and removing the multilayer film in the scribe region by irradiating the protection film with a laser beam.

Abstract: A semiconductor structure, such as a field effect device structure, and more particularly a CMOS structure, includes a gate dielectric that is at least in-part aligned to an active region of a semiconductor substrate over which is located the gate dielectric. The gate dielectric comprises other than a thermal processing product of the semiconductor substrate. In particular, the gate dielectric may be formed using an area selective deposition method such as but not limited to an area selective atomic layer deposition method. Within the context of a CMOS structure, the invention provides particular advantage insofar as the use of a self-aligned method for forming a gate dielectric aligned upon an active region of a semiconductor substrate may avoid a masking process that may otherwise be needed to strip portions of an area non-selective blanket gate dielectric.

Abstract: A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits.

Abstract: A semiconductor die includes a semiconductive substrate layer with first and second sides, a metal layer adjacent the second side of the semiconductive substrate layer, one or more active devices in an active layer on the first side of the semiconductive substrate layer; and a passive device in the metal layer in electrical communication with the active layer. The passive device can electrically couple to the active layer with through silicon vias (TSVs).

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. A semiconductor device comprises a first single-crystal semiconductor layer including a first channel formation region and a first impurity region over a substrate having an insulating surface, a first gate insulating layer over the first single-crystal semiconductor layer, a gate electrode over the first gate insulating layer, a first interlayer insulating layer over the first gate insulating layer, a second gate insulating layer over the gate electrode and the first interlayer insulating layer, and a second single-crystal semiconductor layer including a second channel formation region and a second impurity region over the second gate insulating layer. The first channel formation region, the gate electrode, and the second channel formation region are overlapped with each other.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Abstract: A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.