With Specific Source Of Supply Or Bias Voltage Patents (Class 327/530)
  • Patent number: 10163763
    Abstract: An integrated circuit package having a first die configured to sense a first physical characteristic and provide a first data signal, and a second die, wherein the first die is configured to transmit the first data signal to the second die, and the second die is configured to determine if there is an error in the first die and transmit the result to a controller.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: December 25, 2018
    Assignee: Infineon Technologies AG
    Inventors: Friedrich Rasbornig, Wolfgang Granig, Dirk Hammerschmidt, Hans-Joerg Wagner, Thomas Zettler
  • Patent number: 10157644
    Abstract: Methods of operating a voltage generation circuit, and apparatus configured to perform such methods, include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the voltage driver output to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of the voltage driver output is less than a threshold, connecting the voltage driver output to a second voltage node configured to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of the voltage driver output is greater than the threshold, and connecting the voltage driver output to a third voltage node configured to receive a third voltage less than the first voltage when the clock signal has a different logic level.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: December 18, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Agostino Macerola, Marco-Domenico Tiburzi, Stefano Perugini
  • Patent number: 10141925
    Abstract: A circuit for strengthening load transient response compensation is provided, including a comparator, a first MOSFET and a second MOSFET. The comparator compares a system voltage of an electronic device with a reference voltage. The first MOSFET is coupled to the comparator and a first power supply. The second MOSFET is coupled to the comparator and a second power supply of the electronic device. When an external device is connected to the electronic device such that the system voltage is lower than the reference voltage, the comparator outputs a low-level signal and the first MOSFET becomes conductive, so that the external device is powered by the first power supply.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: November 27, 2018
    Assignee: WISTRON CORP.
    Inventors: Chengwei Huang, Sin-Fang Wang, Yen-Hsiang Wang, Jiun-Lin Tseng, Po-Yen Huang
  • Patent number: 10056783
    Abstract: An energy harvesting circuit for use with a logic circuit includes an induction coil positioned near conductive elements of the logic circuit and configured to extract energy from the magnetic fields produced by transient currents associated with state changes within the logic circuit.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: August 21, 2018
    Assignee: Johnson Research & Development Co., Inc.
    Inventor: Lonnie G. Johnson
  • Patent number: 10050518
    Abstract: A power supply circuit may include a first power converter that may be configured to generate a first inner supply voltage having a first voltage level based on a first external supply voltage and to output the first inner supply voltage to a first node that is coupled to the first node, a second power converter that may be configured to generate a second inner supply voltage having the first voltage level based on a second external supply voltage and to output the second inner supply voltage to a second node that is coupled to the second node, a first diode that may include an anode coupled to the first node and a cathode coupled to the second node, and a second diode that may include an anode coupled to the second node and a cathode coupled to the first node.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 14, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyoung-Taek Lim, Chung-Hyun Ryu
  • Patent number: 10033355
    Abstract: A voltage adjustment circuit includes switches connected in parallel between a circuit unit and an electric power supply line to which a first electric power supply voltage is applied, and changes the number of switches turned off, based on a comparison result between a target value and a second electric power supply voltage supplied to the circuit unit, to adjust the second electric power supply voltage. A control circuit decides an interval for increasing the number of switches turned off when the circuit unit changes to standby state, based on a leak current value of the circuit unit in standby state, a time in which the second electric power supply voltage changes from a first to a second value, the first and second values, and an electric potential difference by which the second electric power supply voltage changes when one switch switches between on and off.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: July 24, 2018
    Assignee: SOCIONEXT INC.
    Inventor: Yosuke Tsukamoto
  • Patent number: 10031544
    Abstract: A power supply voltage detection circuit can detect the power supply voltage obtained by stabilizing a power supply voltage supplied from outside and also the magnitude of the power supply voltage before being stabilized. This power supply voltage detection circuit includes a selection circuit that selects one power supply potential from among a plurality of power supply potentials including a first power supply potential supplied from outside and a second power supply potential obtained by stabilizing the first power supply potential, a variable voltage dividing circuit that divides the voltage between the power supply potential selected by the selection circuit and a reference potential by a set division ratio, a comparison voltage generation circuit that generates a comparison voltage based on a reference voltage, and a comparator that compares the voltage divided by the variable voltage dividing circuit with the comparison voltage and outputs a signal representing a comparison result.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: July 24, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Sachiyuki Abe
  • Patent number: 10014762
    Abstract: The invention provides a protection circuit applied in an inductive boost converter, the inductive boost converter includes a transmission circuit and a charging circuit, the protection circuit includes a detection circuit and a control circuit, an input terminal of the detection and an output terminal of the transmission circuit are connected, a first output terminal of the detection circuit and an input terminal of the charging circuit are connected, a second output terminal of the detection circuit and an input terminal of the control terminal are connected; the detection circuit detects whether an input current from the transmission circuit is a short-circuit current, if the circuit is shorted, the result will be sent to the control circuit, the control circuit cuts the connection of the charging circuit and ground, which can prevent charges stored in the charging circuit from flowing backward into the input terminal of the inductive boost converter.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: July 3, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Xianming Zhang, Dan Cao
  • Patent number: 10008614
    Abstract: A dual channel transistor includes a first gate electrode, a second gate electrode, a first gate insulation layer, a second gate insulation layer, a silicon semiconductor channel layer, and an oxide semiconductor channel layer. The first gate insulation layer is disposed on the first gate electrode. The silicon semiconductor channel layer is disposed on the first gate insulation layer. The oxide semiconductor channel layer is disposed on the silicon semiconductor channel layer. The second gate insulation layer is disposed on the oxide semiconductor channel layer. The second gate electrode is disposed on the second gate insulation layer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wanxun He, Su Xing
  • Patent number: 9946276
    Abstract: A voltage regulator provides an output current at an output voltage, based on an input voltage. The voltage regulator has a pass transistor for deriving the output current. The voltage regulator contains a drive transistor forming a current mirror in conjunction with the pass transistor, such that the output current through the pass transistor is dependent on a drive current through the drive transistor. The voltage regulator comprises an auxiliary transistor arranged such that at least a fraction of the drive current through the drive transistor flows through the auxiliary transistor. The voltage regulator has amplification circuitry to set the drive current through the drive transistor depending on the output voltage and on a reference voltage. The voltage regulator further contains control circuitry to detect an indication for a dropout situation where a difference between the input voltage and the output voltage falls below a dropout voltage.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: April 17, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventors: Ambreesh Bhattad, Frank Kronmueller, Hande Kurnaz
  • Patent number: 9933800
    Abstract: A linear voltage regulator and associated integrated circuit and method are disclosed. The linear voltage regulator is operable within a plurality of predefined operational modes, and comprises a pass element configured to generate an output voltage based on a received input voltage. The linear voltage regulator further comprises an error amplifier comprising an output node coupled with a control node of the pass element. The error amplifier is configured to generate a control signal at the output node based on the output voltage and a reference voltage. The linear voltage regulator further comprises a frequency compensation circuit configured to selectively apply an impedance to the output node based on which of the predefined operational modes is selected.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 3, 2018
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Aswani Tadinada, Sivan Kumar Pandian, Kaushalendra Tripathi, Srinivasaraju Dhenuvakonda
  • Patent number: 9933286
    Abstract: A sensor comprises a sensor element configured to provide a sensor signal representing at least one measurand detected by the sensor element, an electrical circuit configured to process the sensor signal to form a data signal, a photovoltaic cell configured to provide electrical energy for the sensor element and the electrical circuit, and a housing, in which the sensor element, the electrical circuit and the photovoltaic cell are positioned, the housing including a recess in which the photovoltaic cell is positioned, and a rim surrounding the recess and protruding beyond the photovoltaic cell. A method is also provided.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: April 3, 2018
    Assignee: Robert Bosch GmbH
    Inventors: Ricardo Ehrenpfordt, Mathias Bruendel, Frederik Ante, Johannes Kenntner
  • Patent number: 9929644
    Abstract: An internal voltage trimming device and a semiconductor integrated circuit including the same are provided. The internal voltage trimming device includes a voltage dividing circuit configured to generate a feedback voltage based on a resistance of the voltage dividing circuit and a target voltage that is received in a trimming mode, and a comparator configured to compare a reference voltage and the feedback voltage to generate a comparison signal. The internal voltage trimming device further includes a direct current to direct current (DC-DC) converter configured to generate an internal voltage based on an input voltage and the comparison signal, and be disabled in the trimming mode, and an automatic trimming circuit configured to generate, in the trimming mode, a trimming signal based on the comparison signal. The voltage dividing circuit is further configured to adjust the resistance based on the trimming signal.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: March 27, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-sung Kim, Se-eun Oh, Jun-young Park, Hyeon-seong Im
  • Patent number: 9904647
    Abstract: A system may include date flow module circuits configured between electronic devices or circuits that may affect and/or intercept the flow of data being communicated between electronic devices. The data flow module circuits may communicate with an external controller that may want to intervene in the data communication. The data flow module circuits may be configured in a pass mode or in an intervention mode. In the pass mode, a data flow module circuit may pass on data it receives without intervention by the external controller. In the intervention mode, the data flow module circuit may receive instructions from the external controller as to the data that the external controller wants the data flow module to output.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: February 27, 2018
    Assignee: SanDisk Technologies LLC
    Inventor: Sharon Mutchnik
  • Patent number: 9858986
    Abstract: An integrated circuit containing a SRAM memory with SRAM bits optimized to have a lower minimum read voltage than the minimum write voltage. A method for reading a SRAM memory bit using a read voltage that is lower than the write voltage.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: January 2, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Theodore W. Houston, Srinivasa Raghavan Sridhara
  • Patent number: 9857811
    Abstract: A programmable power discharge circuit and a method of discharging power are provided. The programmable power discharge circuit includes a programmable voltage controller, a detect circuit, and a discharge circuit. The programmable voltage controller selects and provides a threshold voltage by a voltage divider including a plurality of impedance components. The detect circuit detects a difference between the threshold voltage and a working voltage to decide whether the working voltage is discharged.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: January 2, 2018
    Assignee: National Chiao Tung University
    Inventors: Ming-Dou Ker, Wan-Hsueh Cheng
  • Patent number: 9837901
    Abstract: A system includes an inductor having first and second terminals. First and second transistors have first terminals connected to the first and second terminals of the inductor, respectively, and second terminals connected to a power supply and a common potential, respectively. Third and fourth transistors have first terminals connected to the first and second terminals of the inductor, respectively, and second terminals providing first and second output voltages of first and second polarities, respectively. First and second feedback circuits generate first and second feedback signals based on the first and second output voltages, respectively. A first control circuit controls the first and third transistors based on the second feedback signal and not based on the first feedback signal. A second control circuit controls the second and fourth transistors based on the first feedback signal and not based on the second feedback signal.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: December 5, 2017
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Karl Volk
  • Patent number: 9831868
    Abstract: A drive signal generator includes a drive signal generator that generates a drive signal for driving a capacitive load. In the drive signal generator, a set of a first MOSFET and a second MOSFET which are electrically connected in series between a wire of a high potential and a wire of a low potential is arranged in plurality in series. A part or all of the first MOSFETs and the second MOSFETs in the plurality of sets have different sizes from each other.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: November 28, 2017
    Assignee: Seiko Epson Corporation
    Inventors: Shuji Otsuka, Tadashi Kiyuna, Toshifumi Asanuma
  • Patent number: 9829911
    Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: November 28, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Kosuke Yayama, Takashi Nakamura
  • Patent number: 9819260
    Abstract: Disclosed is a charge pump protection device including a power supply voltage, a charge pump to produce an output voltage higher than the power supply voltage, the charge pump including, a pumping capacitor to store voltage during a charging state and to discharge the voltage during a pumping state thereof, a plurality of switches to regulate the charging and pumping states, a charge pump capacitor to store the output voltage, and at least one current limiter in series with at least one of the plurality of switches to limit current and prevent an electrical failure of the charge pump.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: November 14, 2017
    Assignee: NXP B.V.
    Inventors: Derk Jan Hissink, Jacobus Govert Sneep, Fred Mostert, Hendrikus van Iersel
  • Patent number: 9805681
    Abstract: A gate line driver circuit for a display panel includes a pull up circuit to drive a gate line of a display panel to a positive voltage that causes display panel switch elements that are coupled to the gate line to transition into an on state, a first pull down transistor to drive the gate line to a first negative voltage that causes the coupled display panel switch elements to transition into an off state, and a second pull down transistor to maintain the gate line at a second negative voltage that is less negative than the first negative voltage so as to maintain the coupled display panel switch elements in the off state. Other embodiments are also described and claimed.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: October 31, 2017
    Assignee: APPLE INC.
    Inventor: James E. C. Brown
  • Patent number: 9793795
    Abstract: A charge pump circuit that utilizes a sensing circuit for determining the current loading or status of the output supply generated by the charge pump circuit to determine a corresponding frequency for a variable rate clock for the charge pump circuit. When a current load is present, the clock frequency automatically ramps up to a relatively high level to increase the output current of the charge pump circuit. When the current load is removed and the supply is settled out, the clock frequency is automatically reduced to a relatively quieter level and the charge pump circuitry operates at a lower power level. Accordingly, the charge pump circuit is only noisy when it has to be, thus providing optimal power when required and being electrically quiet and operating at lower power at all other times.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: October 17, 2017
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 9767870
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include core circuitry having an array of memory cells and a row decoder that accesses each of the memory cells via a selected wordline and a wordline signal. The core circuitry may operate at a first supply voltage. The integrated circuit may include periphery circuitry having a column decoder that accesses each of the memory cells via a selected bitline. The periphery circuitry may operate at a second supply voltage that is different than the first supply voltage. The periphery circuitry may include voltage differential sensing circuitry that may compare the first supply voltage to the second supply voltage, sense a voltage differential between the first and second supply voltages, and delay the wordline signal when the voltage differential is greater than a threshold voltage.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: September 19, 2017
    Assignee: ARM Limited
    Inventors: Rajiv Kumar Roy, Kanika Malik, Manoj Puthan Purayil, Vikash
  • Patent number: 9715204
    Abstract: A discharge circuit unit for minimizing standby power occurring in a standby mode and an image forming apparatus having the same are provided. The discharge circuit unit is connected to an input line of alternating current (AC) power and discharges a capacitive element for reducing noises. The discharge circuit unit includes a discharge circuit including first and second resistance units connected in series to discharge the capacitive element in response to a discharge control signal generated when an input of the AC power is interrupted, and a detection circuit that detects whether the input of the AC power is interrupted, and includes third and fourth resistance units connected in series so as to generate the discharge control signal when it is detected that the input of the AC power is interrupted. Each of the first to fourth resistance units includes at least one of a resistor and a switch.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: July 25, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Jin Ha Kim
  • Patent number: 9692406
    Abstract: A power device drive circuit reduces the short-circuit resistance of a power device that switches an input voltage. The power device drive circuit includes an output amplifier that applies a control voltage to a control terminal of the power device so as to be turned on and off, and an internal power supply circuit that generates a drive voltage of the output amplifier in accordance with a change in the input voltage, thereby causing the control voltage to change. In particular, the internal power supply circuit reduces the drive voltage of the output amplifier when the input voltage rises, thereby reducing the short-circuit current of the power device.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: June 27, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hidetomo Ohashi
  • Patent number: 9672902
    Abstract: In some embodiments, a system includes a bit-cell circuit and a body voltage control circuit. During a sleep mode, the bit-cell circuit receives, via a source node of a transistor, a retention voltage. During an active mode, the bit-cell receives, via the source node, an operating voltage. The body voltage control circuit includes a first transistor that connects a body node of the transistor of the bit-cell circuit to the source node such that during the sleep mode, the body node receives the retention voltage. The body voltage control circuit further includes a second transistor that connects the body node to a voltage source such that during the active mode, the body node receives the operating voltage.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: June 6, 2017
    Assignee: Apple Inc.
    Inventors: Yildiz Sinangil, Mohamed H. Abu-Rahma, Jaroslav Raszka
  • Patent number: 9673803
    Abstract: A load driving device 10 includes a temperature detector TD1 that sets a temperature difference detection signal dt_ot to active when a temperature difference Tdif between a temperature Ttr of an output transistor T1 and an ambient temperature becomes more than a reference temperature difference Tdref1, and sets an over temperature detection signal at_ot to active when the temperature Ttr of the output transistor T1 becomes higher than a reference temperature Tref1, a current limiter IL1 that limits a GS current of the output transistor T1 when any one of the detection signals becomes active, and the output transistor T1 that turns off regardless of an external input signal IN when any one of the detection signals becomes active.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 6, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Uemura, Akihiro Nakahara
  • Patent number: 9660635
    Abstract: A power device drive circuit reduces the short-circuit resistance of a power device that switches an input voltage. The power device drive circuit includes an output amplifier that applies a control voltage to a control terminal of the power device so as to be turned on and off, and an internal power supply circuit that generates a drive voltage of the output amplifier in accordance with a change in the input voltage, thereby causing the control voltage to change. In particular, the internal power supply circuit reduces the drive voltage of the output amplifier when the input voltage rises, thereby reducing the short-circuit current of the power device.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: May 23, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hidetomo Ohashi
  • Patent number: 9647209
    Abstract: Various methods and devices that involve phase change material (PCM) switches are disclosed. An exemplary integrated circuit comprises an active layer with a plurality of field effect transistor (FET) channels for a plurality of FETs. The integrated circuit also comprises an interconnect layer comprising a plurality of conductive interconnects. The plurality of conductive interconnects couple the plurality of field effect transistors. The integrated circuit also comprises an insulator layer covering at least a portion of the interconnect layer. The integrated circuit also comprises a channel of a radio-frequency (RF) PCM switch. The channel of the RF PCM switch is formed on the insulator layer.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: May 9, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Sinan Goktepeli, Michael A. Stuber
  • Patent number: 9633743
    Abstract: A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: April 25, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jangwoo Lee, Kyoungtae Kang, Taesung Lee, Jeongdon Ihm
  • Patent number: 9608631
    Abstract: A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: March 28, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki Won Lee, Seung Jun Bae, Joon Young Park, Yong Cheol Bae
  • Patent number: 9595951
    Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate and a body. A compensation network including a gate-coupling circuit couples the gates of each pair of neighboring FETs. The compensation network may further including a body-coupling circuit that couples the bodies of each pair of neighboring FETs.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: March 14, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Steven Christopher Sprinkle, Fikret Altunkilic, Haki Cebi
  • Patent number: 9588154
    Abstract: A method for operating a microcomputer apparatus includes provisioning an electrical reference voltage that is independent of an electrical supply voltage, continuously comparing a defined level of the electrical reference voltage with the electrical supply voltage, and performing a defined operation with the microcomputer apparatus for at least one defined ratio between the defined level of the electrical reference voltage and the electrical supply voltage. The provisioning and the continuous comparing involves using a functional module of the microcomputer apparatus.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: March 7, 2017
    Assignee: Robert Bosch GmbH
    Inventors: Daniel Rombach, Kamil Pogorzelski, Jacek Wiszniewski, Marcus Prantner
  • Patent number: 9559699
    Abstract: A method and apparatus for reducing global interconnect delay on a field programmable gate array (FPGA) on an integrated circuit die comprising coding with a digital to analog coder on the integrated circuit die successive groups of n digital bits into an 2n level voltage or current signal where n is an integer greater than or equal to 2; transmitting the voltage or current signal on a global interconnect on the integrated circuit die; receiving on the integrated circuit die the signal transmitted on the global interconnect; and decoding the received signal on the integrated circuit die to reconstitute the successive groups of digital bits.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: January 31, 2017
    Assignee: Altera Corporation
    Inventors: Weimin Zhang, Yanzhong Xu
  • Patent number: 9484912
    Abstract: A resistance element generator includes a reference current generation unit suitable for receiving a source reference current to generate first and second reference currents, a first resistance generation unit suitable for generating a first resistance value by using a first reference voltage and the first reference current, and outputting a first voltage corresponding to the formed first resistance value, and a second resistance generation unit suitable for generating a second resistance value by using a third reference voltage and the second reference current, and outputting a second voltage corresponding to the formed second resistance value.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: November 1, 2016
    Assignee: SK Hynix Inc.
    Inventor: Sung-Jin Lee
  • Patent number: 9429964
    Abstract: A voltage regulator includes a programming interface via which programming instructions may be applied to a processor of the voltage regulator. The voltage regulator operates the processor according to the programming instructions to select one of multiple active internally-generated analog voltage levels to determine an output voltage level of the voltage regulator.
    Type: Grant
    Filed: June 20, 2014
    Date of Patent: August 30, 2016
    Assignee: TAMIRAS PER PTE. LTD., LLC
    Inventor: David G. Wright
  • Patent number: 9392171
    Abstract: A motion sensor includes a sensor element that outputs a sense signal in response to a motion applied thereto and a sensor circuit that senses the motion based on the sense signal. The sensor circuit includes a sensor-element-signal amplifier that receives the sense signal. The sensor-element-signal amplifier operates switchably between at a normal mode and at a low-noise mode that consumes a larger electric power and produces a smaller noise than the normal mode. This motion sensor senses a small motion and a large motion accurately.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: July 12, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takeshi Uemura, Hideyuki Murakami, Shinjiro Ueda, Ryota Sudo
  • Patent number: 9379693
    Abstract: A self bias buffer circuit includes a buffer and bias controller. The buffer provides a self bias voltage based on a reference voltage and to be driven based on the self bias voltage. The buffer also generates an output signal based on a comparison of an input signal and the reference voltage. The bias controller adjusts the self bias voltage based on the reference voltage.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: June 28, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hye-Seung Yu, Jun-Bae Kim
  • Patent number: 9354654
    Abstract: A multi-stage device for boosting an input voltage is discussed. Each stage of the device comprises a stage of a ring oscillator and a charge pump. An oscillating signal, generated by the ring oscillator within the device, drives the charge pump in each stage of the device. The charge pumps of the stages are serially connected. A final stage of the multi-stage device is adapted to provide voltage to a load circuit. The multi-stage device is applicable for generation of different bias voltages from one or more source voltages.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: May 31, 2016
    Assignee: Peregrine Semiconductor Corporation
    Inventor: James W. Swonger
  • Patent number: 9337826
    Abstract: To reduce power consumption, a semiconductor device includes a power source circuit for generating a power source potential, and a power supply control switch for controlling supply of the power source potential from the power source circuit to a back gate of a transistor, and the power supply control switch includes a control transistor for controlling conduction between the power source circuit and the back gate of the transistor by being turned on or off in accordance with a pulse signal that is input into a control terminal of the control transistor. The power source potential is intermittently supplied from the power source circuit to the back gate of the transistor, using the power supply control switch.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: May 10, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Shunpei Yamazaki
  • Patent number: 9312004
    Abstract: A driver for a semiconductor memory may reduce an error in writing data in memory cells by adjusting the height and width of a spike current, when the memory cells in which data having the same level are written are arranged at different distances. In addition, the driver may reduce the error by controlling the amount of charges supplied to each of the memory cells that are arranged at different distances.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: April 12, 2016
    Assignees: SK HYNIX INC., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Gyu Hyeong Cho, Suk Hwan Choi
  • Patent number: 9310869
    Abstract: A memory storage device, a memory control circuit unit and a power supply method are provided. The power supply method includes: providing a first power voltage to a host interface circuit of the memory storage device; providing a second power voltage to a memory management circuit of the memory storage device; providing a third power voltage to a memory interface circuit of the memory storage device, wherein a reference voltage terminal of the memory interface circuit is coupled to a power input terminal of the memory management circuit. Thus, the overheat problem of the memory storage device due to the voltage conversion may be improved.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: April 12, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chih-Jen Hsu, Hsiang-Hsiung Yu, Ta-Chuan Wei, Yun-Chieh Chen
  • Patent number: 9306571
    Abstract: A device includes a first level shifter, a switch, and a control circuit. The first level shifter is electrically connected to a pad. The switch has an input terminal electrically connected to an input terminal of the first level shifter, and an output terminal electrically connected to an output terminal of the first level shifter. The control circuit is electrically connected to a control terminal of the switch.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lei Pan, Qingchao Meng
  • Patent number: 9225175
    Abstract: A power voltage selection device includes a first power voltage and a second power voltage; a power selection unit having a first PMOS transistor and a second PMOS transistor, wherein the first power voltage is supplied to a source of the first PMOS transistor, a gate of the first PMOS transistor receives a first enable signal, the second power voltage is supplied to a source of the second PMOS transistor, a gate of the second PMOS transistor receives a second enable signal, and a body of the first PMOS transistor is coupled to a body of the second PMOS transistor; an output unit having a common node to which a drain of the first PMOS transistor and a drain of the second PMOS transistor are commonly coupled; and a body voltage control unit controlling to supply one of the first power voltage and the second power voltage to the bodies of the first PMOS transistor and the second PMOS transistor, wherein the one has a higher voltage level than the other.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: December 29, 2015
    Assignee: SK Hynix Inc.
    Inventor: Tae-Hoon Kim
  • Patent number: 9184666
    Abstract: A system and method include a controller that reduces power dissipated by a switch, such as a source-controlled field effect transistor, when an estimated amount of power dissipated by the switch exceeds a predetermined threshold. Reducing the power dissipated by the switch prevents damage to the switch due to overheating. The controller determines the estimated amount of power dissipated by the switch using actual drain-to-source current and drain voltage data. In at least one embodiment, the controller includes a fail-safe, estimated power dissipation determination path that activates when the drain voltage data fails a reliability test. Additionally, in at least one embodiment, the controller includes a model of thermal characteristics of the switch. In at least one embodiment, the controller utilizes real-time estimated power dissipation by the switch and the model to determine when the estimated power dissipated by the switch exceeds a power dissipation protection threshold.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 10, 2015
    Inventors: Mohit Sood, Spencer Isaacson, Rahul Singh, Zhaohui He
  • Patent number: 9160232
    Abstract: A power conversion circuit uses smaller, cheaper, and faster analog and digital circuits, e.g., buffers, comparators, and processing circuits, to provide the information necessary to control a multilevel power converter faster, cheaper, and with a smaller footprint than conventional techniques. For example, a current detection circuit indirectly measures a direction of a current through an inductor connected between midpoint node and an output node of a multilevel power converter based on comparisons between voltages associated with the multilevel power converter. A capacitor voltage detection detects a capacitor voltage across the flying capacitor to generate a logic signal based on a comparison between the capacitor voltage and a first reference voltage.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: October 13, 2015
    Assignee: ST-ERICSSON SA
    Inventors: Matthieu Thomas, Patrik Arno, Vladimir Molata, Ondrej Tlaskal
  • Patent number: 9148718
    Abstract: Circuits, methods, and apparatus for grounding contacts in an audio jack. One example may provide a driver, such as a charge pump, driving a first depletion mode transistor coupled between a first contact in an audio jack and ground, and a second depletion mode transistor coupled between a second contact in the audio jack and ground. The first depletion mode transistor and second depletion mode transistor may be p-channel transistors or n-channel transistors.
    Type: Grant
    Filed: June 10, 2012
    Date of Patent: September 29, 2015
    Assignee: Apple Inc.
    Inventors: David C. Breece, III, Cara S. Yang, Nathan Johanningsmeier, Kavitha Srinivasan
  • Patent number: 9143133
    Abstract: An output driver for driving a pad includes a pull-up circuit and a pull-down circuit. The pull-up circuit includes first, second and third first-type transistors. The first and second first-type transistors are commonly controlled by a first logic signal. The third first-type transistor is connected in parallel to the second first-type transistor. The pull-down circuit includes first, second and third second-type transistors. The first and second second-type transistors are commonly controlled by a second logic signal. The third second-type transistor is connected in parallel to the second second-type transistor. The pull-up circuit is configured such that a response speed of the first first-type transistor to the first logic signal is lower than that of the second first-type transistor to the first logic signal.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: September 22, 2015
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventors: Hsian-Feng Liu, Chun-Chia Chen, Hsin-Kuang Chen, Yao-Zhong Zhang
  • Patent number: 9124086
    Abstract: Among other things, one or more techniques and/or systems for providing failsafe electrostatic discharge (ESD) protection are provided. In one embodiment, ESD protection is provided by connecting a voltage fail safe (VFS) supply voltage to an NWELL circuit interface (e.g., of a PMOS transistor) and connecting PAD to at least one of VFS or the NWELL circuit interface. To this end, circuitry to be protected from ESD (e.g., circuitry operably connected to PAD) is provided with failsafe ESD protection (e.g., such that a non-snapback NMOS device may be utilized to discharge ESD current, where a non-snapback NMOS generally consumes less semiconductor real estate and is less complex to produce as compared to a snapback NMOS), for example. In this manner, failsafe ESD protection is efficiently provided.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: September 1, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei Yu Ma, Kuo-Ji Chen
  • Patent number: 9124272
    Abstract: An output MOS transistor has a drain connected with a power supply and a source connected with an output terminal. The short-circuit MOS transistor has a source connected with the output terminal. The short-circuit MOS transistor is formed in a semiconductor substrate connected with the power supply. A switching device is formed in a semiconductor region which is formed in the semiconductor substrate, and contains a first diffusion layer connected with the gate of the output MOS transistor and a second diffusion layer formed in the semiconductor region and connected with the drain of the short-circuit MOS transistor.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: September 1, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Ikuo Fukami