Abstract: A bandgap reference circuit includes a voltage generation circuit, a capacitor and a clamping control circuit. The voltage generation circuit is used to generate a current on an operation terminal. The capacitor includes a first terminal coupled to the operation terminal, and a second terminal coupled to a first reference voltage terminal. The clamping control circuit is coupled between the operation terminal and a second reference voltage terminal. The clamping control circuit includes a switch and a clamping unit, and is used to allow part of the current flowing through the clamping unit to the second reference voltage terminal when the switch is turned on.

Abstract: A processor system includes first and second regulators for regulating an adjusted supply voltage. The first and second regulators generate a plurality of control signals to regulate an adjusted power supply voltage and that generate a charge when a droop level falls below a droop threshold value by implementing first and second control loops. A supply adjustment block with the two regulators and control loops are provided for each processor core allowing different cores to have different regulated supply levels all based on one common supply. One regulator is a global regulator while another is a local regulator found in each of the processing tiles. Processing tiles are grouped into two groups wherein one group includes tiles that may powered down to save power. Voltage rails of the two groups are selectively connected to equalize voltage levels when both groups are powered on and operating.

Abstract: An acoustic energy detection circuit can include a microphone interface circuit configured for coupling to a microphone. The microphone interface circuit is configured to intermittently activate the microphone to detect acoustic energy and convert the acoustic energy to an electrical signal. The acoustic energy detection circuit also includes a comparator circuit for receiving the electrical signal and comparing the electrical signal with a threshold signal. The comparator circuit is configured to output an output signal to indicate detection of acoustic energy.

Abstract: A system for interfacing an LC sensor includes a starter configured to selectively start an oscillation of the LC sensor. The system also includes an analog peak detector configured to determine a signal (Vpeak) being indicative of a peak voltage of the oscillation of the LC sensor and a detector configured to determine a state of the LC sensor as a function of the signal (Vpeak) determined by the analog peak detector.

Abstract: Methods for fabricating an integrated circuit with a voltage regulator are provided. In some implementations, a method includes forming a primary regulator on a semiconductor substrate, including fabricating a switch, fabricating an amplifier for controlling the switch, and fabricating a voltage generator for biasing the amplifier to operate the primary regulator in a bypass mode or in a regulating mode. The method further includes forming an input terminal and an output terminal of the primary regulator on the semiconductor substrate, forming a secondary regulator on the substrate, forming an input terminal and an output terminal of the secondary regulator on the semiconductor substrate, and forming an electrical connection between the output terminal of the primary regulator and the input terminal of the secondary regulator.

Abstract: An integrated circuit package having a first die configured to sense a first physical characteristic and provide a first data signal, and a second die, wherein the first die is configured to transmit the first data signal to the second die, and the second die is configured to determine if there is an error in the first die and transmit the result to a controller.

Abstract: Methods of operating a voltage generation circuit, and apparatus configured to perform such methods, include applying a clock signal to an input of a voltage driver of a stage of the voltage generation circuit, connecting the voltage driver output to a first voltage node configured to receive a first voltage when the clock signal has a particular logic level and a voltage level of the voltage driver output is less than a threshold, connecting the voltage driver output to a second voltage node configured to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of the voltage driver output is greater than the threshold, and connecting the voltage driver output to a third voltage node configured to receive a third voltage less than the first voltage when the clock signal has a different logic level.

Abstract: A circuit for strengthening load transient response compensation is provided, including a comparator, a first MOSFET and a second MOSFET. The comparator compares a system voltage of an electronic device with a reference voltage. The first MOSFET is coupled to the comparator and a first power supply. The second MOSFET is coupled to the comparator and a second power supply of the electronic device. When an external device is connected to the electronic device such that the system voltage is lower than the reference voltage, the comparator outputs a low-level signal and the first MOSFET becomes conductive, so that the external device is powered by the first power supply.

Abstract: An energy harvesting circuit for use with a logic circuit includes an induction coil positioned near conductive elements of the logic circuit and configured to extract energy from the magnetic fields produced by transient currents associated with state changes within the logic circuit.

Abstract: A power supply circuit may include a first power converter that may be configured to generate a first inner supply voltage having a first voltage level based on a first external supply voltage and to output the first inner supply voltage to a first node that is coupled to the first node, a second power converter that may be configured to generate a second inner supply voltage having the first voltage level based on a second external supply voltage and to output the second inner supply voltage to a second node that is coupled to the second node, a first diode that may include an anode coupled to the first node and a cathode coupled to the second node, and a second diode that may include an anode coupled to the second node and a cathode coupled to the first node.

Abstract: A voltage adjustment circuit includes switches connected in parallel between a circuit unit and an electric power supply line to which a first electric power supply voltage is applied, and changes the number of switches turned off, based on a comparison result between a target value and a second electric power supply voltage supplied to the circuit unit, to adjust the second electric power supply voltage. A control circuit decides an interval for increasing the number of switches turned off when the circuit unit changes to standby state, based on a leak current value of the circuit unit in standby state, a time in which the second electric power supply voltage changes from a first to a second value, the first and second values, and an electric potential difference by which the second electric power supply voltage changes when one switch switches between on and off.

Abstract: A power supply voltage detection circuit can detect the power supply voltage obtained by stabilizing a power supply voltage supplied from outside and also the magnitude of the power supply voltage before being stabilized. This power supply voltage detection circuit includes a selection circuit that selects one power supply potential from among a plurality of power supply potentials including a first power supply potential supplied from outside and a second power supply potential obtained by stabilizing the first power supply potential, a variable voltage dividing circuit that divides the voltage between the power supply potential selected by the selection circuit and a reference potential by a set division ratio, a comparison voltage generation circuit that generates a comparison voltage based on a reference voltage, and a comparator that compares the voltage divided by the variable voltage dividing circuit with the comparison voltage and outputs a signal representing a comparison result.

Abstract: The invention provides a protection circuit applied in an inductive boost converter, the inductive boost converter includes a transmission circuit and a charging circuit, the protection circuit includes a detection circuit and a control circuit, an input terminal of the detection and an output terminal of the transmission circuit are connected, a first output terminal of the detection circuit and an input terminal of the charging circuit are connected, a second output terminal of the detection circuit and an input terminal of the control terminal are connected; the detection circuit detects whether an input current from the transmission circuit is a short-circuit current, if the circuit is shorted, the result will be sent to the control circuit, the control circuit cuts the connection of the charging circuit and ground, which can prevent charges stored in the charging circuit from flowing backward into the input terminal of the inductive boost converter.

Abstract: A dual channel transistor includes a first gate electrode, a second gate electrode, a first gate insulation layer, a second gate insulation layer, a silicon semiconductor channel layer, and an oxide semiconductor channel layer. The first gate insulation layer is disposed on the first gate electrode. The silicon semiconductor channel layer is disposed on the first gate insulation layer. The oxide semiconductor channel layer is disposed on the silicon semiconductor channel layer. The second gate insulation layer is disposed on the oxide semiconductor channel layer. The second gate electrode is disposed on the second gate insulation layer.

Abstract: A voltage regulator provides an output current at an output voltage, based on an input voltage. The voltage regulator has a pass transistor for deriving the output current. The voltage regulator contains a drive transistor forming a current mirror in conjunction with the pass transistor, such that the output current through the pass transistor is dependent on a drive current through the drive transistor. The voltage regulator comprises an auxiliary transistor arranged such that at least a fraction of the drive current through the drive transistor flows through the auxiliary transistor. The voltage regulator has amplification circuitry to set the drive current through the drive transistor depending on the output voltage and on a reference voltage. The voltage regulator further contains control circuitry to detect an indication for a dropout situation where a difference between the input voltage and the output voltage falls below a dropout voltage.

Abstract: A sensor comprises a sensor element configured to provide a sensor signal representing at least one measurand detected by the sensor element, an electrical circuit configured to process the sensor signal to form a data signal, a photovoltaic cell configured to provide electrical energy for the sensor element and the electrical circuit, and a housing, in which the sensor element, the electrical circuit and the photovoltaic cell are positioned, the housing including a recess in which the photovoltaic cell is positioned, and a rim surrounding the recess and protruding beyond the photovoltaic cell. A method is also provided.

Abstract: A linear voltage regulator and associated integrated circuit and method are disclosed. The linear voltage regulator is operable within a plurality of predefined operational modes, and comprises a pass element configured to generate an output voltage based on a received input voltage. The linear voltage regulator further comprises an error amplifier comprising an output node coupled with a control node of the pass element. The error amplifier is configured to generate a control signal at the output node based on the output voltage and a reference voltage. The linear voltage regulator further comprises a frequency compensation circuit configured to selectively apply an impedance to the output node based on which of the predefined operational modes is selected.

Abstract: An internal voltage trimming device and a semiconductor integrated circuit including the same are provided. The internal voltage trimming device includes a voltage dividing circuit configured to generate a feedback voltage based on a resistance of the voltage dividing circuit and a target voltage that is received in a trimming mode, and a comparator configured to compare a reference voltage and the feedback voltage to generate a comparison signal. The internal voltage trimming device further includes a direct current to direct current (DC-DC) converter configured to generate an internal voltage based on an input voltage and the comparison signal, and be disabled in the trimming mode, and an automatic trimming circuit configured to generate, in the trimming mode, a trimming signal based on the comparison signal. The voltage dividing circuit is further configured to adjust the resistance based on the trimming signal.

Abstract: A system may include date flow module circuits configured between electronic devices or circuits that may affect and/or intercept the flow of data being communicated between electronic devices. The data flow module circuits may communicate with an external controller that may want to intervene in the data communication. The data flow module circuits may be configured in a pass mode or in an intervention mode. In the pass mode, a data flow module circuit may pass on data it receives without intervention by the external controller. In the intervention mode, the data flow module circuit may receive instructions from the external controller as to the data that the external controller wants the data flow module to output.

Abstract: A programmable power discharge circuit and a method of discharging power are provided. The programmable power discharge circuit includes a programmable voltage controller, a detect circuit, and a discharge circuit. The programmable voltage controller selects and provides a threshold voltage by a voltage divider including a plurality of impedance components. The detect circuit detects a difference between the threshold voltage and a working voltage to decide whether the working voltage is discharged.

Abstract: An integrated circuit containing a SRAM memory with SRAM bits optimized to have a lower minimum read voltage than the minimum write voltage. A method for reading a SRAM memory bit using a read voltage that is lower than the write voltage.

Abstract: A system includes an inductor having first and second terminals. First and second transistors have first terminals connected to the first and second terminals of the inductor, respectively, and second terminals connected to a power supply and a common potential, respectively. Third and fourth transistors have first terminals connected to the first and second terminals of the inductor, respectively, and second terminals providing first and second output voltages of first and second polarities, respectively. First and second feedback circuits generate first and second feedback signals based on the first and second output voltages, respectively. A first control circuit controls the first and third transistors based on the second feedback signal and not based on the first feedback signal. A second control circuit controls the second and fourth transistors based on the first feedback signal and not based on the second feedback signal.

Abstract: A drive signal generator includes a drive signal generator that generates a drive signal for driving a capacitive load. In the drive signal generator, a set of a first MOSFET and a second MOSFET which are electrically connected in series between a wire of a high potential and a wire of a low potential is arranged in plurality in series. A part or all of the first MOSFETs and the second MOSFETs in the plurality of sets have different sizes from each other.

Abstract: Disclosed is a semiconductor device that suppresses stress-induced resistance value changes. The semiconductor device includes a resistance correction circuit. The resistance correction circuit includes a first resistor whose stress-resistance value relationship is a first relationship, a second resistor whose stress-resistance value relationship is a second relationship, and a correction section that controls the resistance value of a correction target resistor. The correction section detects the difference between the resistance value of the first resistor and the resistance value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction target resistor.

Abstract: Disclosed is a charge pump protection device including a power supply voltage, a charge pump to produce an output voltage higher than the power supply voltage, the charge pump including, a pumping capacitor to store voltage during a charging state and to discharge the voltage during a pumping state thereof, a plurality of switches to regulate the charging and pumping states, a charge pump capacitor to store the output voltage, and at least one current limiter in series with at least one of the plurality of switches to limit current and prevent an electrical failure of the charge pump.

Abstract: A gate line driver circuit for a display panel includes a pull up circuit to drive a gate line of a display panel to a positive voltage that causes display panel switch elements that are coupled to the gate line to transition into an on state, a first pull down transistor to drive the gate line to a first negative voltage that causes the coupled display panel switch elements to transition into an off state, and a second pull down transistor to maintain the gate line at a second negative voltage that is less negative than the first negative voltage so as to maintain the coupled display panel switch elements in the off state. Other embodiments are also described and claimed.

Abstract: A charge pump circuit that utilizes a sensing circuit for determining the current loading or status of the output supply generated by the charge pump circuit to determine a corresponding frequency for a variable rate clock for the charge pump circuit. When a current load is present, the clock frequency automatically ramps up to a relatively high level to increase the output current of the charge pump circuit. When the current load is removed and the supply is settled out, the clock frequency is automatically reduced to a relatively quieter level and the charge pump circuitry operates at a lower power level. Accordingly, the charge pump circuit is only noisy when it has to be, thus providing optimal power when required and being electrically quiet and operating at lower power at all other times.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include core circuitry having an array of memory cells and a row decoder that accesses each of the memory cells via a selected wordline and a wordline signal. The core circuitry may operate at a first supply voltage. The integrated circuit may include periphery circuitry having a column decoder that accesses each of the memory cells via a selected bitline. The periphery circuitry may operate at a second supply voltage that is different than the first supply voltage. The periphery circuitry may include voltage differential sensing circuitry that may compare the first supply voltage to the second supply voltage, sense a voltage differential between the first and second supply voltages, and delay the wordline signal when the voltage differential is greater than a threshold voltage.

Abstract: A discharge circuit unit for minimizing standby power occurring in a standby mode and an image forming apparatus having the same are provided. The discharge circuit unit is connected to an input line of alternating current (AC) power and discharges a capacitive element for reducing noises. The discharge circuit unit includes a discharge circuit including first and second resistance units connected in series to discharge the capacitive element in response to a discharge control signal generated when an input of the AC power is interrupted, and a detection circuit that detects whether the input of the AC power is interrupted, and includes third and fourth resistance units connected in series so as to generate the discharge control signal when it is detected that the input of the AC power is interrupted. Each of the first to fourth resistance units includes at least one of a resistor and a switch.

Abstract: A power device drive circuit reduces the short-circuit resistance of a power device that switches an input voltage. The power device drive circuit includes an output amplifier that applies a control voltage to a control terminal of the power device so as to be turned on and off, and an internal power supply circuit that generates a drive voltage of the output amplifier in accordance with a change in the input voltage, thereby causing the control voltage to change. In particular, the internal power supply circuit reduces the drive voltage of the output amplifier when the input voltage rises, thereby reducing the short-circuit current of the power device.

Abstract: A load driving device 10 includes a temperature detector TD1 that sets a temperature difference detection signal dt_ot to active when a temperature difference Tdif between a temperature Ttr of an output transistor T1 and an ambient temperature becomes more than a reference temperature difference Tdref1, and sets an over temperature detection signal at_ot to active when the temperature Ttr of the output transistor T1 becomes higher than a reference temperature Tref1, a current limiter IL1 that limits a GS current of the output transistor T1 when any one of the detection signals becomes active, and the output transistor T1 that turns off regardless of an external input signal IN when any one of the detection signals becomes active.

Abstract: In some embodiments, a system includes a bit-cell circuit and a body voltage control circuit. During a sleep mode, the bit-cell circuit receives, via a source node of a transistor, a retention voltage. During an active mode, the bit-cell receives, via the source node, an operating voltage. The body voltage control circuit includes a first transistor that connects a body node of the transistor of the bit-cell circuit to the source node such that during the sleep mode, the body node receives the retention voltage. The body voltage control circuit further includes a second transistor that connects the body node to a voltage source such that during the active mode, the body node receives the operating voltage.

Abstract: A power device drive circuit reduces the short-circuit resistance of a power device that switches an input voltage. The power device drive circuit includes an output amplifier that applies a control voltage to a control terminal of the power device so as to be turned on and off, and an internal power supply circuit that generates a drive voltage of the output amplifier in accordance with a change in the input voltage, thereby causing the control voltage to change. In particular, the internal power supply circuit reduces the drive voltage of the output amplifier when the input voltage rises, thereby reducing the short-circuit current of the power device.

Abstract: Various methods and devices that involve phase change material (PCM) switches are disclosed. An exemplary integrated circuit comprises an active layer with a plurality of field effect transistor (FET) channels for a plurality of FETs. The integrated circuit also comprises an interconnect layer comprising a plurality of conductive interconnects. The plurality of conductive interconnects couple the plurality of field effect transistors. The integrated circuit also comprises an insulator layer covering at least a portion of the interconnect layer. The integrated circuit also comprises a channel of a radio-frequency (RF) PCM switch. The channel of the RF PCM switch is formed on the insulator layer.

Abstract: A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.

Abstract: A semiconductor memory device includes a ZQ calibration unit configured to generate a pull-up VOH code according to a first target VOH proportional to a power supply voltage and an output driver configured to generate a data signal having a VOH proportional to the power supply voltage based on the pull-up VOH code, wherein VOH means “output high level voltage.

Abstract: Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes a plurality of field-effect transistors (FETs) connected in series between first and second nodes, each FET having a gate and a body. A compensation network including a gate-coupling circuit couples the gates of each pair of neighboring FETs. The compensation network may further including a body-coupling circuit that couples the bodies of each pair of neighboring FETs.

Abstract: A method for operating a microcomputer apparatus includes provisioning an electrical reference voltage that is independent of an electrical supply voltage, continuously comparing a defined level of the electrical reference voltage with the electrical supply voltage, and performing a defined operation with the microcomputer apparatus for at least one defined ratio between the defined level of the electrical reference voltage and the electrical supply voltage. The provisioning and the continuous comparing involves using a functional module of the microcomputer apparatus.

Abstract: A method and apparatus for reducing global interconnect delay on a field programmable gate array (FPGA) on an integrated circuit die comprising coding with a digital to analog coder on the integrated circuit die successive groups of n digital bits into an 2n level voltage or current signal where n is an integer greater than or equal to 2; transmitting the voltage or current signal on a global interconnect on the integrated circuit die; receiving on the integrated circuit die the signal transmitted on the global interconnect; and decoding the received signal on the integrated circuit die to reconstitute the successive groups of digital bits.

Abstract: A resistance element generator includes a reference current generation unit suitable for receiving a source reference current to generate first and second reference currents, a first resistance generation unit suitable for generating a first resistance value by using a first reference voltage and the first reference current, and outputting a first voltage corresponding to the formed first resistance value, and a second resistance generation unit suitable for generating a second resistance value by using a third reference voltage and the second reference current, and outputting a second voltage corresponding to the formed second resistance value.

Abstract: A voltage regulator includes a programming interface via which programming instructions may be applied to a processor of the voltage regulator. The voltage regulator operates the processor according to the programming instructions to select one of multiple active internally-generated analog voltage levels to determine an output voltage level of the voltage regulator.

Abstract: A motion sensor includes a sensor element that outputs a sense signal in response to a motion applied thereto and a sensor circuit that senses the motion based on the sense signal. The sensor circuit includes a sensor-element-signal amplifier that receives the sense signal. The sensor-element-signal amplifier operates switchably between at a normal mode and at a low-noise mode that consumes a larger electric power and produces a smaller noise than the normal mode. This motion sensor senses a small motion and a large motion accurately.

Abstract: A self bias buffer circuit includes a buffer and bias controller. The buffer provides a self bias voltage based on a reference voltage and to be driven based on the self bias voltage. The buffer also generates an output signal based on a comparison of an input signal and the reference voltage. The bias controller adjusts the self bias voltage based on the reference voltage.

Abstract: A multi-stage device for boosting an input voltage is discussed. Each stage of the device comprises a stage of a ring oscillator and a charge pump. An oscillating signal, generated by the ring oscillator within the device, drives the charge pump in each stage of the device. The charge pumps of the stages are serially connected. A final stage of the multi-stage device is adapted to provide voltage to a load circuit. The multi-stage device is applicable for generation of different bias voltages from one or more source voltages.

Abstract: To reduce power consumption, a semiconductor device includes a power source circuit for generating a power source potential, and a power supply control switch for controlling supply of the power source potential from the power source circuit to a back gate of a transistor, and the power supply control switch includes a control transistor for controlling conduction between the power source circuit and the back gate of the transistor by being turned on or off in accordance with a pulse signal that is input into a control terminal of the control transistor. The power source potential is intermittently supplied from the power source circuit to the back gate of the transistor, using the power supply control switch.

Abstract: A memory storage device, a memory control circuit unit and a power supply method are provided. The power supply method includes: providing a first power voltage to a host interface circuit of the memory storage device; providing a second power voltage to a memory management circuit of the memory storage device; providing a third power voltage to a memory interface circuit of the memory storage device, wherein a reference voltage terminal of the memory interface circuit is coupled to a power input terminal of the memory management circuit. Thus, the overheat problem of the memory storage device due to the voltage conversion may be improved.

Abstract: A driver for a semiconductor memory may reduce an error in writing data in memory cells by adjusting the height and width of a spike current, when the memory cells in which data having the same level are written are arranged at different distances. In addition, the driver may reduce the error by controlling the amount of charges supplied to each of the memory cells that are arranged at different distances.

Abstract: A device includes a first level shifter, a switch, and a control circuit. The first level shifter is electrically connected to a pad. The switch has an input terminal electrically connected to an input terminal of the first level shifter, and an output terminal electrically connected to an output terminal of the first level shifter. The control circuit is electrically connected to a control terminal of the switch.

Abstract: A power voltage selection device includes a first power voltage and a second power voltage; a power selection unit having a first PMOS transistor and a second PMOS transistor, wherein the first power voltage is supplied to a source of the first PMOS transistor, a gate of the first PMOS transistor receives a first enable signal, the second power voltage is supplied to a source of the second PMOS transistor, a gate of the second PMOS transistor receives a second enable signal, and a body of the first PMOS transistor is coupled to a body of the second PMOS transistor; an output unit having a common node to which a drain of the first PMOS transistor and a drain of the second PMOS transistor are commonly coupled; and a body voltage control unit controlling to supply one of the first power voltage and the second power voltage to the bodies of the first PMOS transistor and the second PMOS transistor, wherein the one has a higher voltage level than the other.

Abstract: A system and method include a controller that reduces power dissipated by a switch, such as a source-controlled field effect transistor, when an estimated amount of power dissipated by the switch exceeds a predetermined threshold. Reducing the power dissipated by the switch prevents damage to the switch due to overheating. The controller determines the estimated amount of power dissipated by the switch using actual drain-to-source current and drain voltage data. In at least one embodiment, the controller includes a fail-safe, estimated power dissipation determination path that activates when the drain voltage data fails a reliability test. Additionally, in at least one embodiment, the controller includes a model of thermal characteristics of the switch. In at least one embodiment, the controller utilizes real-time estimated power dissipation by the switch and the model to determine when the estimated power dissipated by the switch exceeds a power dissipation protection threshold.