Abstract: Embodiments of the invention provide a power supplying circuit (PSC) and a phase-change random access memory (PRAM) including the PSC. According to an aspect of the invention, the PSC includes: a first voltage generator configured to output a first voltage to a first terminal; and a second voltage generator configured to output a second voltage to a second terminal, the second voltage generator including: a voltage pump unit configured to output the second voltage based on a clock signal and a pump control signal; a pump output detector coupled to the voltage pump unit, the pump output detector configured to output a pump output detection signal; and a discharging unit coupled to the voltage pump unit, the discharging unit configured to discharge a level of the second voltage to a predetermined level in response to a discharge signal. Embodiments of the invention may prevent write and/or read malfunctions that can occur due to changes in the level of a voltage supplied to PRAM cell blocks.

Abstract: A low impedance coupling to bias voltage dissipates abnormal charge levels within a microphone in response to a shock event such as dropping or bumping. High impedance coupling to bias voltage is thereafter restored.

Abstract: A swing limiter comprises a logic circuit including a first pull-up transistor and a first pull-down transistor connected between first and second nodes and which generate an output signal; a second pull-up transistor connected between a first power voltage and the first node; a second pull-down transistor connected between the second node and a second power voltage; a first control voltage generator connected between a high voltage which is higher than the first power voltage and a first reference voltage which is lower than the high voltage; and a second control voltage generator connected between a low voltage which is lower than the second power voltage and a second reference voltage which is higher than the low voltage.

Abstract: A negative voltage generating circuit for providing a negative voltage for an electronic circuit, includes a voltage input terminal receiving a positive voltage, a voltage output terminal outputting the negative voltage to the electronic circuit, a pulse generator, a first transistor, a second transistor, a first capacitor, at least one first diode, a second diode, a second capacitor, and a first resistor. When the pulse generator outputs a high level signal, the capacitor is charged, and the full voltage of the capacitor equals the difference between the voltage of the voltage input terminal and the voltage of the at least one first diode. When the pulse generator outputs a low level signal, the capacitor discharges through the first resistor, the voltage output terminal outputs a negative voltage, the value of the negative voltage equals the difference between the voltage of the capacitor and the voltage of the second diode.

Abstract: Multiple supply voltage select circuit for use with reduced supply voltage levels and method for using same are described. A first and second set of P-channel transistors are used for voltage pull-up at a common node using two supply voltages, respectively. A P-channel transistor from each of the sets is gated by output of a respective level shifter. Both of the level shifters are biased with a higher of the two supply voltages. First and second inputs are respectively provided to the level shifters and to gates of other P-channel transistors of each of the sets.

Abstract: Noise generation is reduced further. Oscillation control circuit 11 generates a modulation signal modulating oscillation frequency of an oscillation signal generated by oscillation circuit 12 and outputs modulation signal to same. Preferably, the modulation signal fluctuates period of the oscillation signal sequentially. The oscillation circuit 12 is composed of a ring oscillator, for example, and the power supply voltage or power supply current of the ring oscillator is controlled to fluctuate sequentially by the modulation signal output from the oscillation circuit 11. Buffer 14 of charge pump circuit 13 generates signals /? and ? by the oscillation signal and drives capacitors C1 and C2 for supplying a higher voltage than the voltage of the power supply Vcc to gate of N-channel MOSFET Q1.

Abstract: According to an aspect of the present invention, there is provided a power supply circuit including: a detection circuit that is connected to an external power supply voltage and that outputs a first signal indicating whether the external power supply voltage is in a dropped-state in which the external power supply voltage is dropped below a reference voltage; a control circuit that includes: a delay circuit that outputs a second signal acquired by delaying the first signal for a reference time; and a determination circuit that outputs a third signal based on the first signal and the second signal; a generation circuit that generates internal power supply voltage from the external power supply voltage and that supplies the internal power supply voltage; and an interruption circuit that interrupts the internal power supply voltage supplied from the generation circuit based on the third signal.

Abstract: Each of first and second differential amplifiers has a function of increasing a bias current in response to the activation of a drivability control signal. A first driving circuit connects an output node to a high power supply line in response to the activation of an output signal of the first differential amplifier, and connects the output node to a low power supply line in response to the activation of an output signal of the second differential amplifier. Only during the activation period of the drivability control signal, a second driving circuit connects the output node to the high power supply line in response to the activation of the output signal of the first differential amplifier, and connects the output node to the low power supply line in response to the activation of the output signal of the second differential amplifier.

Abstract: A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified into a circuit which uses a MOST that changes dynamically into an enhancement mode and a depletion mode.

Abstract: A high-speed digital multiplexer is disclosed, The multiplexer includes a plurality of input pins for receiving a plurality of digital input signals ad switching circuitry coupled to the input pins. The switching circuitry has respective outputs coupled to a common node and is operative to enable a selected one of the plurality of input pins, The multiplexer further includes a local signal converter having a circuit branch set to a common voltage. The branch is connected to the common node to sense changes in current corresponding to an input signal received by an enabled input pin. An output pin is coupled to the local signal converter, whereby the local signal converter is operative to produce voltage changes at the output corresponding to the sensed current changes.

Abstract: An apparatus, comprising a transistor having a source/drain node and a gate, and a circuit coupled between the source/drain node and the gate and configured to limit a voltage between the source/drain node and the gate to a clamping voltage such that the clamping voltage is reduced in response to a rising temperature of the transistor. Also, a method, comprising measuring a first temperature, measuring a second temperature, and reducing a clamped voltage between a source/drain node of a transistor and a gate of the transistor responsive to a difference between the first and second temperatures increasing.

Abstract: A feedforward error-compensated receiver for minimizing undesired odd-order nonlinear distortion products. The receiver includes a first receiver path configured to receive an input signal. The first receiver path outputs a signal including at least one baseband (BB) frequency. At least one second receiver path is configured to receive the input signal and to provide a second receiver path output signal. The second receiver path includes at least one odd-order nonlinear distortion reference generator. The at least one odd-order nonlinear distortion reference generator and the mixer are configured to generate a synthetic odd-order nonlinear distortion signal. A combining element is configured to receive the output signal from the first path and the output signal from the second receiver path output and to combine the signals such that the odd-order nonlinear distortion signals are substantially attenuated at an output of the combining element.

Abstract: Provided are an apparatus and method for generating an internal voltage adaptively with respect to an external supply voltage. The apparatus includes a class detector and an internal voltage generator. The class detector outputs detection signals indicating a class of a plurality of classes, which correspond to predetermined voltages, to which an input external voltage belongs with respect to a first reference voltage. The internal voltage generator generates and outputs an internal voltage corresponding to the class to which the external voltage belongs as indicated by the detection signals.

Abstract: The present disclosure is directed to self-powered voltage islands on an integrated circuit. A structure in accordance with an embodiment includes: an integrated circuit including a power source; a voltage island; and an on-board power source provided on the voltage island for powering the voltage island independently of the power source of the integrated circuit.

Abstract: An apparatus includes a plurality of first driving signal driving units, and generates a first driving signal by driving an input signal, a plurality of second driving signal driving units, each of which drives an input signal and generates a second driving signal, a timing control unit that controls each of the first driving signal driving units such that a predetermined time difference is generated between an enable timing of the first driving signal and an enable timing of the second driving signal, a plurality of sense amplifier driving units, each of which generates a first driving level and a second driving level according to the first driving signal and the second driving signal, and a plurality of sense amplifiers that are provided for respective bit line pairs, and each include first type switching elements operating according to the first driving level and second type switching elements operating according to the second driving level.

Abstract: An apparatus and method is provided for optimizing LED driver efficiency. The present invention offers low cost solutions for powering LEDs while minimizing overall power dissipation in devices powered by a depletable power source. Low system cost is attained using a charge pump to increase LED drive voltage level and implementing combinations of drive techniques to overcome the inefficiency of the charge pump. A switch bypasses the charge pump when depletable power source output voltage is sufficient to directly drive an LED load. At certain output voltage levels, the switch can be opened causing the charge pump to boost drive voltage. The output voltage may also be PWM modulated to drive the LED load and, at some voltages, the depletable power source may drive the LED load directly. Efficiency levels of 90-97% are attainable.

Abstract: A low power system is disclosed for working in conjunction with a digital circuit that is disposed between positive and negative terminals. The system includes an internal voltage generator for increasing, for at least a first portion of the digital circuit, a voltage difference between the at least a first portion of the digital circuit and the voltage on at least one of the positive and negative terminals during a low power mode of operation. This allows the voltage across the at least first portion of the digital circuit to be less than the full voltage across the positive and negative terminals.

Abstract: A circuit configured to be programmed using a resistor includes an output terminal, a reference voltage source, a first circuit, and a current mirror arrangement. The output terminal is configured to be connected to a programming resistor. The reference voltage source is configured to generate a reference voltage on the output terminal. The measurement and evaluation circuit is configured to detect an output current on the output terminal, and to generate a control signal which is dependent on the output current. The current mirror arrangement is coupled to an output current path containing the output terminal and provides a reference current which is dependent on the output current and the control signal.

Abstract: A driving circuit includes a first switch, a first driver and a second driver. The first switch has a first terminal coupled to a first voltage. The first driver includes a second switch and a third switch. The second switch has a first terminal coupled to a second terminal of the first switch, and a second terminal coupled to a first capacitor. The third switch has a first terminal coupled to the second terminal of the second switch, and a second terminal coupled to a second voltage. The second driver includes a fourth switch and a fifth switch. The fourth switch has a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to a second capacitor. The fifth switch has a first terminal coupled to the second terminal of the fourth switch, and a second terminal coupled to the second voltage.

Abstract: A semiconductor assembly is disclosed. One embodiment provides a first semiconductor and a second semiconductor, each having a first main connection and a second main connection arranged on opposite sides, and a carrier having a patterned metallization with a first section spaced apart from a second section. The first semiconductor is electrically connected to the first section by its second main connection, and the second semiconductor electrically connected to the second section by its second main connection. The first semiconductor chip first main connection and the second semiconductor chip first main connection are electrically connected to one another and for the connection of an external load or of an external supply voltage.

Abstract: A charge pump drive circuit includes a first MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a second MOSFET. The first MOSFET and the second MOSFET are different in channel type and provided to form a complementary inverter circuit. The complementary inverter circuit drives a charge pump circuit based on an input potential inputted to an input terminal. A first gate of the first MOSFET and a second gate of the second MOSFET are connected to the input terminal such that a potential at the first gate is different from a potential at the second gate.

Abstract: A circuit (FIGS. 2A-2D) and method of providing an auto-on and/or auto-off capability for an audio device, of a type having an audio plug (14) which mates with the output jack of an audio source. The portable transmitter (10) modulates audio signals from the audio source onto a carrier and transmits them to a receiver. The auto-on and auto-off capability is provided to prolong battery life and degradation of the transmitter circuit and comprises pinching off a FET (Q2) when the circuit is in an “off” state. This occurs when a pre-determined threshold in a capacitor is reached by not discharging that capacitor. The capacitor (C29) is discharged by dropping a comparator input below a pre-determined threshold limit when presented with an audio peak and wherein the drop in value causes the comparator output to go low, causing the capacitor to discharge and causing the FET (Q2) to supply power to the regulator.

Abstract: An isolation gate to provide isolation to a circuit to be isolated for a first voltage and a second voltage includes a voltage source for the first voltage and the second voltage, a first path coupled to the circuit to be isolated and a first control switch to control the first path. The first control switch isolates the circuit to be isolated while said isolation gate is subject to either the first voltage or the second voltage.

Abstract: The present invention discloses a bias circuit for a sense amplifier having a device under sensing, the device under sensing having an un-programmed state and a programmed state, the bias circuit comprises at least one first branch having at least one first device formed substantially the same as the device under sensing and remaining in the un-programmed state, and at least one second device formed also substantially the same as the device under sensing and being in the programmed state, wherein the at least one first device and the at least one second device are serially connected. A typical application of the present invention is an electrical fuse memory.

Abstract: The present invention relates to a frequency-independent voltage divider in which a compensation structure (10) for compensating a distributed parasitic capacitance of a resistor arrangement (20) is arranged between the resistor arrangement (20) and a substrate (50). Thereby, the compensation structure (10) shields the resistor arrangement (20) partly from the substrate (50), and thus shields the parasitic capacitance. This allows for an improved compensation.

Abstract: A semiconductor device including a bias voltage generator formed from a junction field effect transistor (JFET). The JFET includes a control gate terminal and a first and a second source/drain terminal. The first and second source/drain terminals can form a first terminal of a p-n junction and the control gate terminal can form a second terminal of the p-n junction. The first terminal of the p-n junction can be provided with a first potential. The second terminal can be left essentially floating to provide a bias voltage. A bias receiving circuit can receive the bias voltage. The bias receiving circuit can be in close proximity on the semiconductor device to the bias voltage generator.

Abstract: A semiconductor integrated circuit according to the present invention comprises an MOS substrate having a substrate region (MOS) and a source region separated from each other, a dummy MOS circuit substrate-separated from the MOS circuit and having a substrate region (dummy) and a source region (dummy) separated from each other, a substrate voltage generating circuit for generating a substrate voltage to be applied to the substrate region (MOS) and the substrate region (dummy), and a comparing circuit for measuring a current generated in the dummy MOS substrate, wherein an area ratio between the substrate region (dummy) and the source region (dummy) is substantially equal to an area ratio between the substrate region (MOS) and the source region (MOS).

Abstract: An integrated circuit is provided comprising a first NMOS transistor; a first PMOS transistor; a second NMOS transistor; a second PMOS transistor; a first bias voltage node coupled to a first source/drain of the first NMOS transistor; a second bias voltage node coupled to a first source/drain of the second PMOS; a third bias voltage node coupled to a gate of the first PMOS transistor; a fourth bias voltage node coupled to a gate of the second NMOS transistor; a pull-up node coupling a second source/drain of the first NMOS transistor to a first source/drain of the first PMOS transistor; a pull-down node coupling a second source/drain of the second PMOS transistor to a first source/drain of the second NMOS transistor; an input node; a storage node coupling a second source/drain of the first PMOS transistor to a second source/drain of the second NMOS transistor; an output node; an input switch coupled to controllably communicate an input data value from the input node to a gate of the first NMOS transistor and t

Abstract: An internal voltage generator that generates an internal voltage for a Delay Locked Loop (DLL) and an internal clock generator including the same, and an internal voltage generating method for a DLL. The internal voltage generator includes a standby voltage generator that generates the DLL internal voltage as a reference voltage level, a controller that generates an active control signal in response to a power-down signal and an active signal, and an active voltage generator that generates the DLL internal voltage of the reference voltage level in response to the active control signal. After the power-down mode is ended, the active voltage generator is additionally operated during a predetermined time when the DLL is initially enabled. It is therefore possible to generate stabilized DLL internal voltages.

Abstract: Each of first and second differential amplifiers has a function of increasing a bias current in response to the activation of a drivability control signal. A first driving circuit connects an output node to a high power supply line in response to the activation of an output signal of the first differential amplifier, and connects the output node to a low power supply line in response to the activation of an output signal of the second differential amplifier. Only during the activation period of the drivability control signal, a second driving circuit connects the output node to the high power supply line in response to the activation of the output signal of the first differential amplifier, and connects the output node to the low power supply line in response to the activation of the output signal of the second differential amplifier.

Abstract: An integrated circuit includes an operational amplifier configured to receive a current sense voltage (VCS) at a first input and an offset voltage at a second input. A comparator is coupled to the operational amplifier and adapted to receive at a first input an output voltage signal (VOUT) of the operational amplifier. A voltage limiting circuit is configured to receive a regulation voltage. A fold back correction circuit is coupled to the voltage limiting circuit and to a second input of the comparator. A pulse width modulator circuit is coupled to the comparator and is adapted to receive the output of comparator.

Abstract: An embodiment of a bias switching circuit may include a first transfer switch that transmits a bias voltage to a first output node in response to a first switching signal, a second transfer switch that transmits a first power voltage to the first output node in response to a second switching signal, a third transfer switch that transmits the bias voltage to a second output node in response to the second switching signal, a fourth transfer switch that transmits the first power voltage to the second output node in response to the first switching signal. The circuit may further include a first transistor that transmits a second power voltage to the first output node in response to a third switching signal, and a second transistor that transmits the second power voltage to the second output node in response to a fourth switching signal.

Abstract: A semiconductor circuit for reducing flicker noise includes a negative-conductance generator and a body bias voltage supplying circuit. The negative-conductance generator includes a pair of cross-coupled field effect transistors in order to generate negative-conductance, wherein each field effect transistor includes a body. In order to remove flicker noise generated by the pair of the field effect transistors, the body bias voltage supplying circuit supplies a body bias voltage to the body of each of the pair of the field effect transistors so that a forward bias voltage is supplied to the body and source of each of the pair of the field effect transistors. The field effect transistors are preferably NMOS transistors or CMOS transistors. The semiconductor circuit is used in a voltage controlled oscillator (VCO) or a phase-locked loop (PLL).

Abstract: A brown-out-reset circuit having programmable power and response time characteristics. These characteristics may be programmed over an n-bit wide bus for 2n different characteristics ranging from very low power consumption and slower response time to very fast response time and higher power consumption. A serial one wire bus may be used instead of the n-bit wide bus.

Abstract: A voltage regulator operable as a voltage follower while a fusible link is closed and in a regulated voltage mode when the fusible link becomes open. The voltage regulator can be formed on monolithic semiconductor chips. Patterned thin films including aluminum and nickel-iron, and aluminum and polycrystalline silicon, comprise the fusible link. With the fusible link closed, the voltage regulator output is an analog of positive polarity variable voltage levels at the regulator input. Systems powered by the voltage regulator are allowed to be programmed until system programming requiring variable voltage levels is complete. Afterwards, a negative polarity voltage is applied to the regulator input causing a large current to pass through the fusible link once the system programming is completed. Current thereby causes the fusible link to become opened and enables the voltage regulator to begin operating at a regulated voltage in response to positive voltage input.

Abstract: A voltage conversion device capable of enhancing conversion efficiency includes a charge pump for generating output voltage linear to input voltage according to the input voltage, a feedback unit for generating a feedback signal according to the output voltage generated by the charge pump, and a regulating unit for outputting and adjusting the input voltage according to the feedback signal provided by the feedback unit, so as to keep the output voltage unchanged.

Abstract: A leakage current prevention circuit for preventing a power source from being affected by leakage current includes a first transistor, and a second transistor. A gate of the first transistor receives a control signal and a source of the first transistor is grounded. A gate of the second transistor is connected to a drain of the first transistor, a drain of the second transistor is electrically connected to the power source, and a source of the second transistor is connected to a pull-up circuit which is connected to a chipset. When the chipset receives a drive signal, the control signal controls status of the first and second transistors so that the power source provides voltage to the pull-up circuit for the drive signal.

Abstract: A circuit for providing a reference voltage includes a bandgap reference circuit, the bandgap reference circuit providing a first reference voltage and a data storage. The data storage stores a digital value corresponding to the first reference voltage. A digital to analog converter is coupled to the data storage for providing a second reference voltage corresponding to the digital value. The circuit also includes an output switch circuit responsive to at least one control signal, the output switch circuit providing either the first reference voltage or the second reference voltage to an output node responsive to the control signal.

Abstract: A method of reducing power consumption while maintaining performance characteristics and avoiding costly over-design of a high-speed communication link embedded in an SOC is provided. The method includes synthesizing the communication link at a reduced voltage to determine and isolate circuitry that is supply-voltage-critical from circuitry that is non-supply-voltage-critical. The supply-voltage-critical circuitry contains components that may not operate at the reduced voltage without degrading the performance characteristics of the communication link. A non-reduced voltage is used to drive the supply-voltage-critical circuitry while the reduced voltage is used to drive the non-supply-voltage-critical circuitry. The reduced voltage is generated using a voltage regulator embedded in the communication link.

Abstract: Method and system for dynamically adjusting performance of circuitry blocks are described. A first circuit domain is coupled to an interim storage device. The first circuit domain includes a first level shifter coupled to an input of a first circuitry block and a second level shifter coupled to an output of the first circuitry block. The second level shifter is coupled between the output of the first circuitry block and an input of the interim storage device. A controller is coupled to the first circuit domain for adjustment of a first operating voltage of the first circuit domain.

Abstract: A power-diode-driver uses a single power source to supply power to the sub-drivers inside. The sub-drivers are well isolated so that they can be safely and easily expanded by connecting to other device or driver. Thus, the power-diode driver has a changeable turn-on time and a highly modulated assembly. And, hence, the present invention is suitable for mass producing reliable power-diode drivers.

Abstract: The pin number reduction circuit circuits and methodology of the present invention provide a higher pseudo power supply and a lower pseudo power supply for a digital functional section in mixed-signal IC, memory IC, and SOC including analog functional section and digital (or memory) functional section in order to reduce digital noise coupling. The circuit and methodology of the present invention basically includes resistors, capacitors, transistors, and amplifiers. It is noted that analog functional section is coupled between a positive power supply and a negative power supply, which are connected to two pins. One amplifier with a PMOS transistor and one resistor string provides a higher pseudo power supply, and the other amplifier with an NMOS transistor and the other resistor string provides a lower pseudo power supply so that a digital functional section is coupled between these pseudo power supplies.

Abstract: Embodiments of an inductive charge pump are generally described herein. Other embodiments may be described and claimed.

Abstract: A broadband multi-phase output delay locked loop (DLL) circuit can be operated in a wide range of frequencies and generate various phases. Unlike conventional voltage control delay lines in which delay cells are connected in series, the DLL circuit utilizes a delay matrix in which a resistant network is used so that the number of delay cells connected in series is reduced, various phases can be outputted, and a delay interval error (phase error) due to the resistant network is minimized. The current of the delay cells is controlled so that the delay cells in the delay matrix can operate in a wide range of frequencies, and load capacitance values of capacitors connected in parallel in the delay cells can be controlled.

Abstract: A biasing circuit for biasing differential delay elements is provided. The circuit is a feedback-free circuit consisting of a CMOS output stage having a P-type transistor and an N-type transistor, with a diode connected transistor between the P-type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the Vnbias between the P-type transistor and the diode connected transistor. The circuit is simpler than conventional biasing circuits that employ feedback and operational amplifiers.

Abstract: Methods and apparatus are disclosed for calibrating summing amplifiers based on current integration. For example, apparatus for calibrating output voltage levels of a current-integrating summing amplifier includes the following components. A duplicate integrator circuit is provided, wherein the duplicate integrator circuit replicates an integrator circuit of the current-integrating summing amplifier. A comparing circuit, coupled to the duplicate integrator circuit, is provided for comparing at least one output voltage level generated by the duplicate integrator circuit with a reference voltage level.

Abstract: A semiconductor device and a method for controlling its patterns is described where the electrical characteristics of the patterns formed by a double patterning process may be individually controlled responsive to critical dimensions (CDs) of the patterns. The method includes controlling two or more patterns having different CDs to optimally operate the patterns. The patterns may be individually controlled by signals provided to the patterns on the basis of the pattern's CDs. The signals may be controlled by controlling the magnitudes or the application time of the signals provided to the respective patterns.

Abstract: A power supply controller having final test and trim circuitry. In one embodiment, a power supply controller for switched mode power supply includes a selector circuit, a trim circuit, a shutdown circuit and a disable circuit. The trim circuit includes a programmable circuit connection that can be selected by the selector circuit by toggling a voltage on an external terminal such as for example a power supply terminal, a control terminal or a function terminal of the power supply controller. The programmable circuit connection in the trim circuit can be programmed by applying a programming voltage to the external terminal. The shutdown circuit shuts down the power supply controller if the temperature rises above an over temperature threshold voltage. The shutdown circuit includes adjustment circuitry that can be used to test the shutdown circuit. The adjustment circuitry can adjust and reduce the over temperature threshold of the power supply controller.

Abstract: A high voltage generating circuit includes a boosting portion (e.g., a trigger coil (22)) for boosting DC voltage delivered from a DC power supply (26) so as to deliver high voltage at a secondary side, a switching element (e.g., a MOS FET (23)) for turning on and off current flowing in the primary side of the boosting portion, and a pulse signal generating portion (24B) for generating a pulse signal for controlling on and off of the switching element.

Abstract: A regulator for regulating the output from a high-voltage pump, Vpump, to provide a regulated load voltage, Vpp, to a load in MOSFET integrated circuits. The regulator includes a MOSFET switch which when enabled in a first state connects Vpp to the integrated circuit voltage level, Vcc, and which when disabled in a second state allows Vpp to be driven to levels greater than Vcc. The regulator includes a multipath control circuit for controlling the switch state and for controlling Vpp. A first current path, Iramp, controls the rise-time parameters of Vpp and a second current path, Idis, controls the fall-time parameters of Vpp. The rise-time parameters and the fall-time parameters are separately controlled.