Abstract: A semiconductor integrated circuit includes a plurality of dies, wherein each of the dies is configured to enable a power circuit provided therein according to a power control signal, in a state in which the die was determined to be a good die or a fail die.

Abstract: A semiconductor device includes rectifying elements which are connected in series and has a rectifying function from a first input terminal portion to an output terminal portion; a first wiring and a second wiring, which are connected to a second input terminal portion; and a boosting circuit including a plurality of capacitor elements each having a first electrode, an insulating film, and a second electrode and storing a boosted potential. The plurality of capacitor elements includes a capacitor element in which the first electrode and the second electrode are formed using conductive films, and a capacitor element in which at least the second electrode is formed using a semiconductor film. In the plurality of capacitor elements, at least a capacitor element in a first stage is a capacitor element in which the first electrode and the second electrode are formed using conductive films.

Abstract: A High Definition Multimedia Interface (HDMI) cable carries high speed encoded data, which are transmitted differentially over data channels, along with a clock. A Mobile High-Definition Link (MHL) cable carries high speed data which are multiplexed to achieve smaller connectors with fewer pins. A MHL-to-HDMI cable is proposed, which includes an embedded MHL to HDMI adapter device for demultiplexing the received MHL-formatted signal and outputting an HDMI-formatted signal. The embedded circuit is powered by a combination of power sources, the power being harvested from the high-speed HDMI signals themselves, including a startup circuit harvesting power from a low speed HDMI signal when power from the high-speed HDMI signals is not available.

Abstract: A power supply circuit for a PCI-E slot includes a control chip, a first electronic switch, and a second electronic switch. The control chip determines a status of a motherboard, outputting a control signal. A first terminal of the first electronic switch is connected to the control chip to receive the control signal, and connected to a +3.3V dual power supply of the motherboard through a first resistor. A second terminal of the first electronic switch is grounded. A third terminal of the first electronic switch is connected to a first terminal of the second electronic switch, and connected to the +3.3V dual power supply through a second resistor. A second terminal of the second electronic switch is connected to the +3.3V dual power supply. A third terminal of the second electronic switch is connected to a PCI-E slot.

Abstract: The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.

Abstract: A circuit module device with addresses generated by a method of divided voltage, in particular a specific circuit module device that is able to connect a plurality of circuit modules having various resistances with varied divided voltage and under this circumstance, it will be able to utilize various resistances with varied voltage values to create various specific addresses for the circuit modules thereof

Abstract: An electronic device comprises a first component susceptible to a wearout effect, operation of which first component depends on an operating parameter, and a second component having an on-state and an off-state. The electronic device further comprises a time estimator for updating an estimate of an accumulated time the second component was in the on-state; and a controller for controlling the operating parameter on the basis of the accumulated time estimate so as to respond to the expected wearout effect. The first component and the second component may be the same, or the first component may have an on-state correlated to the on-state of the second component. The operating parameter may, for example, be a level or amplitude or correction value of one of the following: a voltage applied at the first component, an electric current fed to the first component, and a power provided to the first component. A method of operating such an electronic device is also disclosed.

Abstract: Systems and methods are disclosed that use multiple DC-DC (direct-current-to-direct-current) regulators and configurable DC-DC regulators with respect to multi-band audio receivers in order to allow for the use of different DC-DC regulator switching clock signals for different audio broadcast bands. The systems and methods disclosed thereby help to alleviate interference problems typically caused by switching devices used in the DC-DC conversion process. The embodiments described are also applicable to switching power supplies run from alternating current (AC) power sources and to Class D amplifiers working with broadcast radios.

Abstract: There is described a passive heater-and-diode multiplexing network for selective addressing of thermally-coupled and electrically-disconnected fuses within a passive device network (resistor/capacitor/inductor) or within an application circuit.

Abstract: A transmitter having at least one channel comprising a first differential circuit driven by a differential data signal, the first differential circuit configured to output the differential data at a first and second output and a first control circuit coupled between the first differential circuit and the first and second output, the first control circuit driven by a drive voltage.

Abstract: A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles.

Abstract: A stack package having stacked chips includes first voltage dropping units respectively formed in the chips; second voltage dropping units respectively formed in the chips; first signal generation units connected in parallel to a first line formed by connecting the first voltage dropping units in series, respectively formed in the chips, and configured to apply high level signals according to a voltage of the first line; second signal generation units connected in parallel to a second line formed by connecting in series the second voltage dropping units, respectively formed in the chips, and configured to apply high level signals according to a voltage of the second line; and chip selection signal generation units respectively formed in the chips, and configured to combine signals outputted from the first signal generation units and the second signal generation units and generate chip selection signals.

Abstract: A field-effect magnetic sensor facilitates highly-sensitive magnetic field detection. In accordance with one or more example embodiments, current flow respectively between first and second source/drain terminals and a third source/drain terminal is controlled using inversion layers in separate channel regions for each of the first and second terminals. In response to a magnetic field, a greater amount of current is passed between the third source/drain terminal and one of the first and second source/drain terminals, relative to an amount of current passed between the third source/drain terminal and the other one of the first and second source/drain terminals.

Abstract: A semiconductor chip has a gated through silicon via (TSVG). The TSVG may be switched so that the TSVG can be made conducting or non-conducting. The semiconductor chip may be used between a lower level semiconductor chip and a higher semiconductor chip to control whether a voltage supply on the lower level semiconductor chip is connected to or disconnected from a voltage domain in the upper level semiconductor chip. The TSVG comprises an FET controlled by the lower level chip as a switch.

Abstract: A design structure is provided for a reference voltage generator. The design structure includes a first capacitor and an analog to digital converter having its voltage reference coupled to the first capacitor. The first capacitor supplies the voltage reference to the analog to digital converter. A control loop is configured to resupply charges to the first capacitor that are lost when the first capacitor supplies the voltage reference to the analog to digital converter.

Abstract: A transistor includes a first active layer having a first channel region and a second active layer having a second channel region. A first gate of the transistor is configured to control electrical characteristics of at least the first active layer and a second gate is configured to control electrical characteristics of at least the second active layer. A source electrode contacts the first and second active layers. A drain electrode also contacts the first and second active layers.

Abstract: A circuit for balancing a sub-stack voltage in a stack of ultracapacitors includes a pair of electrical leads that are connectable across a first sub-stack of one or more ultracapacitors, wherein a stack includes N sub-stacks of ultracapacitors coupled to an electrical bus, a discharge device switchably connectable with the pair of electrical leads, the discharge device configured to discharge the sub-stack of ultracapacitors, a voltage sensing circuit coupled to the electrical bus and configured to sense and output a voltage of the stack of ultracapacitors after the first sub-stack of one or more ultracapacitors has been discharged to a given threshold, and a voltage amplifier coupled to the output of the voltage sensing circuit and coupled to the pair of electrical leads, the voltage amplifier configured to provide a re-charge voltage to the first sub-stack of one or more ultracapacitors.

Abstract: A circuit includes a memory cell having a ground reference node, a switch coupled to the ground reference node, and a mode changing circuit having an output coupled to the switch. The mode changing circuit is configured to change a logic state of the output between a first output logic state and a second output logic state in response to a change in an operational voltage and/or temperature, thereby set the memory cell in a first mode in which the ground reference node is at first reference level or in a second mode in which the ground reference node is at a second reference level different from the first reference level.

Abstract: An integrated circuit includes a number of pads. The integrated circuit further includes a cascode transistor having an open drain connection to a first one of the pads. A bias generator circuit is included in the integrated circuit. The bias generator circuit has an output connected to a gate terminal of the cascode transistor. In a first mode of operation, the bias generator outputs a bias signal that is derived from an integrated circuit supply voltage present at a second one of the pads. However, in a second mode of operation provided when the integrated circuit supply voltage is not present, the bias generator generates the bias signal derived from a voltage present at the first one of the pads.

Abstract: An integrated circuit (IC) system includes a plurality of ICs configured in a stacked voltage domain arrangement such that a low side supply rail of at least one of ICs is common with a high side supply rail of at least another of the ICs; a reversible voltage converter coupled to power rails of each of the plurality of ICs, the reversible voltage converter configured for stabilizing individual voltage domains corresponding to each IC; and one or more data voltage level shifters configured to facilitate data communication between ICs operating in different voltage domains, wherein an input signal of a given logic state corresponding to one voltage in a first voltage domain is shifted to an output signal of the same logic state at another voltage in a second voltage domain.

Abstract: Disclosed herein are nanoscale devices comprising one or more ferroelectric nanoshells characterized as having an extreme curvature in at least one spatial dimension. Also disclosed are ferroelectric field effect transistors and metal ferroelectric metal capacitors comprising one or more ferroelectric nanoshells. Methods for controlling spontaneous ferroelectric polarization in nanoshell devices are also disclosed.

Abstract: An electrochemical gas sensor testing device that includes a test signal generator that generates a multiplexed signal that includes a first test signal that includes alternating current (AC) and is free from a direct current (DC) component and a second signal that includes a DC bias voltage, an electrochemical cell that includes a counter electrode, a sensing electrode, and an electrolyte, the counter electrode and the sensing electrode being in electrical communication with the electrolyte and each other, the counter electrode being in electrical communication with the signal generator to receive the multiplexed signal generated by the signal generator, and a processor that receives an AC signal from the sensing electrode and that analyzes the AC signal.

Abstract: An embodiment of a variable stage charge pump includes a plurality of pump stages. Each stage is configured to generate an intermediate boosted output voltage. A pump stage selector selects the number of charge pump stages to be coupled between an input and output terminal of the variable stage charge pump. The pump stage selector may control a plurality of switches to select the number of stages. For example, two stages maybe coupled in parallel and the parallel combination coupled in series to a third stage, resulting in a two stage charge pump. For a three stage charge pump, all three stages are coupled in series.

Abstract: A power control circuit includes an input/output controller hub (ICH), and first to third metal-oxide-semiconductor field effect transistors (MOSFETs). A drain of the first MOSFET is connected to a standby power source through a first resistor. A gate of the first MOSFET is connected to a sleep control terminal of the ICH through a second resistor. A drain of the second MOSFET is connected to the drain of the first MOSFET through a third resistor. A gate of the second MOSFET is connected to a general purpose input/output terminal of the ICH through a fourth resistor. A source of the third MOSFET is connected to the standby power source. A gate of the third MOSFET is connected to the drain of the second MOSFET. A drain of the third MOSFET is connected to a power terminal of an onboard network interface card.

Abstract: Embodiments for at least one method and apparatus of a wireless transceiver are disclosed. For one embodiment, the wireless transceiver includes a transmit chain, wherein the transmit chain includes a power amplifier. The wireless transceiver additionally includes a receiver chain that is tunable to receive wireless signals over at least one of multiple channels, wherein the multiple channels are predefined. Further, the wireless transceiver includes a voltage converter. The voltage converter provides a supply voltage to the power amplifier, and operates at a single switching frequency, wherein the single switching frequency and all harmonics of the single switching frequency fall outside of the multiple channels.

Abstract: Systems, methods, and devices are disclosed, including an electronic device that includes a first data location, a quantizing circuit, and a reference current source, all coupled to an electrical conductor. The reference current source may include a current mirror with a side coupled to the electrical conductor and a second data location coupled to another side of the current mirror.

Abstract: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

Abstract: According to one disclosed embodiment, an adaptive voltage rail circuit for integrating low voltage devices with high voltage analog circuits is described. This adaptive voltage rail circuit includes a high voltage analog circuit having a common mode voltage. Further included is a first voltage rail having a first rail voltage which is based on and greater than the common mode voltage of the high voltage analog circuit. A second voltage rail having a second rail voltage which is based on and less than the same common mode voltage is also present. By connecting these first and second voltage rails across at least one low voltage device, an adaptive voltage rail circuit is able to safely integrate low voltage devices with high voltage analog circuits in the same system.

Abstract: An apparatus and method for the dynamic detection and compensation of performance variations within an integrated circuit (IC) is provided to detect performance variations within the IC at any stage of test or operation. An arbitrary reference signal is utilized in conjunction with an internal oscillation device to establish a speed reference that may be used to characterize the IC. Dynamic detection and compensation may also be configured within a plurality of geographic locations within the IC, so that performance variations may be detected and compensated. Test data that is indicative of the IC's performance may be dynamically generated continuously, or at programmable intervals, so that performance variations caused by virtually any source may be substantially detected and compensated at any point in time of the IC's life cycle.

Abstract: According to an embodiment, a semiconductor device includes a functional circuit, an electric current measurement circuit and a control circuit. The functional circuit operates with a supplied electric power. The electric current measurement circuit is configured to measure an electric current based on the electric power. The control circuit is configured to control an operation of the functional circuit in accordance with operation information about the functional circuit and the measured electric current.

Abstract: An integrated circuit chip includes a first input port, a first output port, and first and second transistors electrically coupled in series across the first input port. The second transistor is also electrically coupled across the first output port and is adapted to provide a path for current flowing through the first output port when the first transistor is in its non-conductive state. The integrated circuit chip additionally includes first driver circuitry for driving gates of the first and second transistors to cause the transistors to switch between their conductive and non-conductive states. The integrated circuit chip further includes first controller circuitry for controlling the first driver circuitry such that the first and second transistors switch between their conductive and non-conductive states to at least substantially maximize an amount of electric power extracted from an electric power source electrically coupled to the first input port.

Abstract: An internal source voltage generating circuit includes a comparison voltage generator which receives reference and internal source voltages, outputs to a second node a comparison voltage differentially amplified responsive to a voltage of a first node according to a difference between the reference and internal source voltages, and allows a driving current to flow from a third node to a fourth node. An internal voltage driver transfers an external source voltage to an output node responsive to the comparison voltage. A driving current generator increases the driving current flowing from the third node to the fourth node responsive to the voltage of the first node which rises when the internal source voltage abruptly drops. The internal source voltage generating circuit is insensitive to variation of an external source voltage, exhibits improved response time when an internal source voltage abruptly drops, and stably generates an internal source voltage.

Abstract: A semiconductor device includes an overdriving control circuit configured to generate a first drive signal and a second drive signal in response to an internal signal of an active command mode, an equalizing signal generating unit configured to generate an equalizing signal which is controlled with an overdriving voltage VPP level higher than a normal drive voltage during a first duration of an activation period and with the normal drive voltage VDD during a second duration of the other activation period after the first duration in response to the first drive signal and the second drive signal, and an equalization unit configured to equalize first and second lines in response to the equalizing signal.

Abstract: To reduce power consumption of a semiconductor integrated circuit and to reduce delay of the operation in the semiconductor integrated circuit, a plurality of sequential circuits included in a storage circuit each include a transistor whose channel formation region is formed with an oxide semiconductor, and a capacitor whose one electrode is electrically connected to a node that is brought into a floating state when the transistor is turned off. By using an oxide semiconductor for the channel formation region of the transistor, the transistor with an extremely low off-state current (leakage current) can be realized. Thus, by turning off the transistor in a period during which power supply voltage is not supplied to the storage circuit, the potential in that period of the node to which one electrode of the capacitor is electrically connected can be kept constant or almost constant. Consequently, the above objects can be achieved.

Abstract: Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an activation code and a second programmable non-volatile memory that is capable of storing the activation code. If an integrated circuit passes testing, the activation code stored in the first non-volatile memory is written into the second non-volatile memory. An integrated circuit is independently functional upon separation from the cluster if the codes in the first and second non-volatile memories match. Upon separation, integrated circuits are queried to determine which respond. Each integrated circuit includes logic adapted to determine whether the codes in the first and second non-volatile memories match. If the codes do not match, the logic permanently disables the integrated circuit upon separation from the cluster.

Abstract: The present invention relates to an electronic device, which comprises: a first module, comprising an I/O pad for being an interface between the electronic device and an external device, and receiving a first bias source; a second module, coupled to the first module, comprising a register, and receiving a second bias source; and a signal converter, coupled between the first module and the second module. Wherein when one of the first and second bias sources is stable and the other is unstable, the signal converter outputs a first predetermined bias value to the first or second modules receiving the unstable bias source.

Abstract: According to one embodiment, a peak detector having extended dynamic range comprises a first differential output coupled to a supply voltage of the peak detector by a first load and coupled to ground by first and second switching devices, and a second differential output coupled to the supply voltage by a second load and coupled to ground by third and fourth switching devices. The control terminals of the first, second, third, and fourth switching devices receive a common bias voltage, and the respective first and second control terminals are configured as differential inputs of the peak detector. In some embodiments, corresponding first power terminals of the first and second switching devices share a first common node further shared by the first differential output, and corresponding first power terminals of the third and fourth switching devices share a second common node further shared by the second differential output.

Abstract: A bias current generator comprising at least one field effect transistor operating as a current source or sink, a capacitive store for storing a first control voltage, and a first switch for selectively connecting the capacitive store to a gate of the at least one field effect transistor.

Abstract: An internal voltage generating circuit includes a supply voltage driving unit, an internal voltage driving unit, and a driving control unit. The supply voltage driving unit is configured to compare a voltage division signal of a supply voltage with a bias voltage, generate a first pull-up signal, and drive the supply voltage in response to the first pull-up signal. The internal voltage driving unit is configured to receive the supply voltage, generate a second pull-up signal, and drive an internal voltage. The driving control unit is configured to select the first pull-up signal or a power supply voltage as a third pull-up signal.

Abstract: A universal serial bus device includes: a core circuit having a first pin and a second pin, and having an input impedance looking into the core circuit from the first pin and the second pin; and a charging control circuit, coupled to the core circuit, arranged for selectively providing a voltage source to one of the first pin and the second pin; wherein the input impedance of the core circuit is configured to make the voltage source substantially intact when the voltage source is coupled to one of the first pin and the second pin.

Abstract: A radio receiver includes a down-converter 110 for receiving a radio multiplexed signal containing a first signal and a second signal, multiplying the first signal and the second signal by a mixer 104 to thereby down-convert the radio multiplexed signal and generate an intermediate frequency signal 5e. The mixer 104 has a control section for controlling an operating bias of the mixer 104 in response to a signal strength of at least either one of the first signal or the second signal. Thus, the dynamic range of the mixer can be widened so that stable image characteristics can be obtained over a wide range of transmission distance.

Abstract: An amplifier comprises a power source, a load network comprising a load and a resonance circuit, an input branch having a first end electrically coupled to the power source and a second end electrically coupled to the load network, and an active switch having one terminal electrically coupled to the second end of the input branch. The input branch including at least one parallel-LC-circuit configured to provide an infinitely large impedance at harmonics of a determined order.

Abstract: An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of the transistors are controlled by a control circuit that generates a first control signal to set the impedance of another PMOS transistor to be equal to a first predetermined resistance, and generates a second control signal to set the impedance of another NMOS transistor to be equal to a second predetermined resistance. The first control signal is used to control all of the PMOS transistors and the second control signal is used to control all of the NMOS transistors. As a result, the PMOS and NMOS transistors coupled to each input terminal have impedances corresponding to the first and second resistances, respectively.

Abstract: A semiconductor device with a reduced layout area includes pads disposed between a first voltage line and a second voltage line; first and second driver units adjacently disposed at an upper portion or a lower portion of the respective pads; and a metal line disposed between the pads and supplying power commonly to the first and second driver units.

Abstract: A power supply controller having final test and trim circuitry. In one embodiment, a power supply controller for switched mode power supply includes a selector circuit, a trim circuit, a shutdown circuit and a disable circuit. The trim circuit includes a programmable circuit connection that can be selected by the selector circuit by toggling a voltage on an external terminal such as for example a power supply terminal, a control terminal or a function terminal of the power supply controller. The programmable circuit connection in the trim circuit can be programmed by applying a programming voltage to the external terminal. The shutdown circuit shuts down the power supply controller if the temperature rises above an over temperature threshold voltage. The shutdown circuit includes adjustment circuitry that can be used to test the shutdown circuit. The adjustment circuitry can adjust and reduce the over temperature threshold of the power supply controller.

Abstract: Apparatus are disclosed, such as those involving a transmitter circuit that is configured to generate multi-level signals based on a plurality of data digits. One such transmitter circuit includes a signal output and an encoder configured to provide control signals based at least partially on the plurality of data digits. The transmitter circuit also includes a first set of switches configured to receive one or more of the control signals, and to selectively conduct a first or second voltage reference to the signal output. The transmitter circuit further includes first and second voltage drop circuits that provide third and fourth voltage references, respectively. The third and fourth voltage references have voltage levels between those of the first and second voltage references. The transmitter circuit also includes a second set of switches configured to receive one or more of the control signals, and selectively conduct the third or fourth voltage reference to the signal output.

Abstract: An embodiment of a variable stage charge pump includes a plurality of pump stages. Each stage is configured to generate an intermediate boosted output voltage. A pump stage selector selects the number of charge pump stages to be coupled between an input and output terminal of the variable stage charge pump. The pump stage selector may control a plurality of switches to select the number of stages. For example, two stages maybe coupled in parallel and the parallel combination coupled in series to a third stage, resulting in a two stage charge pump. For a three stage charge pump, all three stages are coupled in series.

Abstract: A method and apparatus for reducing power consumption of transistor-based circuit is disclosed. The method includes receiving a low power mode indication; determining whether to supply power to at least a portion of the transistor-based circuit in response to a reset value of the transistor-based circuit and a state of the transistor-based circuit prior the receiving of the low power mode indication, and selectively providing power to at least a portion of the transistor-based circuit. The apparatus is adapted to receive a low power mode indication, and includes: a determining circuit to determine whether to supply power to at least a portion of the transistor-based circuit in response a state of the transistor-based circuit prior the receiving of the low power mode indication; and a power gating, adapted to selectively provide power to at least a portion of the transistor-based circuit in response to the determination.

Abstract: To provide a semiconductor device of which a manufacturing process is simplified and which has a boosting circuit in which the area of a capacitor element is reduced. The present invention includes a plurality of rectifying elements which is connected in series and has a rectifying function from a first input terminal portion to an output terminal portion; a first wiring and a second wiring, which are connected to a second input terminal portion, into which a signal and a signal obtained by inverting the signal are respectively input; and a boosting circuit including a plurality of capacitor elements each having a first electrode, an insulating film, and a second electrode and storing a boosted potential. The plurality of capacitor elements includes a capacitor element in which the first electrode and the second electrode are formed using conductive films, and a capacitor element in which at least the second electrode is formed using a semiconductor film.

Abstract: A negative voltage generating circuit includes a pulse generator U1, a switch, a resistor, a first capacitor, a first diode, a second diode, and a second capacitor. The pulse generator includes a positive voltage input pin coupled to a power supply, an oscillating output pin, and a negative voltage input pin. The switch includes a first terminal coupled to the oscillating output pin, a second terminal coupled to one terminal of the first capacitor, and coupled to the power supply via the resistor, and a third terminal being grounded. Another terminal of the first capacitor is coupled to the anode of the fist diode and the cathode of the second diode. The cathode of the first diode is grounded. The anode of the second diode is coupled to the positive voltage input pin of the pulse generator, and is coupled to ground via the second capacitor.