Abstract: A memory device includes an array of memory cells arranged in rows and columns with a portion of the rows of the memory cells being divided into segments. A global bias circuit generates a plurality of first bias currents. Each of a plurality of local bias networks includes a local bias circuit that generates a plurality of second bias currents in response to a corresponding one of the plurality of first bias currents, and includes a plurality of segment bias circuits that each generates a third bias current. Each segment bias circuit is adjacent to a corresponding segment of the memory cells. Each segment bias circuit provides a ground feedback signal to the local bias circuit, which adjusts the second bias current in response to the ground feedback signal. The segment bias circuits are disposed in geometric positions in the segments.

Abstract: External output terminal 28 is clamped by clamping circuit 20, and a current mirror is configured using diode circuit 23 within clamping circuit 20 and detector transistor 34. When the voltage of external output terminal 28 can no longer be maintained by the first current supply circuit 11 alone as load 27 increases, clamping circuit 20 shuts off, and detector transistor 34 shuts off. As detector transistor 34 shuts off, the second current supplying element 12 becomes conductive and supplies a current to load 27. Because the second current supplying element 12 is not operating during normal operation during which the current consumption by load 27 is low, the current consumption is low. In addition, because no amplifier is required, only a small number of elements are required.

Abstract: A capacitive element includes two or more voltage-variable capacitors (varactors). The varactors are configured so that they are coupled in series with respect to an applied AC signal and are coupled in parallel with respect to an applied DC bias voltage. The effective capacitance of the overall capacitive element can be tuned by varying the DC bias voltage.

Abstract: An IC device has a MOSFET serving as a power switch, a condenser connected between a first input terminal of the IC and the gate of the MOSFET, and a ferroelectric condenser connected between a second input terminal of the IC and the gate of the MOSFET. A prescribed voltage having a predetermined polarity is applied across the first and the second input terminals to generate a remanent polarization oriented in a specific direction in the ferroelectric condenser, thereby raising the threshold voltage of the MOSFET to a higher level than its original level. The power switching MOSFET is fabricated in the same manufacturing process as for other circuit blocks of the IC device such that it has substantially the same threshold voltage as that of the MOSFETs in other circuit blocks.

Abstract: A first bias voltage generating circuit which applies a bias voltage to an amplifier circuit of an AD converter has a driving unit and a control unit. The driving unit includes a first bias circuit and a second bias circuit as a plurality of bias circuits which are connected in parallel and have different current driving capabilities. The first bias circuit and the second bias circuit each include a CMOS transistor which is connected directly between a power supply potential and a ground potential, and a switching element which interrupts a feedthrough current. The drains of the CMOS transistors output the bias voltage. The control unit turns on both or either one of the first bias circuit and the second bias circuit, thereby controlling the current driving capability of the entire driving unit.

Abstract: The invention relates to a conversion circuit to convert a differential power signal II[1], II[2] into a differential output current IC[1], IC[2], said circuit including conversion means CONV and regulation means REG for the input impedance of the circuit connected to the conversion means CONV. The regulation means REG according to the invention include negative feedback means to control a regulating current IREG taken from each component of the power signal II[1], II[2] as a function of the values of the potentials V[1], V[2] at the inputs of the conversion circuit. The half-sum between the two potentials V[1], V[2] at the inputs of the circuit is advantageously used to guide the negative feedback which can advantageously be applied to the bases of the regulation transistors controlling the value of the regulating current.

Abstract: An improvement in a communications device, such as a transceiver, which is used with a fiber optic communication line, wherein the communications device is powered from a host device. The improvement is a voltage supply circuit which comprises a full wave bridge rectifier responsive to data and control signals from the host device to produce plus and minus rectified voltage signals. First and second voltage regulators are responsive to the rectified voltage signals to product plus and minus regulated voltages, for example ±5 volts, which is sufficient to power the communications device. A charge circuit alternately transfers energy from the plus and minus voltage lines to ensure the presence of plus and minus voltage signals when only positive or negative signals are provided by the host device.

Abstract: Different reference voltages are employed in different logical electrical circuits. In the conventional arts, a reference voltage circuit is only employed in a specific logical electrical circuit or a reference voltage circuit with fuse can changes a reference voltage by fusing the fuse. Nevertheless, the reference voltage circuit with fuse is still only employed in a specific system of logical circuit regardless of the fuse is fused or unfused. A select reference voltage circuit for a logical electrical system of the present invention can solve the problem. Therefore, the select reference voltage method for a logical electrical system can be employed in different systems having respective different system voltages.

Abstract: A capacitive load driving circuit (1) for charging and discharging a capacitive load (11) is provided with a voltage divider (5) for dividing a power supply voltage (VH) into a plurality of different voltages (V1-V9), a plurality of condensers (2a-i) to which the voltages (V1-V9) are respectively charged as terminal voltages, and a switch (7) for switching connections between the capacitive load (11) and the condensers (2a-i), the switch (7) sequentially connecting the condensers (2a-i) in an ascending order of the terminal voltages so that electrostatic energy is supplied to the capacitive load (11) when the capacitive load (11) is charged, the switch (7) sequentially connecting the condensers (2a-i) in a descending order of the terminal voltages so that electrostatic energy is collected from the capacitive load (11) when the capacitive load (11) is discharged.

Abstract: A method and a device generate a reference voltage for discriminating between the logic states of a data signal received at a receiving end. A transmitting device transmits a continuous clock signal with a constant pulse period duration and a symmetrical sequence of low and high clock signal states in such a way that, at the receiver end, the clock signal has the same low and high voltage levels as the received data signal and it is subject to the same system-governed variations as the received data signal. An integrator at the receiver end receives and integrates the clock signal, and the integrated value becomes the reference voltage for the receiver unit.

Abstract: A VDC circuit that supplies an internal voltage VDD1 to an internal circuit in a normal operation forces a transistor off in a burn-in test mode through input of a test signal to suppress supply of an external power supply voltage VDDH to a node. In a burn-in test mode, an external power supply voltage lower than external power supply voltage VDDH and higher than internal voltage VDD1 is supplied from an external pad.

Abstract: Charging a storage cell requires the electromotive force exerted at a photogenerating cell in addition to the voltage equal to or higher than the forward on voltage developed at an backflow preventing diode. Therefore, the charging is inefficient. Moreover, the area of the backflow preventing diode must be large in consideration for a current supply from the photogenerating cell at a high intensity of illumination.

Abstract: A bias generator adjustment system adjusts a PLL or DLL bias generator dependent on negative bias temperature instability effects in an integrated circuit. The bias generator adjustment system uses an aging independent reference circuit and a bias circuit to operatively adjust a bias generator such that transistor ‘aging’ effects that occur over the lifetime of an integrated circuit are compensated for or corrected.

Abstract: A voltage control circuit for a non-volatile memory (NVM) array or other integrated circuit that uses a comparator circuit, a switch control circuit, and a pair of PMOS switches to selectively couple an output node to the greater of two voltage signals. An output gain provided by the comparator circuit is used to control the coupling process such that the voltage difference needed to switch between the first and second voltage signals is minimized. The high or low comparator output signal is transmitted to the switch control circuit, which utilizes a pair of level shifters to control the pair of PMOS switches, which in turn couple one of the first and second voltage sources to the output node.

Abstract: A cascode SSTL output buffer using a source follower circuit includes a biasing circuit arranged to generate a first bias signal. The source follower circuit is responsive to the first bias signal and generates a second bias signal which is then used by a cascode circuit that receives an input signal to the SSTL output buffer to drive an output signal from the SSTL output buffer.

Abstract: Even in the case where the reference voltage of a reference-voltage generating circuit is adjusted by fuses, a number of fuses are required to be disconnected, and the area of fuse circuits tends to increase for fine adjustment. Therefore, by dividing control signals into one part that are predetermined by fixed wiring and another part that is adjustable by fuse circuits, time required for disconnecting fuses is minimized and fine adjustment is made possible.

Abstract: A method and apparatus for generating a reference voltage potential, also known as an input switching reference, using differential clock signals or other differential signals that ideally have a 180 degree phase shift is provided. The differential signals are generated by a transmitting circuit. The reference voltage potential is dependent on the differential signals. The voltage potentials of the differential signals are averaged and low-pass filtered. Comparators in a receiving circuit compare an input signal's voltage potential to the reference voltage potential to determine if the transmitted input signal is a binary one or binary zero.

Abstract: A calibration configuration for setting an adjustable impedance has a voltage divider with a variable resistor and a resistor connected in series, which circuit is supplied with potentials of a supply voltage and has, between the resistors, a partial voltage tap off terminal. A circuit has a further resistor, whose value is in a fixed relationship with a resistance of the first voltage divider resistor, and generates a voltage dependent upon a value derived from the further resistor. The voltage and the partial voltage are fed to a comparator for outputting a comparison result to a downstream control logic unit, which logic unit is coupled to the resistor of the first voltage divider and generates a control signal dependent upon the comparator output signal. The control logic unit control signal is used to set the variable resistor until the voltages fed to the comparator correspond to one another.

Abstract: A start up circuit includes: a diode Q0; a first transistor Q1 coupled in series with the diode Q0; a first resistor R4 coupled in series with the first transistor Q1; a second transistor Q2 having a control node coupled to a control node of the first transistor Q1 and coupled to a node between the first transistor Q1 and the first resistor R4; and a second resistor R2 coupled in series with the second transistor Q2 such that a current in the second transistor Q2 is independent of a voltage applied across the diode Q0, the first transistor Q1, and the first resistor R4.

Abstract: A means of high speed switching of a current source is accomplished by switching the source of the output current source transistor. The primary capacitance charging is the source diode, and the source of charge for this is a power rail. Circuitry is employed to limit the movement of the drain, resulting in both a reduction of and a good match of transients coupling to the output. Circuitry is also added to compensate for any current remaining when the current source is turned off.

Abstract: A semiconductor integrated circuit operating in an active state and a sleep state has a power line that is branched through a first transistor to a first virtual power line and through a second transistor to a second virtual power line. The first transistor is switched on in the active state and off in the sleep state; the second transistor is switched off in the active state and on in the sleep state. The first virtual power line powers logic circuits. The second power line powers a memory circuit that stores necessary logic-circuit signal levels during the sleep state. The memory circuit does not consume power in the active state.

Abstract: When an AC adaptor is removed and a power supply to a power node NP of a ROM writing apparatus is stopped, an analog switch which is controlled by a voltage at the power node NP is turned off. Thus, even if a power voltage VTG of a user board side is applied, a data signal DAT which is outputted from the user board is shut off by the analog switch and does not reach the power node NP via a diode. Therefore, a control terminal of a 3-state buffer is certainly set to “L”. There is not a risk such that a pass current flows in the 3-state buffer and a breakdown by heat is caused. When a power source is shut off, a breakdown of an interface circuit due to a wraparound of a power voltage from another apparatus is prevented.

Abstract: A charge pump circuit includes inverters INV1 and INV2. The inverter INV1 receives a clock signal CLK2, and applies a voltage waveform at an immediately previous node to a second end of a capacitor connected to a transistor and to the p-well thereof. The voltage of the capacitor on the side of the control terminal of the transistor, and the voltage waveform at the node, are raised with the same phase timing as the clock signal CLK1. The inverter INV2 receives a clock signal CLK1, and applies a voltage waveform at an immediately previous node to a second end of another capacitor connected to another transistor and to the p-well thereof. The voltage of the another capacitor on the side of the control terminal of the another transistor, and the voltage waveform at the node, are raised with the same phase timing as the clock signal CLK2.

Abstract: A current supply circuit supplies a bias current to operational amplifiers which constitute a pipelined AD converter. A current switching circuit switches between output currents in response to a current control signal from current control means, thereby switching between currents to be supplied from a bias circuit to the operational amplifiers via transistors. A sufficiently large current enough for the amplifiers to operate at a high frequency is supplied, while the current is switched to a lower supply current for the amplifier to operate at lower frequencies.

Abstract: A semiconductor integrated circuit includes a switch unit for controlling the supply of a power source voltage to a signal amplification circuit for receiving an input signal, and a control unit for selectively turning ON and OFF the switch unit in accordance with the amplitude or frequency of the input signal. By the constitution, it is possible to provide an input circuit or an output circuit capable of being applied to an input/output interface adapted for a small amplitude operation.

Abstract: A SSTL memory interface pre-driver stage that uses a voltage regulator to generate a ‘virtual’ supply is provided. The ‘virtual’ supply, being lower than a power supply voltage of the pre-driver stage, allows low voltage transistors to be used, thereby improving interface performance and decreasing system power consumption. The pre-driver stage uses a biasing circuit to bias the voltage regulator, formed by a transistor arranged in a source follower configuration, to generate the ‘virtual’ supply off which a voltage translator stage of the pre-driver stage operates to generate an output of the pre-driver stage.

Abstract: A voltage control circuit for a non-volatile memory (NVM) array or other integrated circuit that uses a comparator circuit, a switch control circuit, and a pair of PMOS switches to selectively couple an output node to the greater of two voltage signals. An output gain provided by the comparator circuit is used to control the coupling process such that the voltage difference needed to switch between the first and second voltage signals is minimized. The high or low comparator output signal is transmitted to the switch control circuit, which utilizes a pair of level shifters to control the pair of PMOS switches, which in turn couple one of the first and second voltage sources to the output node.

Abstract: Methods and systems for protecting integrated circuits (“ICs”) from power-on sequencing problems provide an interim voltages during power-on sequences in order to prevent over-voltage conditions across IC terminals. Voltages at first and second terminals of a circuit are monitored and an interim voltage to the second terminal is provided when the voltage at the first terminal exceeds a first threshold and a voltage at the second terminal is below a second threshold. The interim voltage protects the circuit from excessive voltage differences across the first and second terminals during power-on sequences, and is deactivated during normal operation so as not to draw excessive current. The method/system helps to insure that multi-supply dependent logic and/or other circuitry does not receive inappropriate voltage levels, and thus helps to insure that lower voltage level based circuitry is not damaged during power-up, transients, and/or glitches.

Abstract: A micro power, light weight, small size bias supply is achieved by combining a driver element, followed by an inductor, followed by a capacitive voltage multiplier stack. Performance is enhanced and reduction in components count is achieved by having multiple stages in series, output of each stage acting as input to the next stage. It is best suited for battery operated and space environments where low power consumption is essential.

Abstract: Programmable voltage pump for producing an output voltage includes a trim input configured to set the output voltage, an output configured to emit the output voltage therefrom, and an activation/deactivation input configured to at least one of activate and deactivate the voltage pump. The activation/deactivation input includes a switch connected to the output, the switch configured to selectively connect a network to ground, the network being connected to the output.

Abstract: A circuit for providing a regulated voltage to a load. The circuit includes a power converter coupled to the load and including at least one pulse-width modulated switching device, a control circuit for providing a pulse-width modulated control signal to the pulse-width modulated switching device of the power converter based on an output voltage of the power converter, and a transient override circuit responsive to a load voltage for biasing the pulse-width modulated switching device conductive during certain load voltage conditions.

Abstract: A voltage control circuit provides a test supply voltage during manufacturing and testing of a semiconductor device and provides an operational supply voltage after certification of the semiconductor device. The operational supply voltage is lower than the test supply voltage. The voltage control circuit includes a clamp circuit having a plurality of voltage regulation devices, typically diodes. The voltage regulation devices control an output of the clamp circuit. A voltage regulator is electrically coupled to the clamp circuit and generates a first control signal based upon the output of the clamp circuit. A charge pump then receives the control signal from the voltage regulator, and, based on the value of the control signal, the charge pump generates the test supply voltage. At least one bypass device is connected to at least one of the plurality of voltage regulation devices. The bypass device is activated following the certification of the semiconductor device.

Abstract: A semiconductor device having a substrate potential generating circuit (800) is provided. The substrate potential generating circuit (800) can include a pump circuit (820), an oscillator circuit (801) and a substrate potential detector circuit (300). Substrate potential detector circuit (300) can include a voltage divider (301), differential amplifier (310), and a buffer circuit (320). Voltage divider (301) can provide a detect potential determined by the difference between an internally generated reference potential and a substrate potential. Differential amplifier (310) can receive the detect potential and a reference potential as differential inputs and may produce a substrate potential detect signal. The internally generated reference potential may be generated by a reference generator (900), that may include a reference device (918) and a compensation device (920). The internally generated reference potential may have reduced process and temperature dependency.

Abstract: An internal power voltage generator for achieving stable operation of a semiconductor device by selectively connecting an external power voltage terminal to a supply line of an internal power voltage in an operation power potential range of the semiconductor device, and generating a predetermined reference voltage in a reference voltage generator in accordance with the internal power voltage after a predetermined potential.

Abstract: A common power source line has first power supply points and second power supply points. The first power supply points are provided for supplying electric power to buffer circuits of low-frequency signal pads, while the second power supply points are provided for buffer circuits of high-frequency signal pads. A wiring distance from a power source pad to the second power supply points as well as a wiring distance from the first power supply points to the second power supply points are set to be relatively long in an overall wiring arrangement on a chip.

Abstract: An internal power voltage generating circuit of a semiconductor device includes a voltage dividing circuit composed of a single field effect transistor and a plurality of resistances incorporated into a semiconductor chip. The voltage dividing circuit divides an externally supplied power voltage into two types of voltage by conducting or non-conducting the single field effect transistor. The divided voltages are supplied as an internal power voltage to a plurality of field effect transistors incorporated into the semiconductor chip.

Abstract: An integrated circuit has a voltage divider that is configured to save current. The circuit includes a capacitor that is inventively connected to a potential sink or potential source by way of a charge branch even when the voltage divider is inactive. The capacitor is thus held at a charge state that corresponds to the charge state given an active voltage divider. The voltage divider thus becomes functional in a shorter time following activation, because the capacitor does not require recharging.

Abstract: Data pad regions are arranged in four divided regions of a semiconductor memory chip of a rectangular shape, respectively, and data pads are selectively utilized in each of the four divided regions in accordance with a word structure. Thus, it is possible to implement a semiconductor memory chip capable of being assembled in both a single chip package and a multi chip package.

Abstract: A manner of generating internal voltages such as a high voltage, an intermediate voltage and an internal power supply voltage is switched in accordance with a power supply level setting signal. When the voltage level of an external power supply voltage is low, a current drive transistor receiving an output of a comparing circuit and an auxiliary drive transistor are forcedly set in a conductive state, and external power supply voltage is transmitted on an internal power supply line. At this time, the comparing operation of the comparing circuit is stopped. When the level of the external power supply voltage is high, the comparing circuit is activated down convert the external power supply voltage for generating a peripheral power supply voltage on the internal power supply line.

Abstract: A complementary pass transistor based flip-flop (CP flip-flop) having a relatively small layout area and operable at a high speed with reduced power consumption is provided. The CP flip-flop does not need an additional circuit for retaining latched data in a sleep mode. The CP flip-flop receives a clock signal, delays the clock signal for a predetermined time period, and detects the delay time period from the clock signal. The CP flip-flop receives input data for the predetermined delay time and latches the input data until new input data is received. The CP flip-flop is advantageous in that the design of timing for retaining data can be simplified.

Abstract: A ferroelectric memory has a memory cell array of memory cells having ferroelectric capacitors, which is divided into a plurality of blocks, a boost power circuit provided in each block of the memory cell array to generate a boost voltage required for operation of the memory, a boost power switch provided between a power line connected to an external power terminal and a power supply terminal of each boost power circuit, and remaining ON during normal operation of the memory, a voltage detector circuit for detecting a drop of voltage level of the power line, and a switch control circuit for turning off the boost power switches in the blocks of the memory cell array excluding the boost power switch in a currently selected block in response to the voltage detector circuit.

Abstract: A semiconductor memory device internal voltage generator and internal voltage generating method are disclosed. The device and method are capable of supplying a uniform amount of electric charge and generating a stable internal voltage, despite variations in an external voltage. The internal voltage generator includes a PMOS driving transistor having a source connected to the external voltage, a gate connected to a driving signal, and a drain that supplies the internal voltage. The interval voltage generator also includes a driving signal generator that generates the driving signal in response to a control signal. The driving signal generator maintains a voltage between the gate and source of the PMOS driving transistor at a substantially uniform voltage level despite variations in the external voltage.

Abstract: A sequencing circuit and sequencing method are provided for applying a highest voltage of first and second system supplies to a chip. The sequencing circuit includes a first transistor coupled between the first system power supply and a power supply input to the chip and a second transistor coupled between the second system power supply and a power supply input to the chip. The sequencing circuit includes a comparator for sensing a highest voltage of the first and second system power supplies. The first transistor and second transistor are coupled to an output of the comparator. When the comparator senses that the first power supply voltage is higher than the second power supply voltage, the first transistor is turned on and couples the first power supply voltage to the power supply input to the chip.

Abstract: Method and apparatus for using a MOSFET having a thin gate oxide layer as a gate capacitor is provided. The method includes the steps of biasing at least one of a source and a drain of the MOSFET by applying a nonzero voltage to the source and the drain, and applying a voltage to a gate of the MOSFET. The voltage applied to the gate is greater than a voltage rating of the MOSFET but less than the sum of the voltage rating and the voltage applied to the source and the drain. The gate of the MOSFET may have a length that measures at least 150.0 nanometers and no more than 350.0 nanometers. The thin gate oxide layer may have a thickness that measures at least 2.00 nanometers and no more than 7.00 nanometers. The MOSFET may be constructed using CMOS technology or BiCMOS technology. Apparatuses implementing this method include a capacitor, a read channel for a hard disk drive, and an electrical circuit for amplification of a signal.

Abstract: A differential termination resistor adjusting circuit includes: a reference current producing section that produces a nearly constant reference current Iref, a reference voltage producing section that produces nearly constant reference voltages VrefH, VrefL, a replica resistor producing section that is provided with the reference current Iref to produce voltage drops Va, Vb, a control voltage producing section that produces control voltages Vcont1, Vcont2, based on the reference voltages VrefH, VrefL and the voltage drops Va, Vb, and a genuine resistor producing section that is built in a receiving side device and is connected to an input termination, characterized in that the resistances of the replica resistor producing section and the genuine resistor producing section are adjusted by the control voltages Vcont1, Vcont2.

Abstract: Power dissipation of a semiconductor integrated circuit chip is reduced when it is operated at an operating voltage of 2.5 V or below. A switching element is provided in each circuit block within the chip. Constants of the switching element are set so that leakage current in each switching element in their off-state is smaller than the subthreshold current of MOS transistors within the corresponding circuit block. Active current is supplied to active circuit blocks, while switching elements of non-active circuit blocks are turned off. Thus, dissipation currents of non-active circuit blocks are limited to leakage current value of corresponding switching elements. Thus, the sum of dissipation currents of non-active circuit blocks is made smaller than the active current in the active circuit blocks. As a result, power dissipation in the semiconductor integrated circuit chip can be reduced even in the active state.

Abstract: A semiconductor integrated circuit related to the present invention comprises a logic circuit, and a mode-switching circuit. The logic circuit has a multiplicity of logic elements, which are driven by a driving voltage applied from a dummy power supply line. The mode-switching circuit, during an active mode, supplies to the dummy power supply line a first electric potential for driving a logic element, and, during a sleep mode, supplies to the dummy power supply line a second electric potential, which is higher than zero volts, and lower than a first electric potential. In a first preferred embodiment, a second electric potential is set to a value such that it is possible to reduce logic circuit OFF leakage current during a sleep mode, and to shorten the time for transitioning from a sleep mode to an active mode.

Abstract: The present invention realizes higher-speed external output operation synchronized with a clock signal from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer. A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than a breakdown voltage of the first circuit, and operation voltages of the first and second circuits can be made equal to each other or different from each other.

Abstract: A circuit (100) for accurately tuning the absolute values of multiple parameters in a VLSI circuit by reusing a single external resistor. In the illustrative embodiment, the invention includes a first circuit (10) for generating an accurate transconductance using a single external resistor; a second circuit (20) for generating an accurate current reference using the same external resistor; and a switching circuit (60) for alternately switching on and off the first and second circuits in order to share the external resistor. The switching circuit (60) includes several switches controlled by a digital counter for turning off portions of the circuit which are not in use. In the illustrative embodiment, the invention further includes a third circuit (40) for generating one or more additional accurate reference signals. The third circuit can generate an accurate internal resistance Rint, an accurate drain to source resistance of a transistor rDS, and/or an accurate internal capacitance Cint.

Abstract: A reduced-size bipolar supply voltage generator which produces a positive and negative voltages from a unipolar power source. A single inductor is employed for current switching operation, where electric energy supplied from a power source is stored in magnetic form, and the stored magnetic energy is released as electric energy. A first and second diodes are connected to first and second ends of the inductor, respectively. The inductor is grounded at the first end via a first switch, while its second end is connected to the power source via a second switch. A switching controller activates both switches to energize the inductor. It then deactivates the first switch alone, thus directing the inductor's energy to the positive voltage output through the first diode. The controller may turn off the second switch alone after energizing the inductor. The stored energy now appears at the negative voltage output through the second diode.