Abstract: A circuit configuration for supplying voltage to an integrated circuit via a pad that is connected to the input of a Schmitt trigger on the integrated circuit. The pad is also provided for configuring the integrated circuit. The integrated circuit has a multiplicity of voltage supply lines for voltage supply purposes. According to the invention, the pad is connected to a respective voltage supply line via a respective switch, and the switches are switched on or off by a control circuit that is controlled by at least one on-chip control signal.

Abstract: An apparatus comprising one or more output circuits each configured to configure a pad as either an input/output pad, a power pad, or a ground pad in response to a plurality of configuration inputs.

Abstract: A method of adjusting a circuit operating characteristic. The method includes generating a first signal for application to a reference termination. The method then includes generating a first voltage based on the first signal at a first point on the reference termination and generating a second voltage based on the first signal at a second point on the reference termination. The method also includes adjusting an operating characteristic based upon the first voltage and the second voltage. In an embodiment, the operating characteristic can be an impedance.

Abstract: A current reference with reduced sensitivity to process variations includes a variable resistor and a control transistor. The control transistor has a current from source-to-drain that is provided by a current mirror. The current mirror also provides a current to a variable resistor that is coupled gate-to-source to the control transistor. A control loop circuit measures the reference current provided by the current mirror and modifies the resistance value of the variable resistor in response. An external precision resistor is used to measure the reference current, and current variations as a result of process variations are reduced.

Abstract: A power supply circuit receiving several supply voltages on respective switches, at least one of the switches being a first PMOS transistor connected between one of the supply voltages and a common output terminal, this switch being associated with a second PMOS transistor connected between the gate of the first transistor and a power supply node maintained at the highest of the other supply voltages, with a third NMOS transistor, which is less conductive in the on state than the second transistor, connected between the gate of the first transistor and the ground, and with a fourth PMOS transistor having its source connected to the power supply line of the switch and its drain connected to ground via a current source, and to the gates of the second, third, and fourth transistors.

Abstract: A semiconductor controller device to control the operation of a semiconductor memory device. The controller device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. In addition, the controller device includes a voltage divider, coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. In addition, the controller device also includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.

Abstract: A semiconductor device having an internal voltage, signal timing, and logic current supply determined by a desired operating frequency is disclosed. The semiconductor device may include a register (1100) that may store a code value received externally during a code setting operation. A decoder (1200) may decode the code value and provide decoded signals (D1 to D4) to an internal power source circuit (1300), internal logic circuit system (1400), and a sense amp system (1500). The internal power source circuit (1300) may generate a power supply voltage based on the code value. The internal logic circuit system (1400) may be coupled to receive the power supply voltage and may generate a signal delay based on the code value. The sense amp system (1500) may be coupled to receive the power supply voltage and may have a operating current based on the code value. In this way, signal timings may be improved and power consumption may be reduced.

Abstract: A power supply converts a first direct-current voltage into a second direct-current voltage and outputs the second direct-current voltage. The power supply includes a reference voltage generating circuit for generating a reference voltage, a control circuit for controlling an output voltage in accordance with the reference voltage, and a short-circuit detecting circuit for performing an output short-circuit protection operation, when short circuiting occurs at the output, by detecting the occurrence of short circuiting and by decreasing the reference voltage so that the output voltage is decreased.

Abstract: A system including a component (e.g., a processor) with a clock and a thermal management controller that monitors a temperature in the system. The thermal management controller varies the component between different performance states (e.g., cycles the processor between a high and a low performance state) when an over-temperature condition is detected. The thermal management controller further throttles the clock of the component while in the low performance state until the over-temperature condition is removed.

Abstract: The present invention provides a technique for selective cancellation of the 2nd-order or 3rd-order nonlinearity of a transistor. Any nonlinearity is a function of the bias voltage of a transistor. In many cases, this function is such that, at a particular bias voltage, nonlinearity is zero. The invention provides a bias circuit that generates the optimum bias voltage for a transistor at which its selected nonlinearity is zero. Mathematically, the nonlinearity can be represented by a sum of multiple components where some components have negative sign. The components are proportional to the DC currents of the transistor at bias voltages differing by a small amount. The bias circuit includes bias transistors that are scaled versions of the main transistor. Each bias transistor generates a DC current representing one of the components. The currents are combined according to the signs of the respective components to form a DC signal proportional to the selected nonlinearity.

Abstract: A method and apparatus for providing a self-sustaining precise voltage and current feedback biasing loop. The present invention provides a circuit for initially biasing the bandgap and master bias current generator at startup. The feedback biasing loop has loop dynamics that are chosen such that the gain of the positive feedback loop is less than one so that the loop will not oscillate under normal operation after power-up.

Abstract: A power saving device for a wireless pointer includes a first resistor, a second capacitor, a signal generation circuit, and a bias control circuit including an n-type channel MOSFET having a drain connected to the signal generation circuit at a second node for driving the signal generation circuit, a switch having one end connected to a gate of the n-type channel MOSFET at a first node, a semiconductor means having an anode connected to the gate of the n-type channel MOSFET at the first node and a cathode connected to the positive terminal of the power source, and a first capacitor in series connection with the semiconductor means. When wireless pointer is inoperative, then the switch will open automatically to cause the leakage current of the reverse biased semiconductor means to charge the first capacitor. When the switch is closed, the first capacitor discharges completely so as to cut off the n-type channel MOSFET.

Abstract: A semiconductor device which operates an internal circuit based on first and second power supply potentials different from each other, comprising: a first determination circuit which determines whether or not said first power supply potential is higher than a first reference potential; a second determination circuit which determines whether or not said second power supply potential is higher than a second reference potential; a third determination circuit which determines whether or not said first power supply potential is higher than said second power supply potential; and a power supply voltage control circuit which operates said internal circuit based on said first and second power supply potentials if all the determinations by said first, second and third determination circuits are yes, and outputs a signal for initializing said internal circuit if the determination by at least one of said first, second and third determination circuits is no.

Abstract: An integrated semiconductor circuit has a potential detector for detecting a potential boosted by a high voltage generator. One terminal of a first capacitor is connected to a potential detection terminal via a first switching device, the other terminal thereof being connected to a reference potential terminal. A terminal of a second capacitor is connected, via a second switching device, to a first node at which the first switching device and the first capacitor are connected, the other terminal thereof being connected to the reference potential terminal. A third switch is connected between a second node at which the second switching device and the second capacitor are connected and the reference potential terminal. A clock generator generates clock signals to simultaneously and periodically turn on the first and the third switching devices whereas turn on the second switch periodically in an opposite timing for the first and the third switching devices.

Abstract: An apparatus and method for enabling hot swapping of programmable logic devices (PLDs) and boards containing PLDs is provided. If the hot swap capability is desired, a hot swap terminal on the PLD is set to facilitate a floating state on the input/output pad of the PLD. Further, the input buffer and the output buffer of the PLD are disabled. In one embodiment, a predetermined voltage is provided on the output terminal of the input buffer. In this configuration, the hot swap circuit eliminates any leakage current, ensures no static current occurs, and provides appropriate signals to the internal circuits of the PLD.

Abstract: A method and apparatus for local and global power management in a programmable analog circuit. Specifically, the present invention describes an array of programmable analog blocks. Each block contains current mirror circuits that are coupled in parallel fashion. The mirror circuits function to increase current consumption in a corresponding operational amplifier more current when enabled. Global power management is achieved by increasing and decreasing the bias voltage that is applied to the array. Global configuration bits select the bias voltage value, including electrically disabling the bias voltage from the array of programmable analog blocks. Local power management is provided by enabling or disabling mirror circuits with local configuration bits to adjust the performance in an operational amplifier contained within a corresponding programmable analog block. A microcontroller controls the local and global management of power through the programmable analog block.

Abstract: An integrated circuit system having a plurality of macros is provided. The integrated circuit system includes an external voltage supply input configured for supplying an external voltage to the integrated circuit; and a plurality of internal voltage supply generators, each of the plurality of internal voltage supply generators being connected to a respective macro of the plurality of macros and configured for receiving the external voltage via the external voltage supply input for generating an internal voltage supply for operating its respective macro. Each of the plurality of internal voltage supply generators includes circuitry for generating the internal voltage supply and circuitry for disconnecting at least a portion of its respective macro. The integrated circuit system can be applied to a semiconductor chip to save active or stand-by power. It can also be used to disconnect a defective portion of the chip and optionally replace it with a non-defective portion of the chip.

Abstract: In the present invention, an external power source supplied to an integrated circuit device is divided into a first external power source for the DLL circuit and a second external power source for circuits other than the DLL circuit. According to the present invention, it is arranged that power source noise generated in the second external power source cannot be transmitted to the variable delay circuit by utilizing the first external power source preferably for the variable delay circuit of the DLL circuit and even more preferably for its delay unit. Also, preferably, it is arranged that power source noise generated in the second external power source cannot be transmitted to the phase coincidence detection unit by utilizing the first power source for the phase coincidence detection unit in the phase comparison circuit of the DLL circuit.

Abstract: A high-voltage capacitive voltage divider circuit includes a high-voltage Silicon-On-Insulator (SOI) capacitor connected between a high-voltage terminal and a low-voltage terminal, and a low-voltage SOI capacitor connected between the low-voltage terminal and a common terminal. The voltage divider circuit also includes control circuitry for processing a signal generated at the low-voltage terminal in order to provide voltage-related control of a larger circuit employing the voltage divider circuit. The high-voltage SOI capacitor can include an oxide layer on a substrate, with a thinned drift region on the oxide layer, a thick oxide layer over the thinned drift region, and an electrode layer over the thick oxide layer, with the electrode layer and the thinned drift region forming capacitor plates insulated from each other by the thick oxide layer.

Abstract: A logic circuit has two internal voltage lines and includes additional upper and lower MOS transistors for coupling the external voltage supplies to the internal voltage nodes instead of using a single diode or transistor. These additional devices serve to clamp the internal voltages to a level that minimizes leakage current and maintains the data in the logic circuits.

Abstract: In an integrated circuit (IC) for providing an enabling signal (EN) to a converter, the integrated circuit (IC) includes a monitoring circuit (FET1, R2, D1, Io, M, S1) for providing a control signal (CS) in response to a level of a line voltage (Vline) on a first connection terminal (8) of the integrated circuit (IC), and a start-up circuit (FET2, Istrt_up, Vcc_strt-Lev, COMP, S2) for providing the enabling signal (EN) to the converter in response to the control signal (CS) and a generated voltage level (Vcc), the generated voltage level (Vcc) being generated in response to the level of the line voltage (Vline) on the first connection terminal (8). The monitoring circuit and the start-up circuit sense the level of the line voltage (Vline) only via the first connection terminal (8).

Abstract: The present invention includes a logic circuit block operated in synchronism with a clock signal, power supply switches, and a power supply switch control circuit for switch-controlling the power supply switches so as to provide an operation period shorter than the cycle of the clock signal. When the logic circuit block activated in synchronism with a clock signal has a frequency lower than a clock signal frequency, the logic circuit block does not develop a malfunction if capable of operation for each cycle of the clock signal at least only for a time interval defined by the clock signal frequency of the maximum operation speed. Since the supplying of operating power to the logic circuit block is cut off according to the clock signal frequency except for a period necessary for a circuit operation, leak current, that will flow through each turned-off transistor in the meantime, can be significantly reduced.

Abstract: Common circuit includes inactivation/activation circuits. Exclusive circuits include inverters IV3, IV4, IV5 and IV6 at the input portions thereof. When an SDR-SDRM is to be produced, inactivation/activation circuit outputs an inactivation signal DASL fixed to a ground voltage to exclusive circuit, while inactivation/activation circuit outputs a signal /OE inverted from an output enable signal OE to exclusive circuit. Inverters IV5 and IV6 in exclusive circuit then output a signal based on the signal /OE. Further, an N-channel MOS transistor and a P-channel MOS transistor in exclusive circuit are completely turned off, so that no through current flows from a power-supply node to a ground terminal in exclusive circuit. As a result, generation of the through current is prevented in an inactivated circuit.

Abstract: A high-speed current switch circuit of this invention has an n-type MOS transistor Q11 which switches and outputs a current, and a control circuit 11 which performs switching control of the MOS transistor Q11. In the control circuit 11, a source follower is formed by an N-type MOS transistor Q12 and a constant current source I2 which is a load on this transistor. A switch SW11 is connected to the MOS transistor Q12 to perform switching control of a current flowing through the MOS transistor Q12. The control circuit 11 includes a switch SW12 capable of grounding the gate of the MOS transistor 11. The source of the MOS transistor Q12 is connected to the gate of the MOS transistor Q11. Thus, even if a large current is caused to flow through the output transistor, the output transistor can be made to operate for switching at a high speed.

Abstract: A read circuit for a multibit memory cell is provided to convert a multi-level voltage output from the multibit memory cell into the desired number of binary levels. For example, if the multibit memory cell can be programmed to have four resistance levels, which produce four output voltages respectively, the read circuit is provided with two binary outputs. For additional resistance levels, and corresponding voltage levels, additional binary outputs may be provided.

Abstract: A power stealing circuit to charge a capacitor includes a passive electrical power channel. The passive electrical power channel has an input connected to an input signal and an output designed to be connected to the capacitor. An active electrical power channel is powered by the capacitor. The active electrical power channel has an input connected to the input signal and an output connected to the capacitor.

Abstract: A circuit (100) for accurately tuning the absolute values of multiple parameters in a VLSI circuit by reusing a single external resistor. In the illustrative embodiment, the invention includes a first circuit (10) for generating an accurate transconductance using a single external resistor; a second circuit (20) for generating an accurate current reference using the same external resistor; and a switching circuit (60) for alternately switching on and off the first and second circuits in order to share the external resistor. The switching circuit (60) includes several switches controlled by a digital counter for turning off portions of the circuit which are not in use. In the illustrative embodiment, the invention further includes a third circuit (40) for generating one or more additional accurate reference signals. The third circuit can generate an accurate internal resistance Rint, an accurate drain to source resistance of a transistor rDS, and/or an accurate internal capacitance Cint.

Abstract: A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.

Abstract: The integrated device comprises a PMOS transistor and a voltage selector having an output connected to the bulk terminal of the PMOS transistor. The voltage selector comprises an input stage supplying a supply voltage or a programming voltage according to whether the device is in a reading step or in a programming step; a comparator connected to the output of the input stage, receiving a boosted voltage, and generating a first control signal, the state whereof depends upon the comparison of the voltages at the inputs of the comparator; a logic circuit connected to the output of the comparator and generating a second control signal, the state whereof depends upon the state of the first control signal and of a third-level signal; and a switching circuit controlled by the first control signal, by the second control signal, and by the third-level signal and supplying each time the highest among the supply voltage, the boosted voltage, and the programming voltage.

Abstract: A voltage supply circuit capable of starting up a system while maintaining symmetry of a high level selection signal VH and a low level selection signal VL, not requiring a multistage charge pump circuit, and capable of reducing the number of parts of the system, wherein generation circuits of VD and VH are comprised of chopper type booster type switching regulators, and switching timings of a VH generation circuit 12 and a VL generation circuit 13 are controlled so that a virtual reference voltage VS (VD/2) and a middle point potential between VH and VL become the same.

Abstract: A method and apparatus for maintaining a stable power supply voltage. The method comprises using a power supply to provide power at a power supply voltage to a plurality of semiconductor devices. The power supply voltage is nominally at an optimal power supply voltage. A fast increase in the current can cause a drop in the supply voltage, since the high rate of change in current is through the package inductance. The power supply voltage is monitored. Further, a supplemental higher voltage power supply is used to boost the power supply voltage to substantially the optimal power supply voltage if the power supply voltage decreases by a threshold value.

Abstract: Method for increasing the supply voltage range of an integrated circuit. In the previously known methods, the electrical parameters of an integrated circuit are adapted to the intended supply voltage during manufacture. With the new method, the electrical parameters are adapted to the supply voltage by an integrated control circuit. This control circuit adapts or compensates the change of the electrical parameters caused by a change of the supply voltage by means of one or a plurality of switching elements.

Abstract: An integrated semiconductor circuit has at least two supply networks that are supplied independently of one another. The two supply networks include a first, load supply network, which is associated with a load circuit, and a second, driver supply network, which is associated with a driver circuit. Each supply network has a ground path with ground lines and a supply path with supply potential lines which are separate from the ground path. A compensating circuit is provided which alternatively couples the ground paths and/or the supply paths of the at least two supply networks to one another.

Abstract: A line driver supplied with a power supply voltage from a power supply uses whole or part of the power supply voltage to generate the output voltage if the input voltage is within a predefined range; loads at least one capacitor with at least one capacitor voltage; and uses whole or part of the at least one capacitor voltage in addition to whole or part of the power supply voltage to generate the output voltage if the input voltage is outside the predefined range.

Abstract: An apparatus comprising a first device and a second device. The first device may be connected to a first supply voltage. The second device may be connected (i) in series with the first device and (ii) to a second supply voltage. The first device is generally biased to provide enhanced noise suppression performance. The second device is generally configured to switch between the first and second supply voltages.

Abstract: The present invention provides improved slew rate control over a varied operating temperature range. A switching device (P1, N1) receives from a predrive circuit (56) a control signal that limits a slew rate of the switching device's output and also varies proportionally to the operating temperature. In this manner, the effect of temperature on the slew rate can be reduced.

Abstract: A low voltage reset circuit device without being influenced by temperature and manufacturing process is formed by a first low voltage reset circuit using an energy gap circuit to generate a reference voltage, and a second low voltage reset circuit using a threshold voltage of a MOS transistor as a reference voltage. The first low voltage reset circuit is used to provide an accurate low voltage reset property,. while the circuit only works as VDD>1.2V. When VDD<1.2V, the second low voltage reset circuit still works normally for providing the desired reset signal thereby covering the low VDD voltage range.

Abstract: A sensor 1 produces an output that changes linearly with absolute temperature. In response to the output, a reference voltage generator 13 produces reference voltages Vhigh and Vlow that change linearly with absolute temperature. A Schmidt trigger 14 compares the output signal from a sensor signal amplifier 12 with the reference voltages for performing on-off output. A sensor signal amplifier 12 with a temperature-independent amplification factor amplifies the output signal from the sensor 1 while performing offset compensation. A sensor signal processing circuit 2 is formed out of thin-film silicon disposed on an insulating substrate. The output from the sensor 1 undergoes accurate temperature compensation over a wide temperature range from a low temperature to a high temperature, achieving a reliable operation with accuracy at high temperature.

Abstract: A signal processing circuit can be used to select between a high bias current and good noise performance or a low bias current and poorer noise performance. The circuit comprises an input device having high impedance and low noise characteristics. A first current source provides a minimal current level through the input device. Additional current sources provide additional current through the input device to improve noise performance of the circuit. The additional current sources can be switched into the circuit when improved noise performance is required, and switched out of the circuit to conserve power when improved noise performance is not required.

Abstract: A common mode bias voltage generator apparatus and method includes a plurality of MOSFET-based transistors and a plurality of resistors configured and arranged to provide a half of a supply voltage with a predetermined low output impedance while using relatively little power and circuit area.

Abstract: A voltage sequencer includes an input terminal and an output terminal and a control element connected between the input an output terminals. A capacitive element is connected between the output terminal and a first voltage and a resistive element is connected between the output terminal and a second voltage. The control element selectively controls charging and discharging of the capacitive element such that, upon the voltage at the input terminal increasing from the first voltage to a nominal value, the output terminal voltage increases to a nominal value in a first predetermined period of time and upon the voltage at the input terminal decreasing from the nominal value to the first voltage, the output terminal voltage decreases to the first voltage value in a second predetermined period of time, the first predetermined period of time being different from, for example, substantially greater than, the second predetermined period of time.

Abstract: A bias circuit (200, FIG. 2) includes a first bipolar junction transistor (BJT) (240), which provides, to an external transistor (204), a biasing voltage (294) equal to the first BJT's base-emitter junction voltage plus a biasing voltage at the first BJT's base (244). A current multiplying mirror circuit (250) senses a fraction of the first BJT's collector current, and produces a current equal to the collector current. This mirror current flows through a second BJT (230). A voltage at the collector (232) of the second BJT is divided, producing the biasing voltage at the base (244) of the first BJT. This biasing voltage has a temperature coefficient with an opposite sign and a same magnitude as a temperature coefficient of the first BJT's base-emitter junction voltage, resulting in a near zero temperature coefficient for the biasing voltage (294).

Abstract: A reference potential is generated according to a potential Viconst output from a constant current control circuit, and an internal power supply potential is generated based on the reference potential. Fuse elements are provided in the constant current control circuit. Since the resistance value of a resistance circuit can be adjusted, an internal power supply potential can be adjusted in a wider range than that in a conventional circuit. Reduction in yield can be prevented in the case where a threshold voltage or the like is varied.

Abstract: A power supply controller having final test and trim circuitry. In one embodiment, a power supply controller for switched mode power supply includes a selector circuit, a trim circuit, a shutdown circuit and a disable circuit. The trim circuit includes a programmable circuit connection that can be selected by the selector circuit by toggling a voltage on an external terminal such as for example a power supply terminal, a control terminal or a function terminal of the power supply controller. The programmable circuit connection in the trim circuit can be programmed by applying a programming voltage to the external terminal. The shutdown circuit shuts down the power supply controller if the temperature rises above an over temperature threshold voltage. The shutdown circuit includes adjustment circuitry that can be used to test the shutdown circuit. The adjustment circuitry can adjust and reduce the over temperature threshold of the power supply controller.

Abstract: A method for reducing static power dissipation in a semiconductor device is provided. The method is characterized in that utilizing a simple control device connecting with a MOS device, serving for a drain voltage controller, instead of the conventional voltage supply directly connected with the drain. The control device comprises two input terminals and an output terminal. One of the two input terminals is connected with a voltage supply, the other of the two input terminals is connected with a control signal. The output terminal of the control device is connected to the drain of the MOS device. When the control signal is activated, the output terminal of the control device is grounded and thus the drain is grounded. Thereby, all of the possible leakage paths induced by the drain voltage are inhibited. While the control signal is un-activated, the output terminal of the control device provides a supply voltage to the drain.

Abstract: A sense signal IVOFF is generated by a power supply level sense circuit with an external power supply potential Ext.Vcc1 as the operating power supply potential to sense the level of an external power supply potential Ext.Vcc2. By suppressing generation of an internal power supply potential or fixing the internal node by the sense signal IVOFF, the through current at the time of power on can be reduced.

Abstract: A controlling device, such as an ASIC, supplies a clock signal to a controlled device, for example in a mobile phone or other portable battery operated electronic equipment. The presence or absence of a clock signal controls the power supply to the controlled device. This avoids power consumption in analog as well as digital circuits, when in a standby state, while only using a single output pin on the controlling ASIC.

Abstract: Reference voltage regulators and methods for integrated circuit output driver systems generate an initial supplementary current for the integrated circuit output driver system at the reference voltage for a predetermined time period in response to an output enable signal. Preferably, sufficient initial supplementary current is generated to compensate for an initial drop in the reference voltage that is generated by a reference voltage generator upon initial activation of the output driver system. Reference voltage generators according to embodiments of the invention may be included in an integrated circuit output driver system that is responsive to a reference voltage and to an output enable signal, and that varies in current drive capability in response to a current drive control signal. These embodiments of reference voltage regulators include a reference voltage generator that generates the reference voltage for the integrated circuit output driver system.

Abstract: A control device is provided for controlling a selector switch of a high voltage input having at least one cascode stage with MOS transistors. The control device includes a reference voltage generation circuit and a control circuit. The reference voltage generation circuit generates reference voltages from the high voltage input and provides one or more output voltages for the biasing of the MOS transistors of the cascode stage. The control circuit controls the reference generation circuit on the basis of a binary control signal, so as to either set the bias voltages at the level of the logic supply voltages to enable the switching of the selector switch even at low values of the high voltage input, or to enable the bias voltages to be set by the reference generation circuit.

Abstract: Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.